Vous êtes sur la page 1sur 1

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE work.bascule_D.

all; ENTITY serie_parallele IS GENERIC(N:integer:=9); port( clk,ES:IN bit; SP:OUT bit_vector(0 to 6) ); END serie_parallele;

ARCHITECTURE archi_con OF serie_parallele IS SIGNAL s:bit_vector(0 to N-1); COMPONENT bascule_D port(e,clk:in bit;n:out bit);END COMPONENT; ALIAS temp:bit_vector(0 to 6) IS s(1 to 7); BEGIN if ES='1' then premier:bascule_D port map(ES,clk,s(0)); autre: for i in 0 to N-2 GENERATE BOUCLE: bascule_D port m ap(s(i),clk,s(i+1)); END GENERATE ; if s(0)='0' then SP<=temp; else SP<=SP; end if; end if;

END archi_con;