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EE 8223 Analog IC Design

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Differential Amplifiers
The differential amplifier, a fundamental building block of analog IC design, performs the task of amplifying the difference between two input currents or two input voltage signals. The CMOS diff-amps discussed in chapter 24 are the source coupled pair, the source cross-coupled pair, and the current differential amplifier. The Source Coupled Pair M1 and M2 of Figure 24.1 makeup a source coupled pair. These transistors are biased by ISS provided via the M5-M6 current mirror. In this amplifier configuration, the current ISS of M6 in Figure 24.1 is often referred to as a tail current. In the source coupled pair, if 1 = 2, then
I SS = ( I D1 + id 1 ) + ( I D 2 + i d 2 ) = i D1 + i D 2

The differential input voltage, vDI, is given by

v DI = v I 1 v I 2 = v GS1 vGS 2 ,

and due to the symmetry of the circuit (M1 matched to M2, with both sharing one tail current),
v GS1 = vGS 2 = v DI . 2

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EE 8223 Analog IC Design

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Consequently, if vI1 = vI2 (vDI = 0V), then

I D1 = I D2 = I SS . 2

For both M1 and M2 are operating in strong inversion saturation, and we approximate each transistors drain current using the square-law equation
2 i D (vGS VTHN ) , then differential input voltage may be described by 2

v DI =

i D1 i D2 .

Using this result and the tail current expression provided above, the drain current of each transistor within the source coupled pair can be described by
i D1 I = SS 1 + 2
2 4 v DI 2v DI 2 I 4 I SS SS

I SS = 1 + v DI 2

2 2 v DI I 4I 2 SS SS

and
iD 2 = I SS 1 2 v 2 2 v4 DI DI 2 I 4 I SS SS

where = 1 = 2 and (again) we have assumed strong inversion saturation operation. . These drain current equations are no longer valid if, for example, M2 is forced into cutoff while M1 remains on. In this scenario, M1 would then conduct the entire tail current, ISS. Using the vDI expression previously provided, the maximum (positive) differential input voltage at which iD1 = ISS and M2 has just cutoff is given by
v DIMAX = 2 I SS .

An example iD1 versus vDI characteristic is shown in Figure 24.2 (see Example 24.1 of your text). The slope of this characteristic can be obtained by differentiating the iD1 expression with respect to vDI. If we neglect the vDI4 term within the radical, then
diD1 I SS dvDI 2 v 2 1 DI 2 I SS
1 / 2

2 v DI I SS

I SS 2

g m1 . 2

Note the dependence on the small-signal transconductance, gm1.

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Differential Amplifier with Current Source Load Adding another current mirror (M3-M4 in Figure 24.3) to the source coupled pair provides a differential amplifier with a current source load. Note that for balanced operation of this circuit (M1-M4 each have a drain current equal to half the tail current (i.e., ISS/2)), the drain voltage at the M4 (the output node) should be equal the drain/gate voltage of M3. This fact is often exploited in CMOS op amp design where the output quiescent voltage of the op amps input stage (like that shown in Figure 24.3) is used to bias the next stage (e.g., an output stage). Note also that body effect is present in the source coupled pair of Figure 24.3, but not in Figure 24.4 where a pMOS source coupled pair is used. Eliminating body effect, however, comes at the expense of added capacitance to the source-coupled node of the circuit. Now let us consider the common-mode range (CMR, or sometimes referred to as ICMR for input common-mode range) of the source coupled pair differential amplifier. CMR describes the allowable applied voltage range common to both input terminals (gates of M1 & M2) through which the source coupled pair and tail current transistors will remain in saturation. For example, consider the source-coupled pair of Figure 24.6 where the input terminals have been tied together (hence, vI = Vcm = common-mode voltage).

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The minimum input voltage (see Figure 24.6) that allows M1-M2 & M6 to remain in strong inversion (for example) saturation is given by
v IMIN = Vcm, min = VGS 1 + V DS 6, sat + VSS
v IMIN = I SS 2 I SS + VTHN + + VSS 1 6

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At this minimum common-mode input voltage, M6 has barely enough VDS voltage to remain in saturation. For the maximum common-mode input voltage, M1 & M2 are on the verge of entering the triode region,
v IMAX = Vcm, max = V DD V SG3 V DS1, sat + VGS 1 I v IMAX = VDD SS + VTHP 3
v IMAX = V DD

I SS + I SS + VTHN 1 1

I SS VTHP + VTHN 3

Based on this result, a nMOS source coupled pair might allow a commonmode input voltage near, or possibly above, VDD, depending on the values of V3 and the threshold voltages. In this circuit, the body effect on M1 & M2 can help extend the upper limit of ICMR.
I SS + VTHN + 1 2 I SS I + V SS ICMR V DD SS VTHP + VTHN 6 3