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INTRODUCTION

Transistor scaling, a major driving force in the industry for decades, has been responsible for the dramatic increase in circuit complexity. Shorter gate lengths have required lower drain voltages and concurrently lower threshold voltages. Recent CMOS evolution has seen a dramatic reduction in operating voltage as transistor size is reduced. This was due to the maximum field limit on the gate oxide needed to maintain good long-term reliability. Proper selection of the gate material can produce low threshold transistors with off-state performance parameters equivalent to high threshold devices. The Buried Channel Accumulation device, currently being used for p-type transistor processes has the Fermi level at a considerable depth from the gate thereby making it difficult to shut the device off. Attempts to bring the Fermi level up result in severe degradation of device performance. Need for optimization of existing BCA technology arose and Thunderbird Technologies, Inc. delivered! The incredible: Fermi-FET. The Fermi-FET technology brings the Fermi level nearer to the gate. This

technology merges the mobility and low drain current leakage of BCA devices as well as the higher short channel effect immunity of SCI devices Fermi-FET technology can lead to significant improvement in circuit performance, layout density, power requirements, and manufacturing cost with only a moderate alteration of traditional MOSFET manufacturing technology. This technology makes use of a subtle optimization of traditional buried channel technology to overcome the known shortcomings of buried channel while maintaining large improvements in channel mobility.

Fermi-FET can optimize both the N-Channel and P-Channel devices with a single gate material, provided the work function is near the mid-range between N and P-type polysilicon. Materials that have been used in MOSFET technology with a suitable work function include Tungsten, Tungsten Silicide, Nickel, Cobalt, Cobalt Silicide, P-type GeSi and many others. There is about a 30% reduction in junction capacitance relative to traditional MOSFET devices. This fact alone gives a significant speed advantage to the Fermi-FET in large scale circuits. The total speed improvement produced by both the lowered threshold and lowered gate and junction capacitances is very substantial. The impact of lowered threshold voltages via work function engineering can be illustrated by the large-signal transient response of two inverter structures. A comparison of conventional CMOS and metal-gate Fermi-FET structures is performed. It is seen that the Fermi-FET inverter displays significantly improved rise and fall times compared to the MOSFET. The different delay characteristics are evident. It is seen that the Fermi-FET inverter displays significantly improved rise and fall times compared to the MOSFET . The individual device DC characteristics were already well-known from the device simulations. For each inverter, the supply voltage was ramped up to Vd with a delay sufficient to allow the circuit nodes to settle to their initial DC state with the input low. The input was then pulsed high, then low; again with a delay time long enough to guarantee all nodes reach steady state. The corresponding outputs obtained give a comprehensive view of the device performance as compared to the traditional technology and thus acts a primary assessment of the feasibility of the new technology in lieu of existing ones.

Figure (a) The output of the mixed-mode simulations is shown in the figure. Even at 0.4 mm gate length the low threshold Fermi-FET is almost twice as fast as the MOSFET in this simple circuit. Simple circuits such as this underestimate the benefit of the lowered capacitance associated with the source/drain junctions, but they virtually ignore the capacitance associated with the extended wiring in large circuits. The Fermi-FET is the emerging technology in the ever-expanding empire of electronics circuits and devices and is slated to be crowned the king in foreseeable future.

THE TRANSISTOR STRUCTURE


The Fermi-FET is a unique patented variation of the broad class of devices known as Field Effect Transistors (FET). Although the transistor operation differs markedly from standard MOSFET devices, the structure of the new device has many similarities, thus permitting easy conversion of existing CMOS process lines to production of Fermi-FET transistors. BASIC FET The basic principle behind the working of a Field Effect Transistor is the conducting semi-conductor channel between two ohmic contacts; source and drain. The gate terminal controls the channel current and is a very highimpedance terminal. The FET is thus a three terminal, unipolar device. The name field effect is due to the fact that the current flow is controlled by potential set up in the device by an external applied voltage. There are two types of FETs JFET and MOSFET. The FET of interest here is the MOSFET. The N-channel MOSFET has two lightly doped n- regions diffused into a heavily doped p-type substrate; separated by 25 m. These n-regions act as source and drain. An insulating layer of is grown over the surface. Metal contacts are made for the source and drain. A conducting layer of metal will act as the gate, overlaying the insulating layer over the entire channel region. Due to the presence of the insulating layer, the device is called Insulated Gate FET (IGFET) or Metal Oxide Semiconductor FET ( MOSFET).

Modern Complementary MOS (CMOS) processes incorporate polysilicon gate structures less than 0.25 micron long, with the most common process being 0.15m.

SURFACE CHANNEL INVERSION DEVICES

Most short channel CMOS processes create SCI type transistors for both P and N-Channel devices. This decision has evolved, as line widths attained shorter dimensions primarily due to the reduced short channel effect sensitivity of the SCI devices over the BCA transistor, traditionally used for the PMOS. Its because of the widely known control problems with deep buried channel transistor (BCA) technology that most short channel processes incorporate both n-type and p-type polysilicon gates to create surface channel inversion (SCI) devices for both transistor polarities. SCI STRUCTURE

Figure 1 A cross-section drawing of an N-Channel SCI MOSFET transistor. The polysilicon gate would be degeneratively doped n-type. The

drain extension region is typically utilized to reduce short channel effects (SCE). Figure 1 depicts the main features of a short channel NMOS SCI device. Certain other refinements aimed at reducing short channel effects such as pocket implants, SSR well, graded channel, and elevated diffusions have been ignored for simplicity. SCI OPERATION The operation of surface channel transistors is relatively simple to envision. Figure 2 shows an enlargement of the channel region with the source end drain extension from Figure 1. As the gate electrode is biased from zero (fully off) toward the threshold voltage, the initial charge on the gate drives free holes in the substrate away from the gate region.

Figure 2A close-up of the channel region in Fig. 1 near the drain side of the gate. The gate electrode has a positive bias but is below threshold voltage. The silicon depleted of mobile carriers is shown as a white area. The arrows represent the vertical field direction.

The combination of depletion charge on the gate and induced space charged depletion region in the substrate create a vertical electric field through the dielectric and into the substrate. This impedes carrier movement and hence decreases carrier mobility. This is a major disadvantage of SCI transistors affecting device performance to a large extent. Device scaling has forced the gate oxide to become ever thinner and the average doping in the well region to increase. These lead to reductions in carrier mobility; the ease with which charges can move through the transistor producing drive current. If the gate bias is just above the threshold, then the depletion region has reached its maximum depth and a thin region of inverted silicon (n-type carriers in ptype silicon) exists just below the gate oxide. As the gate bias continues more positive, the threshold voltage is reached. At this point the depleted silicon region under the gate stops expanding and additional charge on the gate results in free conduction carriers from the diffusion moving to the region under the gate. It is these carriers that are responsible for the output current of the transistor.

PROBLEMS WITH SCI It should be noted that for an SCI device, good short channel performance requires high channel doping to counteract short channel induced leakage and threshold drop, but at the same time needs a low threshold voltage due to the

low operating voltages of short channel processes. This dictates the thinnest possible gate oxide must be used. The thin gate oxide and high vertical electric fields have caused a new challenge not previously large enough to cause difficulties; polysilicon depletion. Polysilicon depletion occurs when free carriers are swept away from the bottom of the poly gate due to high vertical fields. In an SCI type of device, this occurs when the transistor is fully turned on. As can be seen in Figure 3, this depletion causes the gate dielectric to appear thicker than it actually is, reducing transistor performance. In summary, SCI devices, the current device used in many short channel applications, have three major design difficulties: regions. High Capacitance As SCI devices shrink, the higher substrate doping

causes increased parasitic junction capacitance around the source and drain

Lowered Channel Mobility Higher channel doping and increased

vertical electric field make it more difficult for carriers to move across the channel. Polysilicon Depletion The high charge on the gate can cause polysilicon

depletion to occur, lowering the transistor drive current.

BURIED CHANNEL ACCUMULATION DEVICES

At longer channel widths, the BCA architecture was widely used for the PChannel transistor in CMOS processes. This was primarily done because the BCA transistor would use the same n-type polysilicon gate used by the NChannel device, greatly simplifying the process. Recently it became apparent to most manufacturers that the BCA architecture was incapable of scaling to the very fine line widths in development today. The added process complexity of using both n-type and p-type poly was offset by the better SCE immunity of the SCI transistor. BCA STRUCTURE

Above figure shows an N-Channel BCA transistor. Note that the polysilicon gate would be doped p-type. The drain and source extensions are connected by an n-type channel layer. An N-Channel BCA device would be built with the structure shown in figure. The polysilicon electrode is p+, and there is an n-type channel between the source and drain. The depth of the channel is minimized to reduce short channel effects (SCE).

BCA OPERATION Although the structure of a BCA device is very similar to a SCI transistor, the operation of the two is markedly different. This is due to the presence of the p-n 9

junction formed by the channel and well regions abutting. As in all p-n junctions, free carriers diffuse across the junction until the retarding field, due to the ionized donor and acceptor atoms, causes the drift and diffusion flows to equalize. This field leads to the built-in potential of p-n junctions. The magnitude of this built-in potential is determined by the doping density of the silicon on both sides of the junction. This potential causes carrier depletion on either side of the metallurgical junction. The widths of these depletion regions are proportional to the relative doping of the p and n regions. In traditional BCA architectures, the channel region is more highly doped than the well region beneath it. The arrows in figure below show the vertical electric fields present with the gate electrode at zero bias.

The dashed line depicts the location of the p-n junction and depleted silicon is shown as a white area. The arrows represent the vertical field direction. Here the junction potential is not high enough to fully deplete the entire channel region. There is another field due to the gate work function that also depletes the surface part of the channel region. This potential also causes some depletion of charge near the bottom surface of the gate.

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ADVANTAGES OF BCA BCA devices have a significant advantage over SCI devices in terms of channel mobility. This is due to two reasons. First, the vertical field within the channel is substantially lower in a BCA

device. This is because the gate does not have to deplete majority carriers away from the interface to form a channel. The gate supplied vertical field is due only to the mobile conduction charge. Second, improvement in channel mobility because this architecture can

be made with a significantly lower total doping density in the channel. PROBLEMS WITH BCA At longer channel widths, the BCA architecture is superior to surface channel architectures. The improved channel mobility leads to higher saturation current, the lower substrate doping can dramatically reduce the parasitic diffusion capacitance and the wider channel lowers the gate capacitance at equivalent oxide thicknesses. Problems with this type of transistor appear as the channel length and operating voltage decrease. Transistor scaling, a major driving force in the industry for decades, has been responsible for the dramatic increase in circuit complexity. Shorter gate lengths have required lower drain voltages and concurrently lower threshold voltages. The problem with the BCA is that the channel turns on at the bottom of the conducting channel, far removed from the gate electrode as shown in Figure 7. With the initial conduction far from the surface it can be difficult to shutoff the device.

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FERMI FET
SCI and BCA transistors make up the broad family of buried channel transistors. The Fermi-FET transistor is a specific optimization of buried channel transistors. A Fermi-FET transistor occupies the region near the crossover from BCA to SCI devices. This allows a Fermi-FET to have the mobility and subthreshold swing advantages of a BCA device while maintaining the short channel effect immunity of a SCI or SCA transistor.

Figure above shows the S parameter or Subthreshold Swing of long channel transistors using several combinations of substrate and channel doping densities. Regardless of the doping levels used, there is a minimum S value where the device transitions between BCA and SCA operation. This is the Fermi-FET region. This minimum value corresponds to the point where the device threshold is roughly equal to the Fermi-potential splus the built-in potential of the junction. 12

The S-chart serves as a means to tune the profiles for maximum Fermi-FET performance.

Even with a much higher Vt , the Fermi-FET device outperforms a similar surface channel device.The linear graph clearly shows the much improved mobility of the Fermi-FET. Both devices have identical diffusion profiles and contact spacing. FERMI-FET OPERATION Figure (a) depicts a Fermi-FET transistor analogous to the BCA device. The difference being that the doping in the channel region is lowered (or the depth is decreased) such that the depletion region from the p-n junction would extend to the region very near the surface of the silicon.

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Figure (a), A close-up of the channel region of a Fermi-FET type of transistor. This drawing is similar to the BCA. The dashed line depicts the location of the p-n junction and depleted silicon is shown as a white area. With the junction depletion using most or all of the dopant in the n-channel, an interesting aspect of SCA devices occurs. There is a built-in potential associated with a gate electrode added above the oxide. Movement of charge between the polysilicon gate and the silicon must balance this potential, but there is not enough charge left within the channel region to deplete and satisfy the potential difference. Figure 16 illustrates how this extra charge movement is accomplished in a SCA device. Once all mobile electrons are depleted from the channel, additional potential increase is created by moving holes from the substrate into the formally n-type region, creating a volume inversion or a psuedo p-type region.

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Figure 16 A simulation depicting the location and density of mobile charged carriers in the substrate of a Fermi-FET transistor. Electrons and hole concentrations are shown according to the scale at left. Only concentrations above ni are shown so the white regions designate depleted silicon. The Gate and Source are at zero volt bias with the Drain electrode at 1.5 V (right side). This volume inversion is unique to the SCA (and Fermi-FET) type of device. It is responsible for the lack of short channel roll-off usually seen in BCA type transistors. With the gate potential at zero, the drain field cannot reach the source diffusion and cause carrier injection. As the gate bias is increased slightly, the excess holes are swept away from the interface.

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The current flow while at the surface near the source is not tightly bound to the interface by a strong vertical field as in a SCI device. At the drain end of the channel, the current flow actually moves significantly away from the interface due to the relatively high drain bias. The low vertical field is one of the main contributors to the significant increase in channel mobility of this type of transistor. At this gate bias, the channel region contains many more free electrons than holes, but the electron concentrations are still far short of the ionized donor atom population. Charge neutrality has not yet been reached, so no carrier accumulation in the channel has occurred. The threshold of SCA or Fermi-FET is defined as the point at which the channel carrier concentration exceeds the net chemical dopant concentration; the onset of strong accumulation.

APPLICATIONS
The Fermi-FET device developed and patented by Thunderbird Technologies Inc. can provide significant performance advantages relative to conventional CMOS technologies for a variety of products. The points below are a brief overview of several product areas that are predicted to benefit most from the Fermi-FET technology. In general, the Fermi-FET will directly benefit performance-driven digital products, due to the higher drive current and lower capacitances inherent in the

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device architecture. The Fermi-FET has also been evaluated with respect to some of the other considerations that impact technology decisions, such as process sensitivity, leakage, power consumption, temperature and noise characteristics, scalability and reliability. In addition, the costs, in terms of money, human resources and time-to-market constraints must be carefully weighed when considering any new technology introduction. Considering these issues, the following product groups are expected to benefit in terms of market differentiation and competitive advantage. DSP - Due to the increasing ASSP nature of the DSP market, in contrast

to the MPU market, designs are introduced based upon specific market demands. This allows easier introduction of a new device or process technology into the product line. An existing CMOS line may be run in parallel with a new FermiFET line to support existing products, while existing products are redesigned, if feasible, and new products are being introduced. The technical benefits to be derived from the Fermi-FET technology for DSP products are expected as follows:

a)

The Fermi-FET offers significantly higher performance due to lower

intrinsic device capacitances and better drive current. In the highly competitive DSP market, this is particularly important. b) Considering analog content, the Fermi-FET should offer lower noise than conventional CMOS, due to its buried-channel nature. This has not been verified experimentally yet, but it is reasonable to expect based upon the device structure, and its physics of operation.

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c) Temperature characteristics of the Fermi-FET have been measured and typically exceed those of conventional surface-channel devices, in terms of current drive degradation with temperature. MPU - For standard MPU products which are more performance-driven,

rather than price- driven, the Fermi-FET must be introduced at an appropriate point in the technology roadmap. The MPU products require the highest performance possible, but are also very sensitive to time-to-market requirements and need design information which is timely and as accurate as possible. Technology scalability is also extremely important. Scaling the device to very deep-submicron linewidths, while retaining the performance advantages at longer linewidths is possible. Thunderbird is currently working on methods to extract Fermi-FET design information from measured data and/or simulations.

MCU - For product applications such as these which may be embedded,

are already established as catalog parts and are more price-driven, rather than performance-driven, the Fermi-FET can provide nearly a generational leap in performance with very little (if any) investment in retooling required. It has been Thunderbird's experience that it is often possible to reduce process complexity, due to the lack of the LDD in the device structure, for example, hence lower the manufacturing cost. Analog bolt-ons to MCU parts will also enjoy the same benefits as the DSP products. Logic/ASIC/FPGA/Gate Array - General purpose logic will also benefit

from the Fermi-FET's higher performance, of course, but the cost of porting such low margin products to a new technology should be carefully considered. The most likely candidates will be the ASIC, and perhaps gate array products. For these applications, the stream of designs may be simply switched over to the new

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technology once it is qualified. Gate array base levels would need to be redesigned, to take advantage of the expected performance increase. It would be reasonable to expect to be able to shrink die size based upon the device performance, for a given linewidth. This of course leads to lower manufacturing costs. SRAM - As with the general-purpose digital applications, SRAM would

clearly benefit from the reduced device capacitances and higher drive current. Due to the higher performance, it would be possible to shrink cell and I/O dimensions, and subsequently decrease the die size. As with ASICs and gate arrays, decreased die size means lower costs. This is in addition to the benefits derived from increased yield due to device stability with manufacturing variations. Analog/Mixed-Signal - Telecom, data conversion and networking

products would all benefit from the characteristics mentioned in the DSP bullet. To date, no Fermi-FET analog blocks have been fabricated by Thunderbird, but the expectations of lower noise, higher transconductance with lower device capacitance, hence higher fT are reasonable based upon current device physics knowledge and simulated characteristics. Power MOS - This is an area Thunderbird plans to explore in the near

future. Due to the buried nature of the channel, for longer channel length devices, the current density capability of the Fermi-FET is greater than surface-channel CMOS. Due to the higher mobility experienced by the carriers in the channel, the Rdson at a given geometry will be lower than conventional surface-channel devices as well. This allows either die shrinks or increased drive capability for applications requiring a very low output impedance, such as motors and actuators.

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Of course the list above is not exclusive, and there are many more areas which could benefit from a high performance device architecture such as the FermiFET. Other advantages may surface as well, particularly with respect to the path-breaking low-threshold technology.

CONCLUSION
The Fermi- FET is the latest in emerging revolutionary transistor technologies. Initial experiments appear to affirm the academic work that postulates that the Fermi-FET architecture maintains significant advantages over SCI devices at least through gate lengths of 50 nm. In addition, Fermi-FET produces dramatic reductions in gate tunneling currents through very thin gate dielectric layers. These features and the inherent advantages of the Fermi- FET over the existing traditional transistor technologies renders it the most promising of all evolving developments. Finally, as the Fermi-FET continues to be scaled, the technology will provide a sustainable competitive advantage.

BIBLIOGRAPHY

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1. www.thunderbirdtechnologies.org 2. www.wikipedia.com 3. www.scribd.com

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