IDFF 08-03 Full

Implementation of
Digital Fortress On FPGA

Manojkumar Parmar [03BEC060]
Pratik Shah [03BEC093]
Gaurang Upasani [03BEC115]
Guided by:
Prof. N. P. Gajjar
Associate Professor, EC, IT, NUST
Detailed Definition
• Converting the Algorithm of digital fortress
into equivalent VHDL
− Designing : VHDL code
− Verification : Testbench
− Implementation : FPGA
− Testing : Real-Time
08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 2/69

Thursday [ IDFF / Presentation / Major Project / 01 / 8-2 ]
Motivation behind choosing
Definition
• The main source of motivation behind the
development of the algorithm is the famous
novel “DIGITAL FORTRESS” written by
DAN BROWN
• The authors are not satisfied with the existing
methods of encryption systems
• To serve the goal of perfect secrecy
• To provide perfect encryption at low cost and
with ease of hardware realization

Objective of project
Design a protocol for security in
network in terms of data encryption
and to implement it in hardware
(FPGA) for low power consumption
circuit and low computation power for
reliable communication over network

Unique features
• Design, Analyze & Verify an Encryption
system which is immune to all kind of
existent attack
• Designing of less complex algorithm for easy
implementation
• Design & implementation of low power
consumption & low computation power
hardware on FPGA
• Make it compatible for existing protocol stack

Outcomes of the project
• Software for this algorithm with
inbuilt analysis
• Hardware in terms of prototype
chip using FPGA

Project Affiliation
• FAER & MOTOROLA Scholar Contest -2007
The project is one of the 22 projects selected by a
group of experts for the Motorola Scholar Contest-
2007 from all over India, and it is the only project
selected from Gujarat
• DSP/VLSI Group
The required resources and guidance is being
provided by the DSP/VLSI Group of Institute of
Technology, Nirma University

Project Scheduling
& Progress
Phase Planning of Project
• Phase I : Study & Review of Algorithm {Completed}
• Phase II : MATLAB Simulation {Completed}
• Phase III: Implementation of algorithm in VHDL
− Phase III-A: Designing {94% progress}
− Phase III-B: Verification
− Phase III-C: Implementation on FPGA
− Phase III-D: Testing
• Phase IV: Advancement

Gantt Chart of Phase III-A : Designing

Performance Against Schedule for
Phase III-A : Designing
Design 55 days 94% 2-Jan-2007 12-Mar-2007
Segmenter 15 days 100% 2-Jan-2007 19-Jan-2007
Serial-In-Parallel-Out 5 days 100% 2-Jan-2007 8-Jan-2007
Parallel-In-Serial-Out 5 days 100% 2-Jan-2007 8-Jan-2007
Timing module 10 days 100% 8-Jan-2007 19-Jan-2007
Unique Shifter 20 days 100% 8-Jan-2007 1-Feb-2007
Multiplier 5 days 100% 8-Jan-2007 13-Jan-2007
Rotator 5 days 100% 13-Jan-2007 19-Jan-2007
Internal Control Module 10 days 100% 19-Jan-2007 1-Feb-2007
Permuted Xor 10 days 100% 19-Jan-2007 1-Feb-2007
Mutation Unit 5 days 100% 26-Jan-2007 1-Feb-2007
Internal Control Unit 10 days 100% 19-Jan-2007 1-Feb-2007
Control module 30 days 88% 1-Feb-2007 12-Mar-2007
Timing module 20 days 100% 1-Feb-2007 27-Feb-2007
Status word module 10 days 100% 1-Feb-2007 14-Feb-2007
Control word module 15 days 100% 14-Feb-2007 5-Mar-2007
Interrupt module 10 days 70% 27-Feb-2007 12-Mar-2007
Mode operation module 5 days 20% 5-Mar-2007 12-Mar-2007

Work Load Distribution for Phase III-A
Manojkumar Parmar 270 hrs
Timing module Completed 60 hrs
Mutation Unit Completed 30 hrs
Interrupt module 70% progress 60 hrs
Pratik Shah 300 hrs

Serial-In-Parallel-Out Completed 30 hrs
Rotator Completed 30 hrs
Internal Control Module Completed 60 hrs
Status word module Completed 60 hrs
Control word module Completed 90 hrs
Mode operation module 20% progress 30 hrs
Gaurang Upasani 300 hrs
Parallel-In-Serial-Out Completed 30 hrs
Multiplier Completed 30 hrs
Internal Control Unit Completed 60 hrs
Interrupt module 70% progress 60 hrs
Phase I:
Study & Review of
Algorithm
Status : Completed
Need Of Encryption
• Republic of Korea is trying to attack on
Economy of Federal Government……..
Emergency Report From

-David Kissinger,
Korea to Pentagon without
Encryption on Internet Director,
CIA, Korea
• Privacy of Communication
If Message
• Security & Reliability trapped then
???
• QOS [Quality of Service]
Basic Block Diagram of Encryption

Terminology of Encryption
• Original Data → Plaintext
• Encryption Key → Cipher Key
• Encrypted Data → Cipher text
Plaintext: MOTOROLA 2007/ZONE 09

Key: 2 Function which gives position value of data
Function: ‫(ֹּל‬Ciphertext)
‫ֹּל‬ = ‫(ֹּל‬Plaintext)
‫ֹּל‬ +2
Ciphertext : OQVQTQNC 4229/BQPG 21

Basics of Encryption
• Symmetric {Same Key for Decryption}
1. Symbol Language (Substitution)
2. Caesar Cipher (Shifted)
3.Affine, Vigenère, Hill (Shifting, Adding)
4. SP Cipher (Substitution & Permutation)
• Asymmetric {Different Key for Decryption}

• Cryptanalysis {Decrypt the message without
Knowing the key}

Previous Work & Criticism
• Vernam’s OTP
Assumption
¾Unique key for each message
¾Length of key is same as data
¾Prior to decryption key must be known
Functionality : Normal XORing
Issues
¾Transportation of large key
¾If same key is used then difference between two
messages easily found out & analysis would be easy

Previous Work & Criticism (contd…)
• Random Rotating XOR
Assumption
¾Random rotator is perfectly random in nature
¾KDC distribution is flawless
Functionality :
¾Normal XORing with Randomly rotated key
Issues
¾Requirement of Key Distribution Center
¾Applicable to small network such as LAN

Unique Features of Digital Fortress
• Enhance & Modified version of Vernam’s
OTP (One Time Pad)
• Symmetric Key Algorithm
• Two key (Finite Length, Small)
• Blend of Linearity & Non-linearity
• New Functions (Primitive Format)
• Reversible Algorithm

Flow Diagram for Encryption

Segmenter
• Functionality: Divide the single array of data in to
desired size block length
• Input: 1-D Array of Character {[1,M],[M,1]}
• Output: 2-D Array of Character [ M/N,N]
• Control Parameter: Block Length (N)
• Assumption:
− Each character is represent by a byte
− (M + P) = B x N, where B & P any integer Number, P is
for Padding

Unique Shifter
• Functionality: Generate unique key with the help
of Rotating Key Function by rotating alphanumeric
key
• Input: Two key {Alphanumeric, Numeric}
• Output: 2-D Array of Unique Key [ M/N,N]
• Control Parameters: Block Length (N), Power
Coefficient & Multiplier Coefficient

Unique Shifter [R.K.F.] (Contd…)
• Functionality:
− Generate an Algebraic Equation for each block
− Power & Multiplier Coefficient are dynamic & controlled
by another function
− Algebraic Equation provide amount of rotation for key
− Alphanumeric Key is rotated bitwise
• Input: Alphanumeric
• Output: Bitwise Rotated key
• Control Parameter: Multiplier Coefficient of
Previous block

Permuted XORer
• Functionality: Modified-XOR the segmented block
with key after permuting the key & then add odd
number in to it
• Input: Block of segmented data & Key
• Output: Encrypted data block
• Control Parameters: Permutation Matrix, Shifter,
Parameter for Modified XORing

Permuted XORer (Contd…)
[Modified XORing]
• Functionality:
− XOR the key with data
− Divide the data in two block
− Perform XOR on one block with other & put other block
according to control parameter
• Input: Data & Key

• Output: Intermediate Encrypted data
• Control Parameters: Half decision, Cross/Normal,
Simple/Mirror

Bit Distributor
• Functionality: Distribute ciphertext byte over a
pixel of an image
• Input: Ciphertext & Raw Image
• Output: Ciphertext dumped Manipulated Image
• Control Parameter: Bit Distribution Coefficient

Algorithm for Decryption
• Encryption algorithm is reversed with
certain modification
• Algorithm is not Fully reversed for
decryption only part of it is reversed
• Reversed parts: Segmenter, Bit Distributor
• Inverse function needed for reverse part
• Decryption is easier, if encryption is known

Protocol
• Requirement of control Function Size(bit)
parameter for Unique Rotating Key 24
Decryption Rotating 24
• Transfer this parameter Permutation
with secrecy so it can’t Modified 3
be utilized by intruders XORing
Rotating Odd 5
• Systematic approach is
Shifter
required in terms of
protocol Bit Distribution 24

Limitations
• Dynamic Control Parameters
• Change in Parameter
• Raw image for dumping the data
• Redundancy due to dumping (1/3)
• Synchronism for large amount of data
• Formatting of Ciphertext for transmission

Phase II:
MATLAB Simulation
Status : Completed
Simulation Parameters
Parameter Value
Input File (size) Plaintext.txt (4 kB)
Output File (size) Ciphertext.dat (4 kB)
Alphanumeric Key asdfgbnmv
Numeric Key 231253
Shifter 23
Permutation Matrix [ 2 1 3 7 8 5 4 6]
Right / Left 1
Mirror / Simple 1
Cross / Normal 1

Graphical Representation in 2-D
Image Format
Value of a
character in Size : 4 kB
byte format 512 Rows &
8 Columns
Each element in
byte format

Histogram Representation for
Probability Distribution Function

Spectrum Representation for
Frequency Content & Information

Phase III:
Implementation of
algorithm in VHDL
Phase III - A:
Designing
Status : 94 % progress
Software Hardware
• Xilinx ISE 6.1i • Virtex
• Xilinx ISE 6.3i − XCV300 -6 pq240
− XC5VLX30 -3 ff676
• Xilinx ISE 7.1i webpack
• Spartan
• Quartus II 5.1 − XC2S50 -6 pq208
− Nios II IDE
− XC2S100 -6 pq208
• Syniplify 8.8 Evaluation
• Stratix II
− Identify 2.4.1
− EP2S60F672C3
• Xilinx ISE 9.1i Webpack

Segmenter – SIPO Unit
• Design specifications
− Input
• d_in
− Output
• e_clk
• op_en
• d_out (63 downto 0)
− Control Parameters
• rst •d_en
• clk •d_req
• op_ack •d_ack

Devices Devices
Title Spartan Virtex Title StratixII
Logic Utilization ALUT(USED/UNAVAILABLE) 148/1
Slice FlipFlop/Latches 72/70 72/70 Combinational without Register 73
4 Input LUTs 149 149 Combinational with Register 75
Logic Distribution Register/ Total Register 0/75
Occupied Slices 115 115 ROUTING CELL 0
4 Input LUTs 157 157 I/O PINS / CLOCK 73/4
Bonded IOB 70 70 ALM 75
Gate Count 2108 2108 LAB 11

Operating Frequency Operating Frequency
(MHz) 131.492 132.837 (MHz) 321.34

Segmenter – PISO Unit
− Input
• d_in (63 downto 0)
− Output
• d_out •op_ava
• d_load •t_ov
Control Parameters
• rst •d_ava
• clk •op_ack

Devices Devices
Slice FlipFlop/Latches 73/5 73/5 Combinational without Register 14
4 Input LUTs 87 87 Combinational with Register 11
Logic Distribution Register/ Total Register 62

(MHz) 107.875 109.6 (MHz) 110.35

Unique Shifter – Rotator Unit
− Input
• B_INPUT (63 downto 0)
− Output
• B_OUTPUT (63 downto 0)
• SEL (5 downto 0)
• CLK
• RESET

Devices Devices
Slice FlipFlop/Latches 128/0 128/0 Combinational - Register 160
4 Input LUTs 387 387 Combinational + Register 64

(MHz) 217.912 220 (MHz) 500.00(R)

Unique Shifter – Control Unit
− Input
• i (15 downto 0)
• q (3 downto 0)
− Output
• n (5 downto 0)
• a (3 downto 0)
• b (3 downto 0)
• c (3 downto 0)
• RESET

Devices Devices

(MHz) 159.231 164.954 (MHz) 297.44

Permuted XORer – Mutation unit
− Input
• din (7 downto 0)
− Output
• Dout (7 downto 0)
• half_decision
• normal_cross
• Simple_mirror

Devices Devices

(MHz) 90.26 88.19 (MHz) 109.027

Permuted XORer – Control unit
− Input
• Key0:7 (7 downto 0)
• da0:7 (7 downto 0)
− Output
• op0:7 (7 downto 0)
• Per (23 downto 0)
• clk
• H_RL
• N_C
• S_R
Devices Devices

(MHz) 65.74 63.844 (MHz) 67.22

Key Lessons
What Went Right
• We have the well defined path to follow.
− The algorithm is well defined and easily understood.
• We have scheduled each and every task to be

performed.
• The simulations were verified with the desired
outputs.

What Went Wrong
• Synchronization between the functionalities of SIPO-
serial in parallel out and PISO parallel in serial out.
• In the designing of rotator block we wanted to shift all
the 64 bits to be shifted on a single clock pulse for the
faster computations in the range of 0 to 63 bits.
• Arithmetic operations like mod we have to find a
similar in functionality but different in
implementation as mod can be operated only on the
operands with power of 2.

Proposed solutions
• We have defined the required bits of control
register and status register for better
synchronization.
• For the rotator block we have designed the
barrel shifter to shift the 64 bits on a single
clock pulse.
• For the “mod” operator we defined a new logic
on the basis of approximation with help of
XOR.
Achievements
Papers
• “ Digital Fortress [New Standard for Encryption] ”;
National Conference on Communication -2007;
January-2007; IIT, Kanpur, India
• “ Design, Simulation and Implementation of Digital
Fortress on FPGA ”; Design Techniques for Modern
Electronic Devices, VLSI & Communication
system; May-2007; NIT, Hamirpur, India
• Currently we are preparing a paper on“Comparisopn
between the Digital Fortress and the Existing
Encryption Standards”, for National Level Symposium
on Security & Soft Computing,March-2007,SVNIT,Surat
Methods
• Prime Number Fibonacci Series
• Large Number Division scheme using Divide
& Conquer Approach with the modulo
operator
• Optimization of Modulo operator with other
arithmetic operators like addition/subtraction
and multiplication
• Implementation of large Barrel Shifter using
Divide & Conquer Approach

References
• D. Brown; “Digital Fortress”
• “Security Requirements for cryptographic modules”,
FIPS (Federal Information Processing Standard)
Publication 140-1, US Department of Commerce /
National Institute of standards & technology
• D. Welsh; “Codes & Cryptography”, Oxford Science
Publication ,1998
• J. A. Buchmann; “Introduction to Cryptography”,
Springer- Verlag, New York, Second Edition,2001
• C. E. Shannon; “Communication Theory of Secrecy
System”, Bell System Technology Journal,1949
• Gilbert Vernam; “Vernam’s Cipher”, Bell System
Technology Journal,1918
• D. Stinson; “Cryptography, Theory & Practice”, CRC
Press, Florida, Second Edition, 2002
• “Glossary for Computer System Security”, FIPS
(Federal Information Processing Standard) Publication 39,
US Department of Commerce / National Institute of
standards & technology
• Z. A. Kissel; “Obfuscation of The Standard XOR
Encryption Algorithm”, Crossroads, The ACM Student
Magazine

• A. J. Menezes, S. A. Vanstone, D. C. Van Oorschot;
“Hand-book of Applied Cryptography”, CRC Press,
Florida, 1996
• “Data Encryption Standard”, FIPS (Federal
Information Processing Standard) Publication 46-3, US
Department of Commerce / National Institute of
standards & technology
• D. Kahn; “The Codebreakers: The story of Secret
Writing”, Scribner, New York, 1996
• M. Gardener; “Codes, Ciphers and Secret Writing”;
Dover, New York, 1972

IEEE PAPERS
E Rodriguez-Henriquez, N.A. Saqib and A. Diaz-Pkrez “4.2 Gbit/s
single-chip FPGA implementation of AES algorithm”
Electronics letters,24th July 2003,Vol 39,No 15
M. McLoone and J.V. McCanny “High-performance FPGA
implementation of DES using a novel method for implementing
the key schedule”, IEE Proc.-Circuits Devices Syst., Vol. 150, No.
5, October 2003
Alireza Hodjat and Ingrid Verbauwhede, “A 21.54 Gbits/s Fully
Pipelined AES Processor on FPGA”, Proceedings of the 12th
Annual IEEE Symposium on Field-Programmable Custom
Computing Machines.
S.-F. Hsiao, M.-C. Chen, M.-Y. Tsai and C.-C. Lin, “System-on-chip
implementation of the whole advanced encryption standard
processor using reduced XOR-based sum-of-product
operations”, IEE Proc. Inf. Secur.

Web Sites
• Tom Dunigan’s Security Page
• The Cryptography FAQ
• Computer Security Resource Center
• American Cryptogram Association
• AES Home Page; The Rijandel Page
• Block Cipher Lounge
• NIST Random Number Generation Technical
Working Group
Acknowledgement
• Authors are grateful towards the Department of Electronics &
communication, Institute of Technology, Nirma University,
Ahmedabad for their generous help & support.
• Authors would like to thank Prof. Y. N. Trivedi for their
helpful comments & discussions. Authors would also like to
thank the colleague students for their comments & reviews.
• Authors are grateful towards the Mr. Dan Brown, the author of
book “Digital Fortress” for giving such a wonderful idea
through the book & also for such a good book.
• Last but not the least; authors are thankful to the Almighty who
blessed me with the zeal to work hard.

Questions
& Comments

IDFF 08-03 Full

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Implementation of

Digital Fortress On FPGA

− Designing : VHDL code

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 2/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 3/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 4/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 5/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 6/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 7/69

• Phase IV: Advancement

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 9/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 10/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 11/69

Pratik Shah 300 hrs

Emergency Report From

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 15/69

Plaintext: MOTOROLA 2007/ZONE 09

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 16/69

• Asymmetric {Different Key for Decryption}

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 17/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 18/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 19/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 20/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 21/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 22/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 23/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 24/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 25/69

• Input: Data & Key

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08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 39/69

Title Spartan Virtex Title StratixII

Logic Utilization ALUT(USED/UNAVAILABLE) 148/1

Slice FlipFlop/Latches 72/70 72/70 Combinational without Register 73

4 Input LUTs 149 149 Combinational with Register 75

Logic Distribution Register/ Total Register 0/75

Occupied Slices 115 115 ROUTING CELL 0

4 Input LUTs 157 157 I/O PINS / CLOCK 73/4

Bonded IOB 70 70 ALM 75

Gate Count 2108 2108 LAB 11

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 41/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 42/69

Title Spartan Virtex Title StratixII

Logic Utilization ALUT(USED/UNAVAILABLE) 87/0

Slice FlipFlop/Latches 73/5 73/5 Combinational without Register 14

4 Input LUTs 87 87 Combinational with Register 11

Logic Distribution Register/ Total Register 62

Occupied Slices 52 52 ROUTING CELL 62

4 Input LUTs 95 95 I/O PINS / CLOCK 72/2

Bonded IOB 70 70 ALM 44

Gate Count 1414 1414 LAB 6

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 44/69

08/02/2007 FAER/MOTOROLA Scholar Contest – 2007 45/69