System Programming Course Code: CS609

Cs609@vu.edu.pk

Lecture # 14

RS – 232C Standard
• Standard for physical dimensions of the
connectors.
RS – 232C Cable

PC (DCE)

Modem
(DTE) Connected via
serial port

RS – 232C Connectors and Signals

DB25 (25 pin connector)

13
25
12
24
11
23
10
22 RI
9
21
CD 8
20 DTR
GND 7 19
DSR 6 18
CTS 5
17
RTS 4
16
RD 3
15
TX D 2
14
1
25 pin connector on PC

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Flow Control using RS232C

RI

CD

DTE DTR DCE

DSR
PC RTS MODEM

CTS

RxD TxD

DTR (SHOULD REM AIN HIGH THROUGH OUT THE SESSION )

CTS (CAN BE US ED FOR FLOW CONTROL )

Data is received through the RxD line. Data is send through the TxD line. DTR (data
terminal ready) indicates that the data terminal is live and kicking. DSR(data set ready)
indicates that the data set is live. Whenever the sender can send data it sends the signal
RTS( Request to send) if as a result the receiver is free and can receive data it send the
sender an acknowledge through CTS( clear to send) indicating that its clear to send now.

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DB 9 Connector for UART

DB9 Connector
1
CD
6
2 DSR
Rx D 7
3 RTS
TxD 8
4 CTS
DT R 9
5 RI
GND

The above slide shows the pinouts of the DB 9 connector.

UART internals

UART Internals R xD
Receiver Buffer Register Receiver Shift Register

Interrupt Enable Register

Interrupt
Line Status Register to
Parity LOGIC
Interrupt ID Register

Divisor Latch Register

Line Control Register 2.DTR

1.RT
Modem Control Register
1.CTS 2.DSR
Modem 3.CD
Status Register 4.RI

Transmit Shift T xD
Transmitter Holding Register
Register

This slide shows the various internal registers within a UART device. The programmer
only needs to program these registers efficiently in order to perform asynchronous
communication.
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Register summary

Base +
Transmitter Holding Register THR 0
Receiver Dat a RBR 0
Band Rate Divisor (Low Byte) DLL 0
Band Rate Divisor (High Byte) DLM 1
Interrupt Enable IER 1
FIFO Control Register FCR 2
Interrupt ID IIR 2
Line Cont rol LCR 3
Mode Control MCR 4
Line Status LSR 5
Modem Status MSR 6
Scratch Pad SP 7

The above table lists the registers within the UART ans also shows their abbreviation.
Also it shows there offsets with respect to the base register.

Served Ports in Standard PC

BIOS supports 4 UARTS as COM Ports
COM1, COM2, COM3, COM4

Ports Memory Port Base

Address
COM1 0040:0000 03F8H
COM2 0040:0002 2F8H
COM3 0040:0004 3E8H
COM4 0040:0006 2E8H

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BIOS Data Area

Text Dump

-d 40:0

0040:0000 F8 03 F8 02 E8 03 E8 02-BC 03 78 03 78 02 C0 9F ..........x.x...

0040:0010 23 C8 20 80 02 85 00 20-00 00 34 00 34 00 71 10 #. .... ..4.4.q.
0040:0020 0D 1C 71 10 0D 1C 64 20-20 39 34 05 30 0B 3A 27 ..q...d 94.0.:'
0040:0030 30 0B 0D 1C 00 00 00 00-00 00 00 00 00 00 00 00 0...............
0040:0040 D8 00 C3 00 00 00 00 00-00 03 50 00 00 10 00 00 ..........P.....
0040:0050 00 0A 00 00 00 00 00 00-00 00 00 00 00 00 00 00 ................
0040:0060 0F 0C 00 D4 03 29 30 00-00 00 00 00 02 C9 0B 00 .....)0.........
0040:0070 00 00 00 00 00 00 08 00-14 14 14 14 01 01 01 01 ................
-q

The above dump of the BIOS data area for a certain computer shows that the address of
COM1 is 03F8 , the address of COM2 is 02F8 and the address of COM3 is 03E8. These
addresses may not be same for all the computers and may vary computer to computer.

Setting the Baud rate

Setting the Baud Rate

1.8432 MHZ=frequency generating by UARTS
internally
Baud rate =1.8432 MHZ / (16*Divisor)

Divisor value loaded in DLL ( Base +0 )

and DLM ( Base +1 )

Divisor = 1, Baud Rate = 115200

Divisor = 0CH, Baud Rate = 9600
Divisor = 180H, Baud Rate = 300

The baud rate is set in accordance with the divisor value loaded within the UART internal
registers base +0 and base +1.
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Line Control Register

Line Control Register

7 6 5 4 3 2 1 0
Word Length
0 Load THR 00 = 5 BITS
1Load Divisor Value 01 = 6 BITS
10 = 7 BITS
11 = 8 BITS
Stop Communication =1 Length of Stop BITS
Resume Communication =0 0 = one BIT
Constant Parity 1 =1.5 for 5 bit Word
0 =NO constant Parity
1 =Constant Parity Parity Check and
0 if bit 4 =1 generation on
1 if bit 4 =0 Parity
0 = odd
1 = Even.

The line control register contains important information about the behaviour of the line
through which the data will be transferred. In it various bits signify the word size, length
of stop bits, parity check, parity type and also the a control bit to load the divisor value.
The bit 7 if set indicates that the base +0 and base + 1 will act as the divisor register
otherwise if cleared will indicate that base + 0 is the data register.

Line Status Register

6 5 4 3 2 1 0

Data Ready =1

Over Run Error = 1

TSR is Empty=1
TSR Contain a Byte=0

THR entry =1 Parity Error =1

THR contains a BYTE =0

Transfer Error (Framing Error)

Stop Communication Signal from Other end =1

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Line status register illustrates the status of the line. It indicates if the data can be sent or
received. If bit 5 and 6 both are set then 2 consecutive bytes can be sent for output. Also
this register indicates any error that might occur during communication.

Interrupt Enable Register

Interrupt Enable Register

3 2 1 0

Trigger Interrupt
On Data Ready =1
Trigger Interrupt
As soon as THR is empty =1

Trigger Interrupt
On change in Modem Status =1 Trigger Interrupt
On line status change =1

If interrupt driven output is to be performed then this register is used to enable interrupt
for the UART. It can also used to select the events for which to generate interrupt as
described in the slide.

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Interrupt ID Register

Interrupt ID Register
2 1 0

Trigger Triggered

Modem/Line
00 =Change in Modem Status
01 = THR is Empty
10 = Data is Ready
11 =Error in Data

Once an interrupt occurs it may be required to identify the case of the interrupt. This
register is used to identify the cause of the interrupt.

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