A

MODEL NAME: NAP00

LA-5811P MB
PCB NAME:
COMPAL P/N: DAA00001P00

Compal confidential
Schematics Document

Intel CULV (SFF)

Penryn + Cantiga + ICH9-M
DISCRETE VGA N11P-GS1 (Switchable Graphics)
3

2009-12-16
Rev: 1.0

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Cover Sheet

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
E

of

58

ULV
1

CK505

Mobile Penym

Thermal Sensor
EMC1402 Page4

Clock Generator
ICS9LPRS397

ULV Dual Core

uFCBGA-956 CPU - SFF

Page16
page 4,5,6,7

LCD Conn.

CRT Conn.

page29

H_A#(3..35)
H_D#(0..63)

page30

LCD Switch

CRT Switch

page28

LVDS
LVDS
HDMI Conn.
2

TMDS

page31

Engine
600MHz

667/800/1066MHz 1.05V

DDR3 1066MHz 1.5V

Intel Cantiga
GS45

page30

NVIDIA
N11P-GS1

FSB

BANK 0, 1, 2, 3

page32

FCBGA 1363 - SFF

PCI-Express

page 8,9,10,11,12,13

16X

USB Conn x 2

IO Board

Memory
900MHz

DMI X4

page36

Intel ICH9-M

3.3V 24.576MHz/48Mhz

page29

WBMMAP-569 - SFF
PCI-Express

Page17,18.19,20

Bluetooth
Conn
page33

N11P HDA

ALC665
IO Board

CMOS
Camera 1.3M

USB

SATA

HDA Codec

IO Board

Power Share
USB conn x1

page 21~27

HD Audio

page 14,15

Dual Channel

VRAM DDR3 x 8
1GB(64Mx16)

DP Conn.

DDR3-SO-DIMM X 2

port 0

SATA HDD
Conn.
3

Aline FX/ELC

Right light

Silion LABS
C8051F347

LED board

page38

Left light
Card Reader

page32

JMicron
JMB380

LPC

page35

3 IN 1 Conn.

page35

1394 Conn.

page35

LED board
3

Power light
Power key board

APA2031

Audio AMP

MINI Card WWAN

IO Board

Full length MC

ENE KB926

page33

LOGO light

SIM Card Conn.

page33

LOGO board

page37

Phone Jack x3
Touch Pad
page39

Int.KBD
page37

page33

LAN(GbE)

page37

Atheros AR8132
10/100 M page34

2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

RJ45
4

page34

Compal Secret Data

Security Classification

Function board

802.11a/b/g/n
1/2 length MC

BIOS

Function light

MINI Card WLAN

IO Board

Title

Compal Electronics, Inc.

Block Diagram

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
E

of

58

( O MEANS ON

Voltage Rails

B+

X MEANS OFF )

+5VALW

+1.8V

+5VS

+3VALW

+1.5V

+3VS

VL

power
plane

+0.75VS
+VCCP
+CPU_CORE

I2C / SMBUS ADDRESSING

State

DEVICE
EC_SMB_CK1
EC_SMB_DA1

HEX

ADDRESS

Battery

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery

don't exist

EC_SMB_CK2
EC_SMB_DA2

ICH_SMBCLK
ICH_SMBDATA

CPU THERMAL SENSOR (EMC1402-1-ACZL)

4C

GPU THERMAL SENSOR (ADM1032ARMZ)

4D

01001100
01001101

GPU INTERNAL THERMAL SENSOR

9E

10011110

CLOCK GENERATOR (EXT.)

D2

11010010

Free Fall Sensor

38

00111000

Compal R1 PN
CPU-->SA00003I91L(S IC AV80577UG0132M SLGS4 R0 1.3G FCBGA)----->SU4100
CPU-->SA00003IA1L(S IC AV80577UG0133M SLGS6 R0 1.3G FCBGA)----->SU7300
NB-->SA00002RQ1L(S IC AC82GS45 SLB92 B3 FCBGA 1363)----->45180131L03,45180131L04
SB-->SA00001YC4L(S IC AM82801IUX SLB8N A FCBGA 569P ICH9M)-->45180131L03,45180131L04
VRAM-->SA00003240L(S IC D3 64M16 H5TQ1G63BFR-12C FBGA 96P)-->45180131L03,45180131L04
VRAM-->SA00003570L(S IC D3 64M16 K4W1G1646E-HC12 FBGA 96P)-->45180131L03,45180131L04
Compal R3 PN
CPU-->SA00003I92L(S IC AV80577UG0132M SLGS4 R0 1.3G A31!)----->SU4100
CPU-->SA00003IA2L( S IC AV80577UG0133ML SLGYV R0 1.3G A31!)----->SU7300
NB-->SA00002RQ0L(S IC AC82GS45 SLB92 B3 FCBGA 1363 A31 !)----->45180131L01,45180131L02
SB-->SA00001YC3L(S IC AM82801IUX SLB8N A FCBGA ICH9M A31!)-->45180131L01,45180131L02
VRAM-->SA00003241L(S IC D3 64M16 H5TQ1G63BFR-12C FBGA A31!)-->45180131L01,45180131L02
VRAM-->SA00003571L(S IC D3 64M16 K4W1G1646E-HC12 FBGA A31!)-->45180131L01,45180131L02

Symbol Note :
: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
CONN@ : means ME part.
45@ : means install after SMT.

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Notes List

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

of

58

+VCCP

Place close to U1.

H_A#[3..16]

H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#

18
18
18
18

H_STPCLK#
H_INTR
H_NMI
H_SMI#

C7
D4
F10
F8
C9
C5
E5

STPCLK#
LINT0
LINT1
SMI#
RSVD01
RSVD02
RSVD03
RSVD04
RSVD05
RSVD06
RSVD07

M2

H_BR0#
H_INIT#

18

N1

H_LOCK#

RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#

G5
K2
H4
K4
L1

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

AY8
BA7
BA5
AY2
AV10
AV2
AV4
AW7
AU1
AW5
AV8
J7

THERMTRIP#

8
8
8
8

H_HIT#
H_HITM#

8
8

R3

54.9_0402_1%

XDP_BPM#5

R4

54.9_0402_1%

XDP_TRST#

R6

51_0402_1%

XDP_TCK

R7

54.9_0402_1%

For ESD

R14
0_0402_5%
1
2

XDP_BPM#5_R
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#_R

H_THERMTRIP#

54.9_0402_1%

XDP_TDO

+3VS

XDP_BPM#5

R111 0_0402_5%
1
2 XDP_DBRESET#

XDP_DBRESET# 19

H_PROCHOT# 51
+VCCP

B10

54.9_0402_1%

C1046 @

Add 0 ohm per EMI request.

R22
H_THERMDA_R R23
H_THERMDC_R R24

2 68_0402_5%
2 0_0402_5%
2 0_0402_5%

1
1
1

1
C1034

H_THERMDA
H_THERMDC
+3VS

H_THERMTRIP# 8,18

R306
1
2
10K_0402_5%

H_THERMDA, H_THERMDC routing together,

Trace width / Spacing = 10 / 10 mil

H CLK
BCLK[0]
BCLK[1]

A35
C35

U7

H_THERMDA
C1035
H_THERMDC
1
2
2200P_0402_50V7K
THERM#

Place Close to U1.

D38
BB34
BD34

R2

This shall place near CPU

H_RESET#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

THERMAL
PROCHOT#
THERMDA
THERMDC

R10
51_0402_1%

H_RESET#

H2
F2

R1

XDP_TMS

0.1U_0402_16V4Z

IERR#
INIT#

XDP_TDI

LOCK#

VDD

2
3
4

SMCLK

DP

SMDATA

DN

ALERT#

THERM#

GND

EC_SMB_CK2 21,37

7
6

EC_SMB_DA2 21,37
1

2 10K_0402_5%
R305

+3VS

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100

CLK_CPU_BCLK 16
CLK_CPU_BCLK# 16

RESERVED

V2
Y2
AG5
AL5
J9
F4
H8

A20M#
FERR#
IGNNE#

H_DEFER# 8
H_DRDY# 8
H_DBSY# 8

B40
D8

HIT#
HITM#

ICH

18
18
18

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

N5
F38
J1

8
8
8

H_PROCHOT#
0.1U_0402_16V4Z

AN1
AK4
AG1
AT4
AK2
AT2
AH2
AF4
AJ5
AH4
AM4
AP4
AR5
AJ1
AL1
AM2
AU5
AP2
AR1
AN5

ADDR GROUP 1

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

BR0#

H_ADS#
H_BNR#
H_BPRI#

1
2
R9
56_0402_5%

R1
R5
U1
P4
W5

DEFER#
DRDY#
DBSY#

CONTROL

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

8
8
8
8
8
H_A#[17..35]

ADS#
BNR#
BPRI#

M4
J5
L5

0.1U_0402_16V4Z

H_ADSTB#0

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

ADDR GROUP 0

P2
V4
W1
T4
AA1
AB4
T2
AC5
AD2
AD4
AA5
AE5
AB2
AC1
Y4

U1A
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

XDP/ITP SIGNALS

+VCCP

PENRYN SFF_UFCBGA956
SU4100@

1
C1057 @
2

For EMI

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Penryn(1/4)-AGTL+/ITP-XDP

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

of

58

+VCC_CORE

T9
T10
16
16
16

A37
C37
B38

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
BSEL[0]
BSEL[1]
BSEL[2]

COMP[0]
COMP[1]
COMP[2]
COMP[3]

AE43
AD44
AE1
AF2

COMP0
COMP1
COMP2
COMP3

DATA GROUP 2

MISC

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#

G7
B8
C41
E7
D10
BD10

H_PSI#

H_DSTBN#3 8
H_DSTBP#3 8
H_DINV#3 8

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
T11

8,18,51
18
8
18
8

PENRYN SFF_UFCBGA956
SU4100@
Cause

CPU core power change to

1 phase, and not need support
the pin, leave it as TP. 10/02

layout note: Route TEST3 & TEST5 traces on

ground referenced layer to the TPs
CPU_BSEL

166

CPU_BSEL2

CPU_BSEL1

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

CPU_BSEL0
1

200

266

VCCP_001
VCCP_002
VCCP_003
VCCP_004
VCCP_005
VCCP_006
VCCP_007
VCCP_008
VCCP_009
VCCP_010
VCCP_011
VCCP_012
VCCP_013
VCCP_014
VCCP_015
VCCP_016
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE

+VCCP

J11
E11
G11
J37
K38
L37
N37
P38
R37
U37
V38
W37
AA37
AB38
AC37
AE37

1
+

C5
330U_D2E_2.5VM_R9
2

B34
D34

Change to 330u_R9,
casue high limitation
+1.5VS

BD8
BC7
BB10
BB8
BC5
BB4
AY4
BD12

VCCSENSE

BC13

VSSSENSE

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

51
51
51
51
51
51
51

VCCSENSE

51

VSSSENSE

51

1
C6
2

1
C7
2

Near pin D34

TEST5
TEST6

AW43
E37
D40
C43
AE41
AY10
AC43

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

10U_0805_6.3V6M

TEST2

AV38
AT44
AV40
AU41
AW41
AR41
BA37
BB38
AY36
AT40
BC35
BC39
BA41
BB40
BA35
AU43
AY40
AY38
BC37

H_DSTBN#2 8
H_DSTBP#2 8
H_DINV#2 8
H_D#[48..63] 8

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

AB28
AD30
AD28
Y26
AB26
AD26
AF30
AF28
AH30
AH28
AF26
AH26
AK30
AK28
AM30
AM28
AP30
AP28
AK26
AM26
AP26
AT30
AT28
AV30
AV28
AY30
AY28
AT26
AV26
AY26
BB30
BB28
BD30

0.01U_0402_16V7K

V_CPU_GTLREF
T8

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#

F32
G33
H32
J33
K32
L33
M32
N33
P32
R33
T32
U33
V32
W33
Y32
AA33
AB32
AC33
AD32
AE33
AF32
AG33
AH32
AJ33
AK32
AL33
AM32
AN33
AP32
AR33
AT34
AT32
AU33
AV32
AY32
BB32
BD32
B28
B30
B26
D28
D30
F30
F28
H30
H28
D26
F26
H26
K30
K28
M30
M28
K26
M26
P30
P28
T30
T28
V30
V28
P26
T26
V26
Y30
Y28
AB30

H_DSTBN#1
H_DSTBP#1
H_DINV#1

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#

U1C

8
8
8

P44
V40
V44
AB44
R41
W41
N43
U41
AA41
AB40
AD40
AC41
AA43
Y40
Y44
T44
U43
W43
R43

DATA GROUP 1

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

1 R30
54.9_0402_1%
1 R31
27.4_0402_1%
1 R32
54.9_0402_1%
1 R33
27.4_0402_1%

H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#[16..31]

AP44
AR43
AH40
AF40
AJ43
AG41
AF44
AH44
AM44
AN43
AM40
AK40
AG43
AP40
AN41
AL41
AK44
AL43
AJ41

8
8
8
8

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

DATA GROUP 0

F40
G43
E43
J43
H40
H44
G39
E41
L41
K44
N41
T40
M40
G41
M44
L43
K40
J41
P40

+VCC_CORE

H_D#[32..47] 8

U1B
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#[0..15]

DATA GROUP 3

Near pin B34

PENRYN SFF_UFCBGA956
SU4100@

Length match within 25 mils.

The trace width/space/other is
20/7/25.

+VCC_CORE

+VCCP

R34
1
2
100_0402_1%

VCCSENSE

R35
1
2
100_0402_1%

VSSSENSE

Close to CPU pin

within 500mils.

V_CPU_GTLREF

R36
1K_0402_1%

R37
2K_0402_1%

Close to CPU pin AW43

within 500mils.

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Penryn(2/4)-AGTL+/ITP-XDP

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

of

58

5
4

VCCP_021
VCCP_022
VCCP_023
VCCP_024
VCCP_025
VCCP_026
VCCP_027
VCCP_028
VCCP_029
VCCP_030
VCCP_031
VCCP_032
VCCP_033
VCCP_034
VCCP_035
VCCP_036
VCCP_037
VCCP_038
VCCP_039
VCCP_040
VCCP_041
VCCP_042
VCCP_043
VCCP_044
VCCP_045
VCCP_046
VCCP_047
VCCP_048
VCCP_049
VCCP_050
VCCP_051
VCCP_052
VCCP_053
VCCP_054
VCCP_055
VCCP_056
VCCP_057
VCCP_058
VCCP_059
VCCP_060
VCCP_061
VCCP_062
VCCP_063
VCCP_064
VCCP_065
VCCP_066
VCCP_067
VCCP_068
VCCP_069
VCCP_070
VCCP_071
VCCP_072
VCCP_073
VCCP_074
VCCP_075
VCCP_076
VCCP_077
VCCP_078
VCCP_079
VCCP_080
VCCP_081
VCCP_082
VCCP_083
VCCP_084
VCCP_085
VCCP_086
VCCP_087
VCCP_088
VCCP_089
VCCP_090
VCCP_091
VCCP_092
VCCP_093
VCCP_094
VCCP_095
VCCP_096
VCCP_097
VCCP_098
VCCP_099
VCCP_100
VCCP_101
VCCP_102
VCCP_103
VCCP_104
VCCP_105
VCCP_106
VCCP_107
VCCP_108
VCCP_109
VCCP_110
VCCP_111
VCCP_112
VCCP_113
VCCP_114
VCCP_115
VCCP_116
VCCP_117
VCCP_118
VCCP_119
VCCP_120
VCCP_121
VCCP_122
VCCP_123
VCCP_124
VCCP_125
VCCP_126
VCCP_127
VCCP_128
VCCP_129
VCCP_130
VCCP_131
VCCP_132
VCCP_133
VCCP_134
VCCP_135
VCCP_136
VCCP_137
VCCP_138
VCCP_139
VCCP_140
VCCP_141
VCCP_142
VCCP_143
VCCP_144
VCCP_145

AL37
AN37
AP38
B32
C33
D32
E35
E33
F34
G35
F36
H36
J35
L35
N35
K36
R35
U35
P36
V36
W35
AA35
AC35
AB36
AE35
AG35
AJ35
AF36
AL35
AN35
AK36
AP36
B12
B14
C13
D12
D14
E13
F14
F12
G13
H14
H12
J13
K14
K12
L13
L11
M14
N13
N11
K10
P14
P12
R13
R11
T14
U13
U11
V14
V12
W13
W11
P10
V10
Y14
AA13
AA11
AB14
AB12
AC13
AC11
AD14
AB10
AE13
AE11
AF14
AF12
AG13
AG11
AH14
AJ13
AJ11
AF10
AK14
AK12
AL13
AL11
AN13
AN11
AP12
AR13
AR11
AK10
AP10
AU13
AU11
L9
L7
N9
N7
R9
R7
U9
U7
W9
W7
AA9
AA7
AC9
AC7
AE9
AE7
AG9
AG7
AJ9
AJ7
AL9
AL7
AN9
AN7
AR9
AR7
A33
A13

Security Classification

Issued Date
2009/07/25

Compal Secret Data

Deciphered Date

2010/07/25

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

Title

Date:

VCCP_017
VCCP_018
VCCP_019
VCCP_020

VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
VCC_111
VCC_112
VCC_113
VCC_114
VCC_115
VCC_116
VCC_117
VCC_118
VCC_119
VCC_120
VCC_121
VCC_122
VCC_123
VCC_124
VCC_125
VCC_126
VCC_127
VCC_128
VCC_129
VCC_130
VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
VCC_136
VCC_137
VCC_138
VCC_139
VCC_140
VCC_141
VCC_142
VCC_143
VCC_144
VCC_145
VCC_146
VCC_147
VCC_148
VCC_149
VCC_150
VCC_151
VCC_152
VCC_153
VCC_154
VCC_155
VCC_156
VCC_157
VCC_158
VCC_159
VCC_160
VCC_161
VCC_162
VCC_163
VCC_164
VCC_165
VCC_166
VCC_167
VCC_168
VCC_169
VCC_170
VCC_171
VCC_172
VCC_173
VCC_174
VCC_175
VCC_176
VCC_177
VCC_178
VCC_179
VCC_180
VCC_181
VCC_182
VCC_183
VCC_184
VCC_185
VCC_186
VCC_187
VCC_188
VCC_189
VCC_190
VCC_191
VCC_192
VCC_193
VCC_194
VCC_195
VCC_196
VCC_197
VCC_198
VCC_199
VCC_200
VCC_201
VCC_202
VCC_203
VCC_204
VCC_205
VCC_206
VCC_207
VCC_208
VCC_209
VCC_210
VCC_211
VCC_212
VCC_213
VCC_214
VCC_215
VCC_216
VCC_217
VCC_218
VCC_219
VCC_220

AF38
AG37
AJ37
AK38

BD28
BB26
BD26
B22
B24
D22
D24
F24
F22
H24
H22
K24
K22
M24
M22
P24
P22
T24
T22
V24
V22
Y24
Y22
AB24
AB22
AD24
AD22
AF24
AF22
AH24
AH22
AK24
AK22
AM24
AM22
AP24
AP22
AT24
AT22
AV24
AV22
AY24
AY22
BB24
BB22
BD24
BD22
B16
B18
B20
D16
D18
F18
F16
H18
H16
D20
F20
H20
K18
K16
M18
M16
K20
M20
P18
P16
T18
T16
V18
V16
P20
T20
V20
Y18
Y16
AB18
AB16
AD18
AD16
Y20
AB20
AD20
AF18
AF16
AH18
AH16
AF20
AH20
AK18
AK16
AM18
AM16
AP18
AP16
AK20
AM20
AP20
AT18
AT16
AV18
AV16
AY18
AY16
AT20
AV20
AY20
BB18
BB16
BD18
BD16
BB20
BD20
AM14
AP14
AT14
AV14
AY14
BB14
BD14

5
2
1

D
D

+VCCP

+VCC_CORE

U1F
PENRYN SFF_UFCBGA956
SU4100@
C

+VCCP

B
B

A
A

Penryn(3/4)-Power

Compal Electronics, Inc.

Size Document Number

Custom LA-5811P
Rev
1.0

Tuesday, December 29, 2009

1

Sheet
6
of
58

C31
10U_0603_6.3V6M

C30
10U_0603_6.3V6M

C29
10U_0603_6.3V6M

C28
10U_0603_6.3V6M

+VCC_CORE

High Frequence Decoupling

C55
1U_0402_6.3V6K

C54
1U_0402_6.3V6K

C53
1U_0402_6.3V6K

C52
1U_0402_6.3V6K

C51
1U_0402_6.3V6K

C50
1U_0402_6.3V6K

C49
1U_0402_6.3V6K

C48
1U_0402_6.3V6K

C47
1U_0402_6.3V6K

C46
1U_0402_6.3V6K

C45
1U_0402_6.3V6K

C44
1U_0402_6.3V6K

C43
1U_0402_6.3V6K

C42
1U_0402_6.3V6K

C41
1U_0402_6.3V6K

C40
1U_0402_6.3V6K

C39
1U_0402_6.3V6K

C38
1U_0402_6.3V6K

C37
1U_0402_6.3V6K

C36
1U_0402_6.3V6K

C35
1U_0402_6.3V6K

6/14 :Replace 12pcs 10uF_0805 to 24 pcs 1uF_0402 for CPU transient fail issue.

ESR <= 9m ohm (For CPU)

Near CPU CORE regulator
+VCC_CORE

C58

220U_D2_2VK_R9

220U_D2_2VK_R9

220U_D2_2VK_R9

+VCCP

C70
1U_0402_6.3V6K

C69
1U_0402_6.3V6K

C68
1U_0402_6.3V6K

C67
1U_0402_6.3V6K

C66
1U_0402_6.3V6K

C65
1U_0402_6.3V6K

C64
1U_0402_6.3V6K

C63
1U_0402_6.3V6K

C62
1U_0402_6.3V6K

C61
1U_0402_6.3V6K

C60
1U_0402_6.3V6K

C59
1U_0402_6.3V6K

Compal Secret Data

Security Classification
2009/07/25

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

C27
10U_0603_6.3V6M

C26
10U_0603_6.3V6M

C25
10U_0603_6.3V6M

C24
10U_0603_6.3V6M

C23
10U_0603_6.3V6M

C22
10U_0603_6.3V6M

C21
10U_0603_6.3V6M

C20
10U_0603_6.3V6M

C19
10U_0603_6.3V6M

C18
10U_0603_6.3V6M

C17
10U_0603_6.3V6M

C16
10U_0603_6.3V6M

C15
10U_0603_6.3V6M

C14
10U_0603_6.3V6M

C13
10U_0603_6.3V6M

C12
10U_0603_6.3V6M

C11
10U_0603_6.3V6M

Issued Date

PENRYN SFF_UFCBGA956
SU4100@

C34
1U_0402_6.3V6K

AA15
AC15
Y10
AD10
AH12
AE15
AG15
AJ15
AH10
AM12
AL15
AN15
AR15
AM10
AT12
AV12
AW13
AW11
AY12
AU15
AW15
AT10
BA13
BA11
BB12
BC11
BA15
BC15
B6
D6
E9
F6
G9
H6
K8
K6
M8
M6
P8
P6
T8
T6
V8
V6
U5
Y8
Y6
AB8
AB6
AD8
AD6
AF8
AF6
AH8
AH6
AK8
AK6
AM8
AM6
AP8
AP6
AT8
AT6
AU9
AV6
AU7
AW9
AY6
BA9
BB6
BC9
BD6
B4
C3
E3
G3
J3
L3
N3
R3
U3
W3
AA3
AC3
AE3
AG3
AJ3
AL3
AN3
AR3
AU3
AW3
BA3
BC3
D2
E1
G1
AW1
BA1
BB2
A41
A39
A29
A27
A31
A25
A23
A21
A19
A17
A11
A15
A7
A5
A9
BD4

C10
10U_0603_6.3V6M

VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
VSS_361
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395

C33
1U_0402_6.3V6K

PENRYN SFF_UFCBGA956
SU4100@

VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279

C9
10U_0603_6.3V6M

G25
G23
G21
J25
J23
J21
L25
L23
L21
N25
N23
N21
R25
R23
R21
U25
U23
U21
W25
W23
W21
AA25
AA23
AA21
AC25
AC23
AC21
AE25
AE23
AE21
AG25
AG23
AG21
AJ25
AJ23
AJ21
AL25
AL23
AL21
AN25
AN23
AN21
AR25
AR23
AR21
AU25
AU23
AU21
AW25
AW23
AW21
BA25
BA23
BA21
BC25
BC23
BC21
C17
C19
E19
E17
G19
G17
J19
J17
L19
L17
N19
N17
R19
R17
U19
U17
W19
W17
AA19
AA17
AC19
AC17
AE19
AE17
AG19
AG17
AJ19
AJ17
AL19
AL17
AN19
AN17
AR19
AR17
AU19
AU17
AW19
AW17
BA19
BA17
BC19
BC17
C11
C15
E15
G15
H10
M12
J15
L15
N15
M10
T12
R15
U15
W15
T10
Y12
AD12

C32
1U_0402_6.3V6K

AM36
AR35
AU35
AV34
AW35
AW33
AY34
AT36
AV36
BA33
BC33
BB36
BD36
C27
C29
C31
E29
E27
G29
G27
E31
G31
J29
J27
L29
L27
N29
N27
J31
L31
N31
R29
R27
U29
U27
R31
U31
W29
W27
W31
AA29
AA27
AC29
AC27
AA31
AC31
AE29
AE27
AG29
AG27
AJ29
AJ27
AE31
AG31
AJ31
AL29
AL27
AN29
AN27
AL31
AN31
AR29
AR27
AR31
AU29
AU27
AW29
AW27
AU31
AW31
BA29
BA27
BC29
BC27
BA31
BC31
C21
C23
C25
E25
E23
E21

Mid Frequence Decoupling

+VCC_CORE

U1E
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

C8
10U_0603_6.3V6M

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]

C57

U1D
B42
F44
D44
D42
F42
H42
K42
M42
P42
T42
V42
Y42
AB42
AD42
AF42
AH42
AK42
AM42
AP42
AY44
AV44
AT42
AV42
AY42
BA43
BB42
C39
E39
G37
H38
J39
L39
M38
N39
R39
T38
U39
W39
Y38
AA39
AC39
AD38
AE39
AG39
AH38
AJ39
AL39
AM38
AN39
AR39
AR37
AT38
AU39
AU37
AW39
AW37
BA39
BC41
BD40
BD38
B36
H34
D36
K34
M34
M36
P34
T34
V34
T36
Y34
AB34
AD34
Y36
AD36
AF34
AH34
AH36
AK34
AM34
AP34

C56

Title

Compal Electronics, Inc.

Penryn(4/4)-GND/Bypass

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

of

58

within 100 mils from NB

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

DDR CLK/ CONTROL/COMPENSATION

1
2
1

4
4
4
4
4
4
4
4

K26
G23
G25
J25
L25
L27
F24
D24
D26
J23
B26
A23
C23
B24
B22
K24
C25
L23
L33
K32
K34

J35
F6
PM_EXTTS#0
J39
PM_EXTTS#1
L39
R49 1
2 0_0402_5%
AY39
19,37,51 PM_PWROK
R50 1
2 100_0402_1% BB18
17,35,37 PLT_RST#
1
2
K28
R51
0_0402_5%
K36
19 PM_BMBUSY#
5,18,51 H_DPRSTP#
14,15 PM_EXTTS#0

C75

4,18 H_THERMTRIP#
19,51 PM_DPRSLPVR

Place them close to U4 pin BC51.

+1.5V

1
2
1

R57
10K_0402_1%
H_DPRSTP#

+3VS

2
PM_EXTTS#0

R62

2 10K_0402_5%

PM_EXTTS#1

R90

2 10K_0402_5%

A7
A49
A52
A54
B54
D55
G55
BE55
BH55
BK55
BK54
BL54
BL52
BL49
BL7
BL4
BL2
BK2
BK1
BH1
BE1
G1

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

BC35
BE33
BE37
BC37

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

14
14
15
15

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

BK18
BK16
BE23
BC19

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

14
14
15
15

SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1

BJ17
BJ19
BC17
BE17

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SM_RCOMP
SM_RCOMP#

BL25
BK26

SMRCOMP
SMRCOMP#

BK32
BL31

SMRCOMP_VOH
SMRCOMP_VOL

BC51
AY37
BH20
BA37

+V_DDR3_DIMM_REF
SM_PWROK
SM_REXT
R47 1
SM_DRAMRST#

CLK_MCH_3GPLL 16
CLK_MCH_3GPLL# 16

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

AG55
AL49
AH54
AL47

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

19
19
19
19

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

AG53
AK50
AH52
AL45

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

19
19
19
19

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

AG49
AJ49
AJ47
AG47

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

19
19
19
19

AF50
AH50
AJ45
AG45

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

19
19
19
19

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

48

1 @
C190
0.1U_0402_16V4Z
2

G33
G37
F38
F36
G35

G39

+VCCP
B

CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
TSATN#

HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC

AK52
AK54
AW40
AL53
AL55

CL_CLK0
CL_DATA0
M_PWROK
CL_RST#

CL_VREF

R52
1K_0402_1%

19
19
19
19

F34
F32
B38
A37
C31
K42
D10

T38
T39

0.1U_0402_16V4Z

R53
499_0402_1%

T56
CLKREQ#_B 16
MCH_ICH_SYNC#
TSATN#

R58

19

2 54.9_0402_1%

+VCCP

C29
B30
D28
A27
B28

CANTIGA GMCH SFF_FCBGA1363

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

SM_PWROK

2 499_0402_1%
SM_DRAMRST# 14,15

R49
P50

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

+1.5V

2 80.6_0402_1%
2 80.6_0402_1%

1
1

CLK_MCH_DREFCLK 16
CLK_MCH_DREFCLK# 16
MCH_SSCDREFCLK 16
MCH_SSCDREFCLK# 16

PEG_CLK
PEG_CLK#

14
14
15
15

B42
D42
B50
D50

DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

Compal Secret Data

2009/07/25

R43
R44

14
14
15
15

C76

Security Classification
Issued Date

PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#

+V_DDR3_DIMM_REF

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

BA31
BC25
BC33
BB24

SM_RCOMP_VOH
SM_RCOMP_VOL

CLK

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

14
14
15
15

J13
L13
C13
G13
G15

layout note:

R48
1K_0402_1%

16 MCH_CLKSEL0
16 MCH_CLKSEL1
16 MCH_CLKSEL2
T30
T31
10
CFG5
10
CFG6
10
CFG7
T32
10
CFG9
10
CFG10
T33
10
CFG12
10
CFG13
T34
T35
10
CFG16
T36
T37
10
CFG19
10
CFG20

0.1U_0402_16V4Z
C77

221_0603_1%
2
1

RSVD22
RSVD23
RSVD24
RSVD25

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

5
5
5
5

H_RS#0
H_RS#1
H_RS#2

C79

Near B6 pin

BB20
BE19
BF20
BF18

BB32
BA25
BA33
BA23

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_SWNG

T25
T26
T27
T28

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

L3
M2
Y2
AF2

R56

R61

R42
1K_0402_1%

R54
10K_0402_1%

0.1U_0402_16V4Z

R60

100_0402_1%
2
1

0.1U_0402_16V4Z

24.9_0402_1%
2
1

1K_0402_1%
1

2
2
1
2K_0402_1% R337

C78

RSVD20

NC

H_RCOMP

AW42

DMI

5
5
5
5

14,15 +V_DDR3_DIMM_REF

H_VREF

T24
+1.5V

1
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

F4
F2
G7

5
5
5
5

+VCCP

R55

RSVD17

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

SMRCOMP_VOL

C74

L9
N7
AA7
AG3

Layout Note:
V_DDR_MCH_REF trace
width and spacing is 20/20.

+VCCP

J9

R45
3.01K_0402_1%

0.01U_0402_25V7K

H_ADS#
4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR#
4
H_BPRI#
4
H_BR0#
4
H_DEFER#
4
H_DBSY#
4
CLK_MCH_BCLK 16
CLK_MCH_BCLK# 16
H_DPWR#
5
H_DRDY#
4
H_HIT#
4
H_HITM# 4
H_LOCK# 4
H_TRDY#
4

CANTIGA GMCH SFF_FCBGA1363

Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20

C72

2.2U_0603_6.3V4Z
C71

F10
A15
C19
C9
B8
C11
E5
D6
AH10
AJ11
G11
H2
C7
F8
A11
D8

H_AVREF
H_DVREF

Route H_SCOMP and H_SCOMP# with trace width,

spacing and impedance (55 ohm) same as FSB data
traces

T23

GRAPHICS VID

H_RS#_0
H_RS#_1
H_RS#_2

T21
T22

ME

H_CPURST#
H_CPUSLP#

TCK
TDI
TDO
TMS

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15

MISC

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

@ 1K_0402_5%
@ 4.7K_0402_5%
@ 4.7K_0402_5%
@ 1K_0402_5%

SMRCOMP_VOH

K2
N3
AA3
AF4

HDA

H_SWING
H_RCOMP

2
2
2
2

@ 0.1U_0402_16V4Z

Trace < = 500mils

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

+3VS

1
1
1
1

C1056

layout note:

L17
K18

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

R39
R38
R40
R41

J43
L43
J41
L41
AN11
AM10
AK10
AL11
F12
AN45
AP44
AT44
AN47
C27
D30

T12
T13
T14
T15
T16
T17
T18
T19
T20

PM

J11
G9

H_RESET#
H_CPUSLP#

H_VREF

B6
D4

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

CFG

H_SWNG
H_RCOMP

H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

L15
B14
C15
D12
F14
G17
B12
J15
D16
C17
D14
K16
F16
B16
C21
D18
J19
J21
B18
D22
G19
J17
L21
L19
G21
D20
K22
F18
K20
F20
F22
B20
A19

@ 0.1U_0402_16V4Z

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

J7
H6
L11
J3
H4
G3
K10
K12
L1
M10
M6
N11
L7
K6
M4
K4
P6
W9
V6
V2
P10
W7
N9
P4
U9
V4
U1
W3
V10
U7
W11
U11
AC11
AC9
Y4
Y10
AB6
AA9
AB10
AA1
AC3
AC7
AD12
AB4
Y6
AD10
AA11
AB2
AD4
AE7
AD2
AD6
AE3
AG9
AG7
AE11
AK6
AF6
AJ9
AH6
AF12
AH4
AJ7
AE9

RSVD

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

U3B

0.01U_0402_25V7K

U3A

H_D#[0..63]

4
5

H_A#[3..35]

HOST

2.2U_0603_6.3V4Z
C73

Title

Compal Electronics, Inc.

Cantiga(1/6)-AGTL/DMI/DDR

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

of

58

15 DDR_B_D[0..63]

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

BH22
BK20
BL15

DDR_A_RAS# 14
DDR_A_CAS# 14
DDR_A_WE# 14

AT50
BB50
BB46
BE39
BB12
BE7
AV10
AR9

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DM[0..7]

AR47
BA45
BE45
BC41
BC13
BB10
BA7
AN7
AR49
AW45
BC45
BA41
BA13
BA11
BA9
AN9

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS[0..7]

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

BC23
BF22
BE31
BC31
BH26
BJ35
BB34
BH32
BB26
BF32
BA21
BG25
BH34
BH18
BE25

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_MA[0..14] 14

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

14
14
14

14

14

DDR_A_DQS#[0..7]

14

CANTIGA GMCH SFF_FCBGA1363

AP54
AM52
AR55
AV54
AM54
AN53
AT52
AU53
AW53
AY52
BB52
BC53
AV52
AW55
BD52
BC55
BF54
BE51
BH48
BK48
BE53
BH52
BK46
BJ47
BL45
BJ45
BL41
BH44
BH46
BK44
BK40
BJ39
BK10
BH10
BK6
BH6
BJ9
BL11
BG5
BJ5
BG3
BF4
BD4
BA3
BE5
BF2
BB4
AY4
BA1
AP2
AU1
AT2
AT4
AV4
AU3
AR3
AN1
AP4
AL3
AJ1
AK4
AM4
AH2
AK2

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#

SA_RAS#
SA_CAS#
SA_WE#

BC21
BJ21
BJ41

MEMORY

SA_BS_0
SA_BS_1
SA_BS_2

MEMORY

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SYSTEM

AP46
AU47
AT46
AU49
AR45
AN49
AV50
AP50
AW47
BD50
AW49
BA49
BC49
AV46
BA47
AY50
BF46
BC47
BF50
BF48
BC43
BE49
BA43
BE47
BF42
BC39
BF44
BF40
BB40
BE43
BF38
BE41
BA15
BE11
BE15
BF14
BB14
BC15
BE13
BF16
BF10
BC11
BF8
BG7
BC7
BC9
BD6
BF12
AV6
BB6
AW7
AY6
AT10
AW11
AU11
AW9
AR11
AT6
AP6
AL7
AR7
AT12
AM6
AU7

DDR

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U3E

SYSTEM

U3D

DDR

14 DDR_A_D[0..63]

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

BJ13
BK12
BK38

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

BE21
BH14
BK14

15
15
15

DDR_B_RAS# 15
DDR_B_CAS# 15
DDR_B_WE# 15

AP52
AY54
BJ49
BJ43
BH12
BD2
AY2
AJ3

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

AR53
BA53
BH50
BK42
BH8
BB2
AV2
AM2
AT54
BB54
BJ51
BH42
BK8
BC3
AW3
AN3

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

BJ15
BJ33
BH24
BA17
BF36
BH36
BF34
BK34
BJ37
BH40
BH16
BK36
BH38
BJ11
BL37

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

DDR_B_DM[0..7] 15

DDR_B_DQS[0..7]

15

DDR_B_DQS#[0..7]

15

DDR_B_MA[0..14] 15

CANTIGA GMCH SFF_FCBGA1363

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Cantiga(2/6)-DDR2 A/B CH

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

of

58

DPST_PWM

DPST_PWM

R338 2

28 DDC2_CLK
28 DDC2_DATA

DDC2_CLK
DDC2_DATA

LVDS_IBG
For Crestline:2.4kohm
For Calero: 1.5Kohm
For Cantiga: 2.37Kohm

29

1 100K_0402_5%

R340 0_0402_5% ENABLT_R

R65 1
2 10K_0402_5%

28 IGPU_L_BKLT_EN
+3VS

R341
2.2K_0402_5%
1

R339
2.2K_0402_5%

ENAVDD

R66 1
DDC2_CLK
DDC2_DATA

2 10K_0402_5%

R67

2 2.37K_0402_1%

1
T42

LVDS_A_CLVDS_A_C+

28
28
28

LVDS_A_0LVDS_A_1LVDS_A_2-

28
28
28

LVDS_A_0+
LVDS_A_1+
LVDS_A_2+

LVDS_A_CLVDS_A_C+

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK

L37
J37
L35

L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA

B36
F50
H46
P44
K46
D46
B46
D44
B44

LVDS_A_0LVDS_A_1LVDS_A_2-

G45
F46
G41
C45

LVDS_A_0+
LVDS_A_1+
LVDS_A_2+

F44
G47
F40
A45

1
1
1

2
2
2

75_0402_5%
75_0402_5%
75_0402_5%

D40
C41
G43
B48

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3

J27
E27
G27

TVA_RTN

TV_DCONSEL_0
TV_DCONSEL_1

R16
1
R15
1
R13
1

2
150_0402_1%
2
150_0402_1%
2
150_0402_1%

J29
G29
F30

R71

2 30.1_0402_1%

CRT_VSYNC

R73

2 30.1_0402_1%
R342

R343
0_0402_5%

0_0402_5%

CRT_IRTN
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

D36
C35
J33
D32
G31

CRT_GREEN
CRT_RED

Strap Pin Table

R76
1.02K_0402_1%

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

U45
T44

PEGCOMP

1
R64

PCIE_GTX_C_MRX_N0 21
PCIE_GTX_C_MRX_N1 21
PCIE_GTX_C_MRX_N2 21
PCIE_GTX_C_MRX_N3 21
PCIE_GTX_C_MRX_N4 21
PCIE_GTX_C_MRX_N5 21
PCIE_GTX_C_MRX_N6 21
PCIE_GTX_C_MRX_N7 21
PCIE_GTX_C_MRX_N8 21
PCIE_GTX_C_MRX_N9 21
PCIE_GTX_C_MRX_N10 21
PCIE_GTX_C_MRX_N11 21
PCIE_GTX_C_MRX_N12 21
PCIE_GTX_C_MRX_N13 21
PCIE_GTX_C_MRX_N14 21
PCIE_GTX_C_MRX_N15 21

E51
F48
J55
J49
M54
M50
P52
U47
AA49
V54
V50
AB52
AC47
AC53
AD50
AF52

J47
F54
N47
H52
L53
R47
R55
T50
T52
W47
AA47
W55
Y52
AB50
AE47
AD52

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

C1073
C1074
C1075
C1076
C1077
C1078
C1079
C1080
C1081
C1082
C1083
C1084
C1085
C1086
C1087
C1088
C1089
C1090
C1091
C1092
C1093
C1094
C1095
C1096
C1097
C1098
C1099
C1100
C1101
C1102
C1103
C1104

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

CFG[4:3]

Reserved

CFG5 (DMI select)

0 = DMI x 2
1 = DMI x 4
0 = The iTPM Host Interface is enable

CFG6

1 = The iTPM Host Interface is disable

1 =(TLS)chiper suite with confidentiality

CFG8

Reserved

CFG9

0 = Reverse Lane,15->0, 14->1

(PCIE Graphics Lane Reversal)

1 = Normal Operation,Lane Number in order

CFG10 (PCIE Lookback enable)

PCIE_MTX_C_GRX_N0 21
PCIE_MTX_C_GRX_N1 21
PCIE_MTX_C_GRX_N2 21
PCIE_MTX_C_GRX_N3 21
PCIE_MTX_C_GRX_N4 21
PCIE_MTX_C_GRX_N5 21
PCIE_MTX_C_GRX_N6 21
PCIE_MTX_C_GRX_N7 21
PCIE_MTX_C_GRX_N8 21
PCIE_MTX_C_GRX_N9 21
PCIE_MTX_C_GRX_N10 21
PCIE_MTX_C_GRX_N11 21
PCIE_MTX_C_GRX_N12 21
PCIE_MTX_C_GRX_N13 21
PCIE_MTX_C_GRX_N14 21
PCIE_MTX_C_GRX_N15 21

0 =(TLS)chiper suite with no confidentiality

CFG7 (Intel Management

Engine Crypto strap)

PCIE_GTX_C_MRX_P0 21
PCIE_GTX_C_MRX_P1 21
PCIE_GTX_C_MRX_P2 21
PCIE_GTX_C_MRX_P3 21
PCIE_GTX_C_MRX_P4 21
PCIE_GTX_C_MRX_P5 21
PCIE_GTX_C_MRX_P6 21
PCIE_GTX_C_MRX_P7 21
PCIE_GTX_C_MRX_P8 21
PCIE_GTX_C_MRX_P9 21
PCIE_GTX_C_MRX_P10 21
PCIE_GTX_C_MRX_P11 21
PCIE_GTX_C_MRX_P12 21
PCIE_GTX_C_MRX_P13 21
PCIE_GTX_C_MRX_P14 21
PCIE_GTX_C_MRX_P15 21
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

000 = FSB 1066MHz

010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved

CFG[2:0] FSB Freq select

2
49.9_0402_1%

D52
G49
K54
H50
M52
N49
P54
V46
Y50
V52
W49
AB54
AD46
AC55
AE49
AF54

L47
F52
P46
H54
L55
T46
R53
U49
T54
Y46
AB46
W53
Y54
AC49
AF46
AD54

+VCC_PEG

0 = Enable
1 = Disable

CFG11

Reserved

CFG[13:12] (XOR/ALLZ)

00
01
10
11

CFG[15:14]

Reserved

CFG16 (FSB Dynamic ODT)

0 = Disabled

= Reserved
= XOR Mode Enabled
= All Z Mode Enabled
= Normal Operation(Default)

1 = Enabled

*
C

CFG[18:17]

Reserved

CFG19 (DMI Lane Reversal)

0 = Normal Operation

(Lane number in Order)

1 = Reverse Lane

PCIE_MTX_C_GRX_P0 21
PCIE_MTX_C_GRX_P1 21
PCIE_MTX_C_GRX_P2 21
PCIE_MTX_C_GRX_P3 21
PCIE_MTX_C_GRX_P4 21
PCIE_MTX_C_GRX_P5 21
PCIE_MTX_C_GRX_P6 21
PCIE_MTX_C_GRX_P7 21
PCIE_MTX_C_GRX_P8 21
PCIE_MTX_C_GRX_P9 21
PCIE_MTX_C_GRX_P10 21
PCIE_MTX_C_GRX_P11 21
PCIE_MTX_C_GRX_P12 21
PCIE_MTX_C_GRX_P13 21
PCIE_MTX_C_GRX_P14 21
PCIE_MTX_C_GRX_P15 21

CFG20 (PCIE/SDVO concurrent)

0 = Only PCIE or SDVO is operational.

1 = PCIE/SDVO are operating simu.

CANTIGA GMCH SFF_FCBGA1363

1

3VDDCCL
3VDDCDA
CRT_HSYNC

CRT_BLUE

VGA

30 CRT_VSYNC

TVA_DAC
TVB_DAC
TVC_DAC

M_BLUE
M_GREEN
M_RED

E29
30 3VDDCCL
30 3VDDCDA
30 CRT_HSYNC

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3

B34
D34
M_BLUE
M_GREEN
M_RED

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3

B40
A41
F42
D48

F26

30
30
30

L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

PEG_COMPI
PEG_COMPO

TV

R68
R69
R70

PEGCOMP trace width

and spacing is 20/25 mils.

D38
C37
K38

LVDS

28
28

layout note:Place R64 <500mils to U4 pin U45&T44.

U3C

GRAPHICS

28

PCI-EXPRESS

+3VS

Close to pin D32 and keep

30mil space to other
part/trace.

CFG5

CFG6

CFG7

CFG9

CFG10

CFG12

CFG13

CFG16

R72

2 @

2.21K_0402_1%

R74

2 @

2.21K_0402_1%

R75

2 @

2.21K_0402_1%

R77

2 @

2.21K_0402_1%

R78

2 @

2.21K_0402_1%

R79

R80

2 @

2.21K_0402_1%

R81

2 @

2.21K_0402_1%

R82

2 @ 4.02K_0402_1%

R83

2 @ 4.02K_0402_1%

@ 2.21K_0402_1%

+3VS

CFG19

CFG20

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Cantiga(3/6)-VGA/LVDS/TV

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

10

of

58

+1.05VM_DPLLA

2 0_0603_5%

1
+1.8V

M46
L45

1 0_0603_5%

VCCD_LVDS_1
VCCD_LVDS_2

4.7U_0805_10V4Z
C104

0.1U_0402_16V4Z
0.1U_0402_16V4Z

C84

C88

C86

C85

330U_D2E_2.5VM_R9

VCC_DMI_1
VCC_DMI_2
VCC_DMI_3

AM44
AN43
AL43

10U_0805_6.3V6M
C107

0.1U_0402_16V4Z
C106
1000P_0402_50V7K
C114

AXF

A SM

AB44
Y44
AC43
AA43

1
2
BLM18PG181SN1D_0603

+VCC_PEG

+1.8V
R98

+VCCP

+VCC_PEG

2 0_0603_5%

1
R99

+1.05VM_PEGPLL

+VCCP
L1
1
2
BLM18PG121SN1D_0603

2
0_1206_5%

1
+

+1.05VM_DMI

+VCCP

+1.05VM_DMI

VCCD_PEG_PLL

R101 1

2 0_0603_5%

1
B

+VCCP_D

CANTIGA GMCH SFF_FCBGA1363

+1.8V_LVDS

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4

+1.5VS
R96

+1.8V_TXLVDS

C33
A33

VTTLF1
VTTLF2
VTTLF3

K14 +VTTLF1
Y12 +VTTLF2
+VTTLF3
P2

C130
0.47U_0603_10V7K

VCCD_HPLL

T41

C129
0.47U_0603_10V7K

R102 2

+3VS_HV

VCC_HV_1
VCC_HV_2

+1.8V_TXLVDS

+1.5V_SM_CK

C128
0.47U_0603_10V7K

0.1U_0402_16V4Z
C126

C127
1U_0603_10V4Z

0.1U_0402_16V4Z
C125

AE43

+1.05VM_PEGPLL

Enable HDMI audio

+V1.05VM_AXF

BK24
BL23
BJ23
BK22

+1.5VS_TVDAC

+VCCP
R95
1
2
BLM18PG181SN1D_0603

C124
0.1U_0402_16V4Z

AH12

+1.05VM_HPLL

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

M25
N24
M23

2 0_0603_5%

C123
10U_0805_10V4Z

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

C122
0.1U_0402_16V4Z

+1.05VM_MPLL
R321 1

VCC_TX_LVDS
VCCA_SM_CK_4
VCCA_SM_CK_3
VCCA_SM_CK_2
VCCA_SM_CK_1
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8

2 0_0805_5%

+1.5VS

0.1U_0402_16V4Z

C120
0.1U_0402_16V4Z

C119
10U_0805_6.3V6M

AU27
AU28
AU29
AU31
AT31
AR31
AT29
AR29
AT28
AR28
AT27
AR27

Disable HDMI audio

+VCC_HDA

+VCCP
R93
1
2
BLM18PG181SN1D_0603

C116
220U_B2_2.5VM_R35

R100

+1.05VM_HPLL

C118
10U_0805_6.3V6M

+1.05VM_A_SM_CK

VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VCCA_SM_NCTF_3
VCCA_SM_NCTF_4
VCCA_SM_NCTF_5
VCCA_SM_NCTF_6
VCCA_SM_NCTF_7
VCCA_SM_NCTF_8
VCCA_SM_NCTF_9
VCCA_SM_NCTF_10

C117
4.7U_0805_10V4Z

AT24
AR24
AT22
AR22
AT21
AR21
AT19
AR19
AT18
AR18

+1.5VS_TVDAC

POWER

DMI

C113

C112

C111

+1.5VS_QDAC

N32

C109
0.1U_0402_16V4Z

N34

+1.5V
R89

C108
0.01U_0402_16V7K

1U_0603_10V4Z

2 150U_B2_6.3V-M~D

4.7U_0805_10V4Z

+
C110

10U_0805_6.3V6M

C1045

2 0_0805_5%

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_12
VCCA_SM_13
VCCA_SM_14
VCCA_SM_15
VCCA_SM_16
VCCA_SM_17

0.1U_0402_16V4Z

R97

AW24
AU24
AW22
AU22
AU21
AW20
AU19
AW18
AU18
AW16
AU16
AT16
AR16
AU15
AT15
AR15
AW14

LVDS

+1.05VM_A_SM

+VCCP

VCCA_PEG_PLL

SM CK

AG43

+1.05VM_PEGPLL

0.1U_0402_16V4Z

VCCD_QDAC
VCCD_TVDAC

A31

0_0402_5%

C121

VCCA_PEG_BG

HV

AJ43

1
C105

VCC_HDA

PEG

2 0_0603_5%

@R92
@
R92

+VCCP +1.5V_SM_CK

0.1U_0402_16V4Z
C103

TV

VSSA_LVDS

+3VS
R91
1
2
BLM18PG181SN1D_0603

K30

+VCC_HDA

VTTLF

R94

VCCA_TV_DAC

D TV/CRT HDA

VCCA_LVDS1
VCCA_LVDS2

2
+1.5VS

VTT

CRT

VCCA_MPLL

A PEG A LVDS

V44

VCCA_HPLL

C101
0.1U_0402_16V4Z

U43
U41

C102
1000P_0402_50V7K

PLL

AE1

R88
1
2
BLM18PG181SN1D_0603

+3VS_TVDAC

2 0_0603_5%

C98
10U_0805_6.3V6M

+1.05VM_MPLL

+1.05VM_DPLLB

C97
0.1U_0402_16V4Z

AF10

C83
1U_0603_10V4Z

VCCA_DPLLB

+1.05VM_HPLL

C99
10U_0805_6.3V6M

VCCA_DPLLA

L49

C96

J45

+1.05VM_DPLLB

1
1

C100
0.01U_0402_16V7K

+1.05VM_DPLLA

1
C81

+1.8V_TXLVDS

+1.5VS_PEG_BG

VCCA_DAC_BG
VSSA_DAC_BG

4.7U_0805_10V4Z

L31
M33
1

C87
4.7U_0805_10V4Z

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13

2.2U_0805_16V4Z

VCCA_CRT_DAC

0.47U_0603_10V7K

C93
22U_0805_6.3V

R87
2
1
BLM18PG181SN1D_0603

C94
0.01U_0402_16V7K

0.01U_0402_16V7K

C90

C92
0.1U_0402_16V4Z

C91
10U_0603_6.3V

C89

0.1U_0402_16V4Z

1
D

J31
+3VS_DAC_BG

+3VS

R85
C82
10U_0805_10V4Z

+VCCP

R13
T12
R11
T10
R9
T8
R7
T6
R5
T4
R3
T2
R1

+VCCP

+V1.05VM_AXF

R84
1
2
BLM18PG181SN1D_0603

U3H

+3VS_DAC_CRT
+3VS
BLM18PG181SN1D_0603
R86
2
1

+VCCP

+VCCP

2
D1

R103 1
1
CH751H-40_SC76

2 10_0402_5%

R104 1

2 0_0402_5%

+3VS_HV

+3VS

2
+1.5VS_QDAC

+1.5VS
R105
1
2
BLM18PG181SN1D_0603

1
C133

4.7U_0603_6.3V

C132
0.1U_0402_16V4Z

C131
0.01U_0402_16V7K

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Cantiga(4/6)-PWR

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

11

of

58

U3G
+VCCP

AT38
AR38
AN38
AM38
AL38
AG38
AE38
AA38
Y38
W38
U38
T38
R38
AT37
AR37
AN37
AM37
AL37
AJ37
AH37
AG37
AE37
AD37
AC37
AA37
Y37
W37
U37
T37
R37
AT35
AR35
U35
AT34
AR34
U34
T34
R34

C150

C149

C148

1U_0603_10V4Z

2
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38

10U_0805_6.3V

C147

C146
330U_D2E_2.5VM_R9

10U_0805_6.3V

+VCCP

6326.84mA

VCC GFX NCTF

4.7U_0805_10V4Z
C136

0.22U_0402_10V4Z
C135

0.1U_0402_16V4Z
C134

AJ16
AH16
AD16
AC16
AA16
U16
T16
R16
AM15
AL15
AJ15
AH15
AG15
AE15
AA15
Y15
W15
U15
T15

VCC_AXG_SENSE
VSS_AXG_SENSE

C155 1U_0603_10V4Z

1
1

C154 1U_0603_10V4Z

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

C153 0.47U_0402_6.3V6K

AU45
BF52
BB38
BA19
BE9
AU9
AL9

C152 0.22U_0603_10V7K

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

C157 0.1U_0402_16V4Z

AG13
AE13

VCC_AXG_62
VCC_AXG_63
VCC_AXG_64
VCC_AXG_65
VCC_AXG_66
VCC_AXG_67
VCC_AXG_68
VCC_AXG_69
VCC_AXG_70
VCC_AXG_71
VCC_AXG_72
VCC_AXG_73
VCC_AXG_74
VCC_AXG_75
VCC_AXG_76
VCC_AXG_77
VCC_AXG_78
VCC_AXG_79
VCC_AXG_80

C151 0.22U_0603_10V7K

PAD T43
PAD T44

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_43
VCC_AXG_44
VCC_AXG_45
VCC_AXG_46
VCC_AXG_47
VCC_AXG_48
VCC_AXG_49
VCC_AXG_50
VCC_AXG_51
VCC_AXG_52
VCC_AXG_53
VCC_AXG_54
VCC_AXG_55
VCC_AXG_56
VCC_AXG_57
VCC_AXG_58
VCC_AXG_59
VCC_AXG_60
VCC_AXG_61

T32
U31
T31
R31
U29
T29
R29
U28
U27
T27
R27
U25
T25
R25
U24
U22
T22
R22
U21
T21
R21
AM19
AL19
AH19
AG19
AE19
AD19
AC19
W19
U19
AM18
AL18
AJ18
AH18
AG18
AE18
AD18
AC18
AA18
Y18
W18
U18
T18
R18

C156 0.1U_0402_16V4Z

CANTIGA GMCH SFF_FCBGA1363

W32
AG31
AE31
AD31
AC31
AA31
Y31
W31
AH29
AG29
AE29
AD29
AC29
AA29
Y29
W29
AH28
AG28
AE28
AA28
AH27
AG27
AE27
AD27
AC27
AA27
Y27
W27
AH25
AD25
AC25
W25
AJ24
AH24
AG24
AE24
AD24
AC24
AA24
Y24
W24
AM22
AL22
AJ22
AH22
AG22
AE22
AD22
AC22
AA22
AM21
AL21
AJ21
AH21
AD21
AC21
AA21
Y21
W21
AM16
AL16

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44

VCC SM LF

VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33

VCC GFX

Y34
W34
AM32
AL32
AJ32
AH32
AE32
AD32
AA32
AM31
AL31
AJ31
AH31
AM29
AL29
AM28
AL28
AJ28
AM27
AL27
AM25
AL25
AJ25
AM24
N36

0.1U_0402_16V4Z

VCC_35
VCC_36

+VCCP

VCC NCTF

AC34
AA34

VCC CORE

VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34

POWER

AJ40
AH40
AG40
AE40
AD40
AC40
AA40
Y40
AN35
AM35
AJ35
AH35
AD35
AC35
W35
AM34
AL34
AJ34
AH34
AG34
AE34
AD34

C140

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

0.01U_0402_16V7K
C139

C145

0.1U_0402_16V4Z
C144

0.22U_0402_10V4Z
C143

0.22U_0402_10V4Z
C142

10U_0805_6.3V6M

C141
220U_B2_2.5VM_R35

AT41
AR41
AN41
AJ41
AH41
AD41
AC41
Y41
W41
AT40
AM40
AL40

10U_0805_6.3V6M
C138

+VCCP
D

10U_0805_6.3V6M
C137

330U_D2E_2.5VM_R9

U3F

BB36
BE35
AW34
AW32
BK30
BH30
BF30
BD30
BB30
AW30
BL29
BJ29
BG29
BE29
BC29
BA29
AY29
BK28
BH28
BF28
BD28
BB28
BL27
BJ27
BG27
BE27
BC27
BA27
AY27
AW26
BF24
BL19
BB16

VCC SM

+1.5V

VCC GFX

Extnal Graphic: 1210.34mA

integrated Graphic: 1930.4mA

POWER

3000mA

CANTIGA GMCH SFF_FCBGA1363

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Cantiga(5/6)-PWR/GND

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

12

of

58

U3J
U3I

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

C43
A43
BD42
H42
BG41
AY41
AU41
AM41
AL41
AG41
AE41
AA41
R41
M41
E41
BD40
AU40
AR40
AN40
W40
U40
T40
R40
K40
H40
BL39
BG39
BA39
E39
C39
A39
BD38
AU38
H38
BG37
AU37
M37
E37
BD36
AW36
H36
BL35
BG35
AY35
AU35
AL35
AG35
AE35
AA35
Y35
M35
E35
A35
BD34
AU34
AN34
H34
BL33
BG33
AY33
E33
BD32
AU32
AN32
AG32
AC32
Y32
H32
B32
BJ31
BG31
AY31
AN31
M31
E31
N30
H30
AN29
AJ29
M29
A29
AW28
AN28
AD28
AC28
Y28
W28
H28
F28
AN27
AJ27
M27
BF26
BD26
N26
H26
BJ25
AY25
AU25

CANTIGA GMCH SFF_FCBGA1363

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299

AM8
AK8
AH8
AF8
AD8
AB8
Y8
V8
P8
M8
K8
H8
BJ7
E7
BF6
BC5
BA5
AW5
AU5
AR5
AN5
AL5
AJ5
AG5
AE5
AC5
AA5
W5
U5
N5
L5
J5
G5
C5
BH4
BE3
U3
E3
BC1
AW1
AR1
AL1
AG1
AC1
W1
N1
J1
AU43
BB42
AW38
BA35
L29
N28
N22
N20
N14
AL13
B10
AN13

VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358

VSS

N42
N40
N38
M39

VSS_359
VSS_360
VSS_361
VSS_362

VSS NCTF

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

VSS SCB

BA55
AU55
AN55
AJ55
AE55
AA55
U55
N55
BD54
BG53
AJ53
AE53
AA53
U53
N53
J53
G53
E53
K52
BG51
BA51
AW51
AU51
AR51
AN51
AL51
AJ51
AG51
AE51
AC51
AA51
W51
U51
R51
N51
L51
J51
G51
C51
BK50
AM50
K50
BG49
E49
C49
BD48
BB48
AY48
AV48
AT48
AP48
AM48
AK48
AH48
AF48
AD48
AB48
Y48
V48
T48
P48
M48
K48
H48
BL47
BG47
E47
C47
A47
BD46
AY46
AM46
AK46
AH46
BG45
AE45
AC45
AA45
W45
R45
N45
E45
BD44
BB44
AV44
AK44
AH44
AF44
AD44
K44
H44
BL43
BG43
AY43
AR43
W43
R43
M43
E43

AN25
AG25
AE25
AA25
Y25
E25
A25
BD24
AN24
AL24
H24
BG23
AY23
E23
BD22
BB22
AN22
Y22
W22
H22
BL21
BG21
AY21
AN21
AG21
AE21
M21
E21
A21
BD20
H20
BG19
AY19
M19
E19
BD18
N18
H18
BL17
BG17
AY17
M17
E17
A17
BD16
AN16
AG16
AE16
Y16
W16
N16
H16
BG15
AY15
AN15
AD15
AC15
R15
M15
E15
BD14
H14
BL13
BG13
AY13
AU13
AR13
AJ13
AC13
AA13
W13
U13
M13
E13
A13
BD12
AV12
AP12
AM12
AK12
AB12
V12
P12
H12
BG11
AG11
E11
BD10
AY10
AP10
H10
BL9
BG9
E9
A9
BD8
BB8
AY8
AV8
AT8
AP8

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23

AJ38
AH38
AD38
AC38
T35
R35
AT32
AR32
U32
R32
T28
R28
AT25
AR25
T24
R24
AN19
AJ19
AA19
Y19
T19
R19
AN18

VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
VSS_SCB_6
VSS_SCB_7

BL55
BL1
A55
D1
B55
B2
A4

CANTIGA GMCH SFF_FCBGA1363

A

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Cantiga(6/6)-PWR/GND

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

13

of

58

+1.5V
+V_DDR3_DIMM_REF

9 DDR_A_DQS#[0..7]

JDIMM1

9 DDR_A_D[0..63]
8,15 +V_DDR3_DIMM_REF
9 DDR_A_DM[0..7]

DDR_A_D0
DDR_A_D1

9 DDR_A_DQS[0..7]

DDR_A_DM0

9 DDR_A_MA[0..14]

DDR_A_D2
DDR_A_D3
D

DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1

+1.5V

DDR_A_D10
DDR_A_D11

C115
1000P_0402_50V7K

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

Add C115 for EMI request

2

DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27

Layout Note:
Place near JDIMM1

DDR_CKE0_DIMMA

8 DDR_CKE0_DIMMA

Layout Note: Place these 4 Caps near Command

and Control signals of DIMMA

DDR_A_BS2

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

C1111

C1110

C1109

C1108

DDR_A_MA3
DDR_A_MA1
1

C1115

C1114

0.1U_0402_16V4Z

C1113

0.1U_0402_16V4Z

C1112

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C1107

DDR_A_MA8
DDR_A_MA5

10U_0805_6.3V6M

10U_0805_6.3V6M

C1106

+1.5V

M_CLK_DDR0
M_CLK_DDR#0

8 M_CLK_DDR0
8 M_CLK_DDR#0

2
9

DDR_A_MA10
DDR_A_BS0

DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

9
DDR_A_WE#
9 DDR_A_CAS#

DDR_A_MA13
DDR_CS1_DIMMA#

8 DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

Layout Note:
Place near JDIMM1.203 & JDIMM1.204

DDR_A_DM5
1

DDR_A_D42
DDR_A_D43
C1123

C1122

10U_0805_6.3V6M

1U_0603_10V4Z
C1121

1U_0603_10V4Z
C1120

1U_0603_10V4Z
C1119

1U_0603_10V4Z

DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
1 R347
2
10K_0402_5%

1
C1125

Security Classification

R348
10K_0402_5%
2
1

C1124

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z

+3VS

205

G1

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

G2

206

TYCO_2-2013289-1
CONN@

DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
D

DDR_A_D12
DDR_A_D13
DDR_A_DM1
SM_DRAMRST#

DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31

DDR_CKE1_DIMMA

DDR_CKE1_DIMMA 8
C

DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
M_ODT1

M_CLK_DDR1 8
M_CLK_DDR#1 8
DDR_A_BS1 9
DDR_A_RAS# 9
DDR_CS0_DIMMA# 8
M_ODT0
8
M_ODT1

DDR_VREF_CA_DIMMA
DDR_A_D36
DDR_A_D37

+V_DDR3_DIMM_REF

R346
1

0_0402_5%

DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PM_EXTTS#0
ICH_SMBDATA
ICH_SMBCLK

PM_EXTTS#0 8,15
ICH_SMBDATA 15,16,19,33,36
ICH_SMBCLK 15,16,19,33,36

+0.75VS

+0.75VS

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

SM_DRAMRST# 8,15

DDR_A_D14
DDR_A_D15

Compal Secret Data

2009/07/25

Issued Date

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

C1118

DDR_A_D40
DDR_A_D41

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

C1117

DDR_A_D34
DDR_A_D35

+0.75VS

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

0.1U_0402_16V4Z

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

2.2U_0805_16V4Z

DDR_A_DQS#4
DDR_A_DQS4

+1.5V

DDR3 SO-DIMM A
5.2H Standard
Compal Electronics, Inc.
Title

DDR3-SODIMM A
Size Document Number
Custom
Date:

Rev
1.0

LA-5811P

Tuesday, December 29, 2009

Sheet
1

14

of

58

+1.5V

+1.5V

+V_DDR3_DIMM_REF
9 DDR_B_DQS#[0..7]

JDIMM2

9 DDR_B_D[0..63]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

8,14 +V_DDR3_DIMM_REF
DDR_B_D0
DDR_B_D1

9 DDR_B_DM[0..7]
9 DDR_B_DQS[0..7]

DDR_B_DM0

9 DDR_B_MA[0..14]

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2

Layout Note:
Place near JDIMM2

DDR_B_D18
DDR_B_D19

Layout Note: Place these 4 Caps near Command

and Control signals of DIMMB

DDR_B_D24
DDR_B_D25

+1.5V

DDR_B_DM3

C1131

C1130

C1129

C1128

C1127

C1135

C1134

0.1U_0402_16V4Z

C1133

0.1U_0402_16V4Z

C1132

0.1U_0402_16V4Z

10U_0805_6.3V6M

0.1U_0402_16V4Z

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C1126

DDR_B_D26
DDR_B_D27

DDR_CKE2_DIMMB

8 DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

Layout Note:
Place near JDIMM2.203 & JDIMM2.204

M_CLK_DDR2
M_CLK_DDR#2

8 M_CLK_DDR2
8 M_CLK_DDR#2
+0.75VS

9 DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

9 DDR_B_WE#
9 DDR_B_CAS#
1

DDR_B_MA13
DDR_CS3_DIMMB#

8 DDR_CS3_DIMMB#

C1141

10U_0805_6.3V6M
C1140

1U_0603_10V4Z
C1139

1U_0603_10V4Z
C1138

1U_0603_10V4Z
C1137

1U_0603_10V4Z

DDR_B_MA10
DDR_B_BS0

DDR_B_D32
DDR_B_D33

DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
+1.5V

DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51

C196
1000P_0402_50V7K

DDR_B_D56
DDR_B_D57

Add C196 for EMI request

2

DDR_B_DM7
DDR_B_D58
DDR_B_D59
1 R350
2
10K_0402_5%

0.1U_0402_16V4Z

+3VS
A

1
R351

10K_0402_5% 205

C1144

G1

G2

TYCO_2-2013310-1
CONN@

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13
DDR_B_DM1
SM_DRAMRST#

SM_DRAMRST# 8,14

DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31

DDR_CKE3_DIMMB

DDR_CKE3_DIMMB 8

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
M_ODT3

M_CLK_DDR3 8
M_CLK_DDR#3 8
DDR_B_BS1 9
DDR_B_RAS# 9
DDR_CS2_DIMMB# 8
M_ODT2
8
M_ODT3

DDR_VREF_CA_DIMMB

R349
1

2009/07/25

+V_DDR3_DIMM_REF

8
2 0_0402_5%

DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PM_EXTTS#0
ICH_SMBDATA
ICH_SMBCLK

PM_EXTTS#0 8,14
ICH_SMBDATA 14,16,19,33,36
ICH_SMBCLK 14,16,19,33,36

+0.75VS

+0.75VS

2010/07/25

Deciphered Date

DDR3 SO-DIMM B
9.2H Standard

206

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

DDR_B_MA14

Compal Secret Data

Security Classification
Issued Date

DDR_B_DQS#0
DDR_B_DQS0

C1143

DDR_B_D40
DDR_B_D41

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_D4
DDR_B_D5

C1142

DDR_B_D34
DDR_B_D35

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

0.1U_0402_16V4Z

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2.2U_0805_16V4Z

DDR_B_DQS#4
DDR_B_DQS4

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

Title

Compal Electronics, Inc.

DDR3-SODIMM B

Size

Document Number

Rev
1.0

LA-5811P
Date:

Tuesday, December 29, 2009

Sheet
1

15

of

58

200

800

100

33.3

166

667

100

33.3

2
0_1206_5%

Mount C157 & C166 tp solve

WWAN noise issue. 1/23

+1.05VM_CK505

1
R122

47P_0402_50V8J~D
C1070

+VCCP

0.1U_0402_16V4Z
C228

33.3

2
0_1206_5%

0.1U_0402_16V4Z
C227

100

1
R121

10U_0805_10V4Z
C226

1066

+3VM_CK505

+3VS

0.1U_0402_16V4Z
C225

266

47P_0402_50V8J~D
C1069

PCI
MHz

0.1U_0402_16V4Z
C222

SRC
MHz

0.1U_0402_16V4Z
C221

FSB
MHz

0.1U_0402_16V4Z
C220

CPU
MHz

0.1U_0402_16V4Z
C219

CLKSEL0

0.1U_0402_16V4Z
C218

FSLA

CLKSEL1

0.1U_0402_16V4Z
C217

FSLB

CLKSEL2

10U_0805_10V4Z
C216

FSLC

0.1U_0402_16V4Z
C224

10U_0805_10V4Z
C223

+VCCP

R123
@ 56_0402_5%

R124 1

CLKREQ#_B_R
CLKREQG_WWAN#_R

FSA

1
2.2K_0402_5%

1
R134

CPU_BSEL0

2
1K_0402_5%

R131

1 475_0402_1%
1 475_0402_1%

+3VM_CK505

2
0_0402_5%

R135
@ 1K_0402_5%
2

VDDREF
VDDPCI
VDD48
VDD96_IO
VDDPLL3
VDDSRC
VDDCPU

+VCCP
31
38
52
62
66

2
1

R136
@ 1K_0402_5%

FSB
5

CPU_BSEL1

R137
1K_0402_5%
1
2

VDDPLL3_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO

37 CLK_PCI_EC
33 CLK_DEBUG_PORT_1

1K_0402_5%
R138

CLK_PCI_EC

22_0402_5% 1
22_0402_5% 1

2 R142
2 R352

PCI_CLK1

13

PCI2_TME

14
15

2 R145

27_SEL

16

ITP_EN

17

CLK_XTAL_IN

CLK_XTAL_OUT

ICH_SMBCLK 14,15,19,33,36
ICH_SMBDATA 14,15,19,33,36

PCI_STOP#
CPU_STOP#

H_STP_PCI# 19
H_STP_CPU# 19

CPUT0_LPR_F
CPUC0_LPR_F

71
70

5
4

19 CLK_48M_ICH

FSC

61
60

PCI

CR#6

PCI2/TME

SRCT6_LPR
SRCC6_LPR

PCI3

PCI4/27_Select

SRCT10_LPR
SRCC10_LPR

PCI_F5/ITP_EN

CR#11
SRCT11_LPR
SRCC11_LPR

X1
CR#9
X2

1
10K_0402_5%
2
0_0402_5%

1
R148

CPU_BSEL2

1
R147

2
1K_0402_5%

20

FSB

USB_48MHz/FSLA

CLK_14M_ICH

33_0402_1% 1

R151 FSC

+3VS

+3VS

26

+3VS

C234
22P_0402_50V8J

R156
@10K_0402_5%

34
42

1
27_SEL

ITP_EN

PCI2_TME

R157
10K_0402_5%

57
56

50
51

CLK_PCIE_WLAN 33
CLK_PCIE_WLAN# 33
CLKREQG_WWAN#_R

46
48
47

CLK_PCIE_WWAN 33
CLK_PCIE_WWAN# 33
VGA_CLKREQ#

44
45

VGA_CLKREQ#

VGA_CLKREQ# 21

1 R353
2
10K_0402_5%

+3VS

CLK_PCIE_VGA 21
CLK_PCIE_VGA# 21
CLKREQ_LAN# 34
CLK_PCIE_LAN 34
CLK_PCIE_LAN# 34

CR#3

37

R_PCIE_ICH
R_PCIE_ICH#

35
36

SRCT2_LPR/SATAT_LPR
SRCC2_LPR/SATAC_LPR

32
33

RP28 2
1

3 0_0404_4P2R_5%
4

CLK_PCIE_ICH 19
CLK_PCIE_ICH# 19

SRCT0_LPR/DOTT_96_LPR
SRCC0_LPR/DOTC_96_LPR

24
25

GNDSRC
GNDPCI

27MHz_NonSS/SRCT1_LPR/SE1
27MHz_SS/SRCC1_LPR/SE2

CLK_PCIE_SATA 18
CLK_PCIE_SATA# 18
CLK_MCH_DREFCLK 8
CLK_MCH_DREFCLK# 8

28
29

MCH_SSCDREFCLK 8
MCH_SSCDREFCLK# 8

GND48
GND

CK_PWRGD/PD#

CK_PWRGD

19

GND
GNDCPU

CR#A

CLKSATAREQ#_R

21

GNDSRC
GNDSRC

REF1

GNDREF

T_PAD

ICS9LPRS387BKLFT(SA000020H10)

73

SLG8SP556VTR(SA000020K00)

Compal Secret Data

Security Classification
2009/07/25

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

2 10K_0402_5%

CLK_PCIE_CR 35
CLK_PCIE_CR# 35
CLKREQ_WLAN#_R

49

43

ICS9LPRS397DKLFT MLF 72P

Issued Date

+3VS

R158
@10K_0402_5%
1

69
R155
10K_0402_5%

Y1
2

R154
@10K_0402_5%
1

R153
10K_0402_5%

30

C233
22P_0402_50V8J

22

14.318MHZ_16PF_X5H01431AFG1H-X

18

CLK_XTAL_IN

2 10K_0402_5%

FSLC/TEST_SEL/REF0

59

CLK_MCH_3GPLL 8
CLK_MCH_3GPLL# 8
CLKREQ_CR#_R
R218 1

58

39
40

SRCT3_LPR
SRCC3_LPR

R150
0_0402_5%

CLK_XTAL_OUT

+3VS

CLKREQ_WLAN# 33
CLKSATAREQ# 19

CLK_MCH_BCLK 8
CLK_MCH_BCLK# 8

41

FSLB/TEST_MODE

MCH_CLKSEL2 8
19 CLK_14M_ICH

2 10K_0402_5%

475_0402_1%
475_0402_1%

CLKREQ#_B_R

SRCT4_LPR
SRCC4_LPR

2
R146

FSA

65
64
63

CR#4
2 R149

1 CLK_PCI_EC
@ 4.7P_0402_50V8C

CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4

68
67

SRCT7_LPR
SRCC7_LPR

15_0402_1% 1

11

54
53

SRCT9_LPR
SRCC9_LPR

CLK_48M_ICH

C229

R133 1

CPUT2_ITP_LPR/SRCT8_LPR
CPUC2_ITP_LPR/SRCC8_LPR

D
R141
@ 0_0402_5%

1
1

10
9

CR7#

2
G
Q59
2N7002_SOT23

37 EC_FSB_SEL

33_0402_1% 1

17 CLK_PCI_ICH

R128 2
R129 2

SCLK
SDATA

CR10#

CLK_PCI_ICH

Place close to U5

+3VS

CPUT1_LPR_F
CPUC1_LPR_F

MCH_CLKSEL1 8

C214

1 CLK_48M_ICH
@ 5P_0402_50V8C
2 CLK_14M_ICH
12P_0402_50V8J
1 CLK_PCI_ICH
@ 4.7P_0402_50V8C

R125 1
CLKREQ_WLAN#_R
CLKSATAREQ#_R

NC

+1.05VM_CK505

U4
6
12
19
23
27
55
72

+1.05VM_CK505

2 10K_0402_5%

C213

+3VS

CLKREQ#_B 8
CLKREQ_WWAN# 33
R132 1

MCH_CLKSEL0 8

2
R130

R126 2
R127 2

2 10K_0402_5%

C212

Title

Compal Electronics, Inc.

CLOCK GENERATOR

Size

Document Number

Rev
1.0

LA-5811P
Date:

Tuesday, December 29, 2009

Sheet
1

16

of

58

+3VS

PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

U5B
A11
B12
A10
C12
A8
A12
E10
C11
B9
D8
A4
E8
A3
D9
C8
C2
D7
B3
D11
B6
D5
D3
F4
E3
E4
B2
C4
C1
D1
E2
J4
H2

PCI_PLOCK#
PCI_IRDY#
PCI_SERR#
PCI_PERR#

+3VS

2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
1
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
ACCEL_INT#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PCI_REQ0#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_REQ1#
PCI_REQ2#

F1
F5
F2
C7

PCI

REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
C/BE0#
C/BE1#
C/BE2#
C/BE3#

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
2 0_0402_5%

DGPU_SELECT# 28,29,30

PCI_REQ3#
PCI_GNT3#

D10
A5
E6
C9
C3
B1
T3
A7
D4
C5
H5
A6
A2
B8

PCI_IRDY#

PLTRST#
PCICLK
PME#

A21
B5
T1

PLT_RST#
CLK_PCI_ICH
EC_PME#

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

PCI_REQ2# R354 1

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#

G4
E1
A9
E12
B11
C10
D6
C6

G3
G1
F3
H4

PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

ACCEL_INT#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PLT_RST#
8,35,37
CLK_PCI_ICH 16
EC_PME#
34,37

ACCEL_INT# 36

ICH9-M SFF ES_FCBGA569

PCI_REQ3#
+3VS
5

1
R167
1
R168
1
R169
1
R170
1
R171
1
R172
1
R173
2
R174
1
R175
1
R176
1
R178
1
R179

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

U10

NC7SZ08P5X_NL_SC70-5
Y

2
R356

19 DGPU_HOLD_RST#

1
100_0402_5%

PEG_RST#

For VGA/B

21

PLT_RST#
R355
1
2
0_0402_5%

2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%

1
R159
1
R160
1
R161
1
R162
1
R163
1
R164
1
R165
1
R166

R357
100K_0402_5%

Place closely pin B10

Boot BIOS Strap

CLK_PCI_ICH

PCI_GNT0#

SPI_CS#1

Boot BIOS Location

SPI

PCI

A16 swap override Strap

Low= A16 swap override Enble
PCI_GNT3# High= Default*

PCI_GNT3#
1

2
R181
@ 1K_0402_5%

@
C235
8.2P_0402_50V

LPC

@
R180
10_0402_5%

PCI_GNT0#

19 KBC_SPI_CS1#

R183
@ 1K_0402_5%

R182
1K_0402_5%
@

DEL J3. 9/29

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

ICH9(1/4)-PCI/INT

Size

Document Number

Rev
1.0

LA-5811P
Date:

Tuesday, December 29, 2009

Sheet
1

17

of

58

RTC Reset SW
PJP1
D

ICH_RTCRST#

JUMP_43X39

1
C1145
0.01U_0402_50V7K

LPC_AD[0..3] 33,37

U5A

D14

PAD T47
@ C1047 12P_0402_50V8J
HDA_BITCLK 1
2

R198

+1.5VS
36
36

36

36

HDA_SDOUT

R46

R358 1
R359 1

28,30 DGPU_EDIDSEL#
28 DGPU_PWMSEL#
38

HDD

32
32
32
32

SATA_IRX_DTX_N0
SATA_IRX_DTX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

SATA_LED#

+3VS
SATA_IRX_DTX_N0
SATA_IRX_DTX_P0
SATA_ITX_DRX_N0 C1051
SATA_ITX_DRX_P0 C1052

LAN_TXD0
LAN_TXD1
LAN_TXD2

D15

GPIO56

H22
H21

GLAN_COMPI
GLAN_COMPO

AB6
AE6
AC6
AA5
2 33_0402_1% HDA_SDOUT_R

D13
C13
A13

AC7

2 0_0402_5%
2 0_0402_5%

AD8
AB8
AC9

2
R209
1
1

1
10K_0402_5%

AE14
AD14
2 0.01U_0402_16V7K SATA_TXN0_R AC15
2 0.01U_0402_16V7K SATA_TXP0_R AD15
AD13
AC13
AA14
AB14

+RTCVCC

GATEA20

DPRSTP#
DPSLP#

H_DPRSTP_R#

AD25

H_FERR#_R

FERR#
CPUPWRGD
IGNNE#

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AD23

4
4
4
37

H_SMI#

H_NMI
H_SMI#

4
4

AC25

H_STPCLK#

H_STPCLK#

AC23

THRMTRIP_ICH#

SATARBIAS#
SATARBIAS

H_FERR#

Place Close to U8.

+3VS

H_IGNNE#

NMI
SMI#

SATA_CLKN
SATA_CLKP

H_FERR#

2 56_0402_5%

H_PWRGOOD 5

AD21
AC21

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

5,8,51

AE22

H_INIT#
H_INTR
KB_RST#

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

R192
56_0402_5%
H_DPRSTP#

KB_RST#

TP11

SATALED#

H_DPSLP#
R195

37
4
2 0_0402_5%

AE21
AD24
L1

THRMTRIP#

HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34

GATEA20
H_A20M#
R194

INIT#
INTR
RCIN#

HDA_RST#

+VCCP

T46 PAD

AE23
AE24

STPCLK#

HDA_SDOUT

LPC_FRAME# 33,37

H1
J1
N3
AB23

HDA_BIT_CLK
HDA_SYNC

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

J2

A20GATE
A20M#

LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2

AA7

HDA_SDIN0

LDRQ0#
LDRQ1#/GPIO23

GLAN_CLK

A14
D12
B14

AE7
AB7

2 33_0402_1% HDA_RST#_R

R119 1

HDA_RST#

2 24.9_0402_1% GLAN_COMP
2 33_0402_1% HDA_BITCLK_R
2 33_0402_1% HDA_SYNC_R

R120 1
R8
1

HDA_BITCLK
HDA_SYNC

36

FWH4/LFRAME#

G22

INTVRMEN
LAN100_SLP

E25
D25

RTCRST#
SRTCRST#
INTRUDER#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

H3
J3
K5
L3

+VCCP

GATEA20 R196
KB_RST# R197

2 10K_0402_5%
2 10K_0402_5%

1
1

ICH_INTVRMEN
LAN100_SLP

RTC
LPC

G24
C24
C23

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

LAN / GLAN
CPU

C1044
1U_0603_10V4Z

ICH_RTCRST#
ICH_SRTCRST#
SM_INTRUDER#

RTCX1
RTCX2

IHDA

2
R318
20K_0402_5%

F25
G25

SATA

+RTCVCC

ICH_RTCX1
ICH_RTCX2

AC22

T48 PAD

R206

R201
56_0402_5%
2 54.9_0402_1%

H_THERMTRIP# 4,8

placed within 2" from

ICH9M

AD12
AE12
AB12
AA12
AC11
AD11
AB10
AA10
AC16
AB16

CLK_PCIE_SATA#
CLK_PCIE_SATA

AD10
AE10

R212

CLK_PCIE_SATA# 16
CLK_PCIE_SATA 16
B

2 24.9_0402_1%

Within 500 mils

ICH9-M SFF ES_FCBGA569

0
1
0
1

RV
XOR
Normal(D)
PCIE Bit1

XOR CHAIN ENTRANCE STRAP:RSVD

C247

OUT

IN

Description

2
NC

HDA_SDOUT_CODEC

Y2

NC

2
12P_0402_50V8J

0
0
1
1

ICH_RSVD

32.768KHZ_12.5P_1TJS125BJ2A251

1U_0603_10V4Z

ICH_RTCX2

R187

Change from
& 0.1u to 1u. 9/29

10M_0402_5%

C246

15P_0402_50V8J

1
R186

ICH_RTCX1
R215
2
R188
0_0402_5%
2
R189
0_0402_5%

R185

LAN100_SLP
2
330K_0402_1%
SM_INTRUDER#
2
1M_0402_5%
ICH_INTVRMEN
2
330K_0402_1%
ICH_SRTCRST#
2
20K_0402_5%
1
180K to 20K
C236

1
R184

+3VS

1
R191
1
R193

HDA_SDOUT
2
@ 1K_0402_5%
ICH_RSVD
2
@ 1K_0402_5%

ICH_RSVD

19

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

ICH9(2/4)_LAN,HD,IDE,LPC

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

18

of

58

+3VS

1
R258
1
R259
1
R261
1
R367

37
37
DGPU_PWR_EN

23,40,47,50 DGPU_PWR_EN

R263 1

17 DGPU_HOLD_RST#
PAD T53
PAD T54
16 CLKSATAREQ#
32,36

+3VALW

FFS_INT2
1
R268

+3VS

RP29
5
6
7
8

4
3
2
1

R264 1

2 @ 1K_0402_5%

PAD T59

10K_1206_8P4R_5%
RP30
5
4 USB_OC#1
6
3 USB_OC#6
7
2 GPIO44
8
1 USB_OC#2

WLAN

33
33
33
33

PCIE_IRX_LANTX_N1
PCIE_IRX_LANTX_P1
PCIE_ITX_LANRX_N1
PCIE_ITX_LANRX_P1

PCIE_IRX_WLANTX_N2
PCIE_IRX_WLANTX_P2
PCIE_ITX_WLANRX_N2
PCIE_ITX_WLANRX_P2

C1071 1
C1072 1

C265 1
C266 1

K4
AB20
C19
AB17
AC17
AD17

CLKRUN#/GPIO32
WAKE#
SERIRQ
THRM#
VRMPWRGD
TP12
GPIO1
GPIO6
GPIO7
GPIO8
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5

R274
2.2K_0402_5%
2

ICH_SMBDATA

Q8
RHU002N06_SOT323
3

ICH_SMB_DATA

1
D

ICH_SMBCLK

ICH_SMB_CLK

+3VS

Q9
RHU002N06_SOT323

33
33
33
33

PCIE_IRX_WWANTX_N4
PCIE_IRX_WWANTX_P4
PCIE_ITX_WWANRX_N4
PCIE_ITX_WWANRX_P4
35
35
35
35

PCIE_IRX_CRTX_N5
PCIE_IRX_CRTX_P5
PCIE_ITX_CRRX_N5
PCIE_ITX_CRRX_P5

P25
P24
2 0.1U_0402_10V7K PCIE_C_TXN2 P21
PCIE_C_TXP2
0.1U_0402_10V7K
2
P22

C269 1
C270 1

M25
M24
2 0.1U_0402_10V7K PCIE_C_TXN4 L24
2 0.1U_0402_10V7K PCIE_C_TXP4 L23

C1146 1
C1147 1

K24
K25
2 0.1U_0402_10V7K PCIE_C_TXN5 K21
PCIE_C_TXP5
0.1U_0402_10V7K
2
K22

CARD READER

H24
H25
J24
J23
E24
E23
F23

17 KBC_SPI_CS1#

F22
G23

+3VS
1
@ R327
1
R234
1
R262
1
R230
A

36
36
36

GPIO39
8.2K_0402_5%
2 HDD_DET#
8.2K_0402_5%
2 GPIO38
8.2K_0402_5%
2 GPIO19
8.2K_0402_5%
2

USB_OC#0
USB_OC#1
USB_OC#2
GPIO42
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
GPIO44
USB_OC#9
USB_OC#10
USB_OC#11

USB_OC#0
USB_OC#1
USB_OC#2

GPIO19
8.2K_0402_5%

@ R328

USBRBIAS

1
@ R331

GPIO38
8.2K_0402_5%
2 GPIO39
8.2K_0402_5%

Within 500 mils

R287
22.6_0402_1%

1
@ R330

SATA
GPIO

BATLOW#
PWRBTN#
LAN_RST#
RSMRST#
CK_PWRGD

P4
N4
N1
P5
P1
P2
M3
M2
P3
R1
R4
R2
AE5
AD5

PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4

DPRSLPVR

1
R243
ICH_LOW_BAT#

U4
LAN_RST

D19

PM_RSMRST#

U1

CK_PWRGD_R

T4

M_PWROK

2
0_0402_5%

CL_CLK0

E22
B18

CL_DATA0

F21
A17

CL_VREF0_ICH

C17
B17

CL_RST#

A22
E16
A15
D21

GPIO24

1
R253

PM_DPRSLPVR 8,51

LAN_RST 2
10K_0402_5%

2
0_0402_5%

CK_PWRGD

CL_RST#

37,38,43

2
0_0402_5%

HDMI_HPD#

R257
3.24K_0402_1%
1
2

31

+3VS

1
R251

2
0_0402_5%

MMBT3906H_SOT23-3
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

DMI_CLKN
DMI_CLKP

DMI_ZCOMP
DMI_IRCOMP

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

V25
V24
U24
U23

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

W23
W24
V21
V22

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

Y24
Y25
Y21
Y22

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

AB24
AB25
AA23
AA24

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

T21
T22

CLK_PCIE_ICH#
CLK_PCIE_ICH

AB21
AB22

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

@ Q20

8
8
8
8

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

8
8
8
8

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

8
8
8
8

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

8
8
8
8

PM_RSMRST#

10K_0402_5%

1
@ R332

R276 1

EC_RSMRST# 37

2
+3VS
4.7K_0402_5%
@ D7
1

2
3

BAV99_SOT23-3
B

2
1
3

CLK_PCIE_ICH# 16
CLK_PCIE_ICH 16

DMI_IRCOMP

R326

2 24.9_0402_1%

USBP0N
USBP0P
USBP1N
USBP1P
SPI_CLK
USBP2N
SPI_CS0#
USBP2P
SPI_CS1#/GPIO58/CLGPIO6 USBP3N
USBP3P
SPI_MOSI
USBP4N
SPI_MISO
USBP4P
USBP5N
OC0#/GPIO59
USBP5P
OC1#/GPIO40
USBP6N
OC2#/GPIO41
USBP6P
OC3#/GPIO42
USBP7N
OC4#/GPIO43
USBP7P
OC5#/GPIO29
USBP8N
OC6#/GPIO30
USBP8P
OC7#/GPIO31
USBP9N
OC8#/GPIO44
USBP9P
OC9#/GPIO45
USBP10N
OC10#/GPIO46
USBP10P
OC11#/GPIO47
USBP11N
USBP11P
USBRBIAS
USBRBIAS#

USB

AE2
AD1
AD3
AD4
AC2
AC3
AC5
AB4
AB2
AB1
AA3
AA2
Y1
Y2
W2
W3
V1
V2
Y5
Y4
U3
U2
V4
V5

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

36
36
36
36
36
36
38
38
33
33
33
33
33
33
29
29

@ D8 BAV99_SOT23-3

@
R333
2.2K_0402_5%

Within 500 mils

+1.5VS

USB Port0
USB Port1
USB Port2
ELC

Place closely pin AF3

WLAN

Place closely pin H1

CLK_48M_ICH

WWAN
BT
USB CAM

CLK_14M_ICH

@
R283
10_0402_5%

1 @
C273
2

@
R284
10_0402_5%

1 @
C274

4.7P_0402_50V8C

4.7P_0402_50V8C

ICH9-M SFF ES_FCBGA569

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

16

CL_DATA0 8

ACIN
1
R368

1
R273

CL_CLK0

ACIN
GPIO9

8,37,51

37

M_PWROK

2 10K_0402_5%

10K_0402_5%

PBTN_OUT#

D22

C22
A18

MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9

WWAN

PERN5
PERP5
PETN5
PETP5

C16

B23

CL_RST0#
CL_RST1#

WLAN

EXP

M1

SLP_M#

CL_VREF0
CL_VREF1

PM_PWROK
R241 1

CL_CLK0
CL_CLK1
CL_DATA0
CL_DATA1

ICH9-M SFF ES_FCBGA569

U5D
T25 PERN1
T24 PERP1
PCIE_C_TXN1
2 0.1U_0402_10V7K
R24 PETN1 LAN
2 0.1U_0402_10V7K PCIE_C_TXP1 R23
PETP1

N23
N24
M21
M22

WWAN

R275
2.2K_0402_5%

DPRSLPVR/GPIO16

CLPWROK

SPKR
MCH_SYNC#
TP3
TP8
TP9
TP10

+3VS

14,15,16,33,36 ICH_SMBCLK

34
34
34
34

LAN

10K_1206_8P4R_5%
1
2 EC_LID_OUT#
R269
10K_0402_5%
1
2 GPIO42
R270
10K_0402_5%
1
2 USB_OC#9
R334
10K_0402_5%
1
2 USB_OC#10
R336
10K_0402_5%
1
2 USB_OC#11
R335
10K_0402_5%

14,15,16,33,36 ICH_SMBDATA

SB_SPKR
MCH_ICH_SYNC#
ICH_RSVD

36 SB_SPKR
8 MCH_ICH_SYNC#
18 ICH_RSVD

USB_OC#7
USB_OC#5
USB_OC#0
USB_OC#4

S4_STATE#

D23

R3651 @

1
R256

AE16
AE18
AD18
B25
EC_SCI#
C14
D20
GPIO17
AE17
0_0402_5%
2
K3
DGPU_HOLD_RST# AC8
GPIO22
AC19
D17
E20
M4
GPIO38
AB18
GPIO39
AC18
FFS_INT2
AB19
0_0402_5% AC20
2
GPIO57
A16

E14

PWROK

DGPU_PWROK

37,38
37
37,38

R254

A19
DP_HPD_SB
CR_CPPEN

STP_PCI#/GPIO15
STP_CPU#/GPIO25

SLP_S3#
SLP_S4#
SLP_S5#

DP_HPD_SB
CR_CPPEN
PAD T52
EC_SMI#
EC_SCI#

B24

S4_STATE#/GPIO26

SMBALERT#/GPIO11

R252

32
35

VRMPWRGD

SLP_S3#
SLP_S4#
SLP_S5#

+3VS_DELAY

T50 PAD

0_0402_5%
100K_0402_5%
PAD T51

2
2

C21
L4
AD20

D18
B20
D16

2 10K_0402_5%
@

1
R250

R247 1
R248 1

VGATE

M5

PCIE_WAKE#
SERIRQ
EC_THERM#

SLP_S3#
SLP_S4#
SLP_S5#

PMSYNC#/GPIO0

2 10K_0402_5%

R364 1

CLK_14M_ICH 16
CLK_48M_ICH 16

PM_CLKRUN#

33 PCIE_WAKE#
37 SERIRQ
37 EC_THERM#
37,51

B15
A20

ICH_SUSCLK

GPIO37

DGPU_PWROK 50

1
R246

A23

R3

DGPU_PRSNT R366 1

DGPU_PRSNT

0_0402_5%
0_0402_5%

1
R245

L2

EC_LID_OUT#

SUSCLK

32

2
2

2 R260
1
453_0402_1%

R244

PM_BMBUSY#

2 0_0402_5% H_STP_PCI#_R

37 PM_CLKRUN#
2 LINKALERT#
10K_0402_5%
2 PCIE_WAKE#
10K_0402_5%
2 EC_SWI#
10K_0402_5%
2 XDP_DBRESET#
10K_0402_5%
2 S4_STATE#
10K_0402_5%
2 ICH_LOW_BAT#
10K_0402_5%
2 GPIO24
10K_0402_5%
2 ACIN
100K_0402_5%
2 ME__EC_CLK1
10K_0402_5%
2 ME__EC_DATA1
10K_0402_5%
2 GPIO9
10K_0402_5%

SUS_STAT#/LPCPD#
SYS_RESET#

HDD_DET#
R363 1
R361 1

0.1U_0402_16V4Z
C271

37 EC_LID_OUT#
R325 1

16 H_STP_PCI#
16 H_STP_CPU#

+3VALW

8 PM_BMBUSY#

RI#

T5
C25

HDD_DET#
GPIO19
GPIO36
GPIO37
CLK_14M_ICH
CLK_48M_ICH

Direct Media Interface

1
R362

4 XDP_DBRESET#
R236
@ 10K_0402_5%

C20

XDP_DBRESET#

AE19
AA18
AE20
AA20
K1
AB5

CLK14
CLK48

PCI-Express

R239

R235
@ 10K_0402_5%

EC_SWI#

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

GLAN

37 EC_SWI#

SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1

SPI

1
R238

1
R237

2 GPIO17
@ 8.2K_0402_5%
2 CR_CPPEN
10K_0402_5%
2 DGPU_PWR_EN
10K_0402_5%
2 GPIO57
@ 10K_0402_5%
2 DGPU_HOLD_RST#
8.2K_0402_5%

1
R233

1
+3VS

C18
C15
B21
E18
A24

SMB

R231

U5C
ICH_SMB_CLK
ICH_SMB_DATA
LINKALERT#
ME__EC_CLK1
ME__EC_DATA1

Clocks

SYS GPIO
Power MGT

1
R227

2 M_PWROK
0_0402_5%

1
R221

R224
2.2K_0402_5%

MISC
GPIO
Controller Link

R225

PM_PWROK
R223
2.2K_0402_5%
2

1
R222

1
R220

R271

+3VALW

2 FFS_INT2
10K_0402_5%
2 DP_HPD_SB
@ 10K_0402_5%
2 SERIRQ
10K_0402_5%
2 PM_CLKRUN#
8.2K_0402_5%
2 EC_THERM#
@ 8.2K_0402_5%
2 GPIO22
8.2K_0402_5%

Title

Compal Electronics, Inc.

ICH9(3/4)_DMI,USB,GPIO,PCIE

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

19

of

58

+RTCVCC

PCI

VCCHDA

VCCSATAPLL

VCCSUSHDA

VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]

VCCSUS1_05[1]
VCCSUS1_05[2]
VCCSUS1_5[1]
VCCSUS1_5[2]

VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]

ATX

U12
V12
W12

VCCPSUS

VCC1_5_A[07]

U15
V15

VCC1_5_A[08]
VCC1_5_A[09]

W18

+1.5VS_USBPLL

VCC1_5_A[10]

G9
H9

VCC1_5_A[11]
VCC1_5_A[12]

V11
U11

VCC1_5_A[13]
VCC1_5_A[14]

VCCPUSB

0.1U_0402_16V4Z
C303

W10

VCCSUS1_05_ICH_1
T7
H15 VCCSUS1_05_ICH_2

T60
T61

H16 VCCSUS1_5_ICH_1

T62

VCCSUS1_5_ICH_2

T63

U8
1

+3VS

T9
U9

VCCUSBPLL

VCCSUS3_3[05]
VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]

C308
0.1U_0402_16V4Z
2
1

VCC_LAN1_05_INT_ICH

VCC1_5_A[15]
VCC1_5_A[16]

G11
H11

+1.5VS

G12
H13

R304
MBK1608301YZF 0603
1
2

+1.5VS_GLAN

VCCGLAN1_5[1]
VCCGLAN1_5[2]

1
C311

10U_0603_6.3V6M

C310

+3VS

4.7U_0603_6.3V6K
C287

2 0_0603_5%

+3VS

R323 1

2 0_0603_5%

+1.5VS

R319 180_0402_1%
1
2
1
@ R324

+3VALW

2
+3VALW
0_0603_5%

+1.5VALW

If it support 3.3V audio signals

POP:R322/R324,
Depop R319/R320/R323
If it support 1.5V audio signals
POP:R319/R320/R323,
Depop R322/R324

C304
0.1U_0402_16V4Z
VCCCL1_05_ICH 1
2

H17

VCCCV1_5_ICH 1
C305

J14
K14

+3VS

2
1U_0402_6.3V6K

VCCGLANPLL

H19
J18

+1.5VS_PCIE_ICH

10U_0603_6.3V6M

@ R322 1

VCCLAN3_3[1]
VCCLAN3_3[2]

J17

K16

GLAN POWER

0.1U_0402_16V4Z
C309

MBK1608301YZF 0603

VCCCL1_5
VCCCL3_3[1]
VCCCL3_3[2]

G18

+3VALW

W8
J7
J8
K7
K8
L7
L8
M7
M8
N7
N8
P7
P8

VCCLAN1_05[1]
VCCLAN1_05[2]

R303
1

VCCCL1_05
USB CORE

MBK1608301YZF 0603

0.1U_0402_16V4Z
C307

2
0.1U_0402_16V4Z
C306

G14
G15
H14

R298
+1.5VS

+3VALW
VCCSUS3_3[04]

VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]

+3.3/1.5VCCSUS_HDA

V10

V7

+3.3/1.5VCC_HDA

4.7U_0603_6.3V6K
C302

U13
V13
W13

1U_0603_10V4Z
C299

+1.5VS

1U_0603_10V4Z
C298

C297

ARX

1U_0402_6.3V6K
C296

W17

10U_0603_6.3V6M

1
2
MBK1608301YZF 0603

+1.5VS

AD7

C290

+3VS

G8
H7
H8

R296

1U_0603_10V4Z
C285
+3VS

AE9

+1.5VS_VCCSATAPLL

+VCCP

C286

V18

C293

VCC3_3[06]
VCC3_3[07]
VCC3_3[08]

0.1U_0402_16V4Z
C294

1U_0402_6.3V6K

+VCCP

MBK1608301YZF 0603

C289

C292
VCCP_CORE

VCC_DMI

(DMI)

V16
U16

C288

2
1U_0402_6.3V6K

R292

T17
U17

AA9
V14
W14

VCC_DMI

0.1U_0402_16V4Z

C291

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]

+1.5VS

0.1U_0402_16V4Z

VCC3_3[02]

1 MBK1608301YZF 0603

0.1U_0402_16V4Z

20 mils

20 mils

VCCA3GP

ICH_V5REF_SUS

ICH_V5REF_RUN
1

VCC3_3[01]

CH751H-40_SC76

+1.5VS_DMIPLL

0.1U_0402_16V4Z

D6

100_0402_5%

V_CPU_IO[1]
V_CPU_IO[2]

R294

P19

0.1U_0402_16V4Z

D5

VCC_DMI[1]
VCC_DMI[2]

+5VALW +3VALW

CH751H-40_SC76

0.1U_0402_16V4Z
C278
1

+3VS

100_0402_5%

R290

VCCDMIPLL

R293

B4
B7
B10
B13
B16
B19
B22
D2
D24
E5
E7
E9
E11
E13
E15
E17
E19
E21
F24
G2
G5
G10
G13
G16
G19
G21
H10
H12
H18
H23
J5
J9
J10
J11
J12
J13
J15
J21
J22
J25
K2
K9
K10
K11
K12
K13
K15
K17
K23
L5
L9
L10
L16
L17
L21
L22
L25
M9
M10
M12
M13
M14
M16
M17
M23
N2
N5
N9
N10
N12
N13
N14
N16
N17
N21
N22
N25
P9
P10
P12
P13
P14
P16
P17
P23
R5
R7
R8
R9
R10
R16
R17
R19
R21
R22
R25
T2
T8
T10
T11
T12
T13
T14
T15
T16
T23

150_0402_1%
2 R320
1

0.1U_0402_16V4Z
C301

VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]

0.1U_0402_16V4Z
C300

2.2U_0402_6.3V6M

C279

10U_0603_6.3V6M
C281

C282
220U_B2_2.5VM_R35

10U_0603_6.3V6M
C280

40 mils
1

V5REF_SUS

J19
K18
K19
L18
L19
M18
M19
N18
N19
P18
R18
T18
T19
U18
U19

+1.5VS_PCIE_ICH

V5REF

L11
L12
L13
L14
L15
M11
M15
N11
N15
P11
P15
R11
R12
R13
R14
R15

1U_0603_10V4Z
C284

U7

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]

0.1U_0402_16V4Z
C295

ICH_V5REF_SUS

VCCRTC

0.1U_0402_16V4Z
C277

G7

0.01U_0402_16V7K
C283

ICH_V5REF_RUN

CORE

+5VS

U5E

U5F
G17

0.1U_0402_16V4Z

R289
1
2
BLM18PG181SN1D_0603

+1.5VS

C276

C275
0.1U_0402_16V4Z

20 mils
1

+VCCP

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]

U5
U10
W11
U14
W16
U21
U22
U25
V3
V8
V19
V23
W1
W4
W5
W7
W9
W15
W19
W21
W22
W25
Y3
Y23
AA1
AA4
AA6
AA8
AA11
AA13
AA15
AA16
AA17
AA19
AA21
AA22
AA25
AB3
AB9
AB11
AB13
AB15
AC24
AC1
AC4
AC10
AC12
AC14
AD2
AD6
AD9
AD16
AD19
AD22
AE3
AE4
AE11
AE13
AE15
V17
AE8
V9
J16

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]

A1
A25
AE1
AE25

ICH9-M SFF ES_FCBGA569

A

VCCGLAN3_3
ICH9-M SFF ES_FCBGA569

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]

Title

Compal Electronics, Inc.

ICH9(4/4)_POWER&GND

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

20

of

58

U11A

17

1
C165

0.1U_0402_16V4Z

AE9
SP_PLLVDD

AF9

C166

AD9

XTALIN
XTALOUT
XTAL_OUTBUFF
XTAL_SSIN

B1
B2
D1
D2

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

1
C702

1
C703

LCD

28
28

I2CC_SCL
I2CC_SDA

CRT

0_0402_5%
0_0402_5%

1 R415
1
R416

30 VGA_DDC_CLK
30 VGA_DDC_DATA

2LCDI2C_CLK
2LCDI2C_DAT

E2
E1
E3
E4

I2CB_SCL
I2CB_SDA

G3
G2

VGA_DDC_CLK
VGA_DDC_DATA

G1
G4

I2CH_SCL
I2CH_SDA

F6
G6

HDMI Hot-plug

GPIO2

OUT

VGA_PNL_PWM

GPIO3

OUT

ENVDD

GPIO4

OUT

VGA_BKL_EN

@
R730

GPIO5

OUT

N/A

NVVDD VID0

10K_0402_5%

GPIO6

OUT

N/A

NVVDD VID1

GPIO7

IN

GPIO8

IN

N/A

GPIO9

IN

THM_ALERT#

GPIO10

OUT

N/A

N/A

GPIO11

OUT

N/A

N/A

GPIO12

IN

N/A

N/A

GPIO13

OUT

N/A

N/A

GPIO14

OUT

N/A

GPIO15

IN

31
VGA_PNL_PWM 28
ENVDD
29

1
R217

R117

2
10K_0402_5%

10K_0402_5%
R116 1
DP_HPD

GPU_VID0
GPU_VID1

2 10K_0402_5%
DP_HPD
32

50
50

+3VS_DELAY

2 10K_0402_5%

R752 1
THM_ALERT#

HDMI_DET

ENVDD
R393 10K_0402_5%~D
DGPU_L_BKL_EN
1
2
GPU_VID0 DGPU_L_BKL_EN 28
GPU_VID1

GPIO6 GPIO5
GPU_VID1 GPU_VID0 VGA_CORE
0.8V
0
0
0
1
0.85V
1
1
0.95V

N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6
N2
N3
L3
P5
N5
N4
R4
U5
T5
T4

N11P-GS1

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

1
R410
1
R411
1
R412

MIOB_HSYNC
MIOB_VSYNC

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

MIOB_DE
MIOB_CTL3
MIOB_VREF

XTALOUT

Y3

Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6

20P_0402_50V8

OUT

GND

GND

IN

1
1

27MHZ_16PF_X7T027000BG1H-V

C163

2 20P_0402_50V8

External Spread Spectrum

OSC_OUT

R59

2 @ 22_0402_5%

XTAL_OUTBUFF

W1
W2

1
2
OSC_OUT

Y5
W3
AF1

REFOUT
XOUT

VSS

MODOUT

XIN/CLKIN

VDD

R63
10K_0402_5%

6
OSC_SPREAD

5
4

+3VS_DELAY

@ ASM3P2872AF-06OR_TSOT-23-6

2
AE1
V4

1
R732

OSC_SPREAD R112 1

@
C164
0.1U_0402_16V4Z

2 @ 22_0402_5%

XTAL_SSIN

R113
10K_0402_5%

2
10K_0402_5%

SP_PLLVDD

MIOB_CLKOUT_N

VID_PLLVDD
MIOBCAL_PD_VDDQ
MIOBCAL_PU_GND

XTAL_IN
XTAL_OUT

DACA_RED
DACA_GREEN
DACA_BLUE

XTAL_OUTBUFF
XTAL_SSIN

DACA_HSYNC
DACA_VSYNC
I2CS_SCL
I2CS_SDA

DACA_VDD
DACA_VREF
DACA_RSET

I2CC_SCL
I2CC_SDA
I2CB_SCL
I2CB_SDA
I2CA_SCL
I2CA_SDA
I2CH_SCL
I2CH_SDA

DACB_RED
DACB_GREEN
DACB_BLUE
DACB_HSYNC
DACB_VSYNC
DACB_VDD
DACB_VREF
DACB_RSET

W4

If External Spread Spectrum not stuff then stuff resistor

AA7
AA6
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

AM15
AM14
AL14

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B

AM13
AL13
AJ12
AK12
AK13

30
30
30

VGA_CRT_HSYNC
VGA_CRT_VSYNC

1
1
2
124_0402_1% R143

30
30

AK4
AL4
AJ4

C478

AM1
AM2
AG7
2 R733
1
AK6 10K_0402_5%
R734 2
AH7
1
124_0402_1%

BLM18PG181SN1D_0603
1
2
L49

150 mA

DACA_VDD
2 0.1U_0402_16V4Z
C171

1
C487

1
C490

1
C704

+3VS_DELAY

+3VS_DELAY

0.1U_0402_16V4Z
1
2
C172

@
@

30 VGA_CRT_VSYNC
30 VGA_CRT_HSYNC

N11P-GS1-A2_BGA969~D

R380
R381

1 10K_0402_5%
1 10K_0402_5%

2
2

VGA_CRT_VSYNC and VGA_CRT_HSYNC

pull up to HDMI & DISPLAY PORT AUDIO funciton

+3VS_DELAY

3
1

C162

PLLVDD

+3VS_DELAY

R386
2.2K_0402_5%

1
R405
1
R390
2
R406
1
R394
1
R395
2
R420
2
R421
2
R422
2
R423

+3VS_DELAY

R385
2.2K_0402_5%

N/A
DP Hot-plug

2
150_0402_1%
2
150_0402_1%
2
150_0402_1%

PEX_RST_N
PEX_TERMP
MIOB_CLKIN
MIOB_CLKOUT

N/A

U8

PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N

I2C
DACs

EC_SMB_CK2_PX
EC_SMB_DA2_PX

IN

XTALIN

MIOB_D0
MIOB_D1
MIOB_D2
MIOB_D3
MIOB_D4
MIOB_D5
MIOB_D6
MIOB_D7
MIOB_D8
MIOB_D9
MIOBD_10
MIOB_D11
MIOB_D12
MIOB_D13
MIOB_D14

SP_PLLVDD

1U_0402_6.3V6K

+1.05VSDGPU

4.7U_0603_6.3V6M

BLM18PG181SN1D_0603
2
1
L54

1
C167

AR16
AR17
AR13

R114@
AJ17
2
1
AJ18
200_0402_1%
R373 0_0402_5%
PEG_RST# 1
2 AM16
2
1
AG21
R115 2.49K_0402_1%

GPU_PLLVDD

0.1U_0402_16V4Z

1
C169

CLK_PCIE_VGA
CLK_PCIE_VGA#
VGA_CLKREQ#_R

PEG_RST#

36 mA
1U_0402_6.3V6K

22U_0805_6.3V6M

C492

4.7U_0603_6.3V6M

BLM18PG181SN1D_0603
2
1
L5

+1.05VSDGPU

AL17
AM17
AM18
AM19
AL19
AK19
AL20
AM20
AM21
AM22
AL22
AK22
AL23
AM23
AM24
AM25
AL25
AK25
AL26
AM26
AM27
AM28
AL28
AK28
AK29
AL29
AM29
AM30
AM31
AM32
AN32
AP32

N/A

GPIO1

USAGE

16 CLK_PCIE_VGA
16 CLK_PCIE_VGA#

PCIE_GTX_MRX_P0
PCIE_GTX_MRX_N0
PCIE_GTX_MRX_P1
PCIE_GTX_MRX_N1
PCIE_GTX_MRX_P2
PCIE_GTX_MRX_N2
PCIE_GTX_MRX_P3
PCIE_GTX_MRX_N3
PCIE_GTX_MRX_P4
PCIE_GTX_MRX_N4
PCIE_GTX_MRX_P5
PCIE_GTX_MRX_N5
PCIE_GTX_MRX_P6
PCIE_GTX_MRX_N6
PCIE_GTX_MRX_P7
PCIE_GTX_MRX_N7
PCIE_GTX_MRX_P8
PCIE_GTX_MRX_N8
PCIE_GTX_MRX_P9
PCIE_GTX_MRX_N9
PCIE_GTX_MRX_P10
PCIE_GTX_MRX_N10
PCIE_GTX_MRX_P11
PCIE_GTX_MRX_N11
PCIE_GTX_MRX_P12
PCIE_GTX_MRX_N12
PCIE_GTX_MRX_P13
PCIE_GTX_MRX_N13
PCIE_GTX_MRX_P14
PCIE_GTX_MRX_N14
PCIE_GTX_MRX_P15
PCIE_GTX_MRX_N15

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

IN

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

GPIO0

ACTIVE

4.7U_0603_6.3V6M

C1148
C1149
C1150
C1151
C1152
C1153
C1154
C1155
C1156
C1157
C1158
C1159
C1160
C1161
C1162
C1163
C1164
C1165
C1166
C1167
C1168
C1169
C1170
C1171
C1172
C1173
C1174
C1175
C1176
C1177
C1178
C1179

I/O

4700P_0402_25V7K

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

K1
K2
K3
H3
H2
H1
H4
H5
H6
J7
K4
K5
H7
J4
J6
L1
L2
L4
M4
L7
L5
K6
L6
M6

GPIO

R404
10K_0402_5%~D
1
2

470P_0402_50V7K

PCIE_GTX_C_MRX_P[0..15]

10 PCIE_GTX_C_MRX_P[0..15]

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23

GPIO

PCIE_GTX_C_MRX_N[0..15]

10 PCIE_GTX_C_MRX_N[0..15]

Part 1 of 7

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

PCI EXPRESS
DVO

PCIE_MTX_C_GRX_P[0..15]

10 PCIE_MTX_C_GRX_P[0..15]

AP17
AN17
AN19
AP19
AR19
AR20
AP20
AN20
AN22
AP22
AR22
AR23
AP23
AN23
AN25
AP25
AR25
AR26
AP26
AN26
AN28
AP28
AR28
AR29
AP29
AN29
AN31
AP31
AR31
AR32
AR34
AP34

CLK

PCIE_MTX_C_GRX_N[0..15]

10 PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

DGPU_L_BKL_EN
1
10K_0402_5%

2
R391

1U_0402_6.3V6K

Q21A
2N7002DW-T/R7_SOT363-6
4

EC_SMB_DA2_PX

EC_SMB_CK2 4,37

EC_SMB_CK2_PX

EC_SMB_DA2 4,37

+3VS_DELAY

+3VS_DELAY

Q21B
2N7002DW-T/R7_SOT363-6
A

VGA Thermal Sensor ADM1032ARMZ

I2CC_SCL
2
2.2K_0402_5%
I2CC_SDA
2
2.2K_0402_5%
VGA_CLKREQ#_R
1
@ 10K_0402_5%
VGA_DDC_CLK
2
4.7K_0402_5%
VGA_DDC_DATA
2
4.7K_0402_5%
I2CB_SCL
1
10K_0402_5%
I2CB_SDA
1
10K_0402_5%
I2CH_SCL
1
10K_0402_5%
I2CH_SDA
1
10K_0402_5%

Closed to GPU

C1180
0.1U_0402_16V4Z

U12

C1181
1
2

2200P_0402_50V7K

22 GPU_THERMAL_D-

+3VS_DELAY

VDD

SCLK

D+

SDATA

D-

ALERT#

THERM#

GND

EC_SMB_CK2_PX

EC_SMB_DA2_PX

THM_ALERT#
+3VS_DELAY

5
1
R387

ADM1032ARMZ-2REEL_MSOP8

2
4.7K_0402_5%

2
G

1
R388

VGA_CLKREQ#_R

2
4.7K_0402_5%

1
22 GPU_THERMAL_D+

R389
2.2K_0402_5%

16 VGA_CLKREQ#

+3VS_DELAY

2N7002_SOT23-3
Q58

Compal Secret Data

Security Classification
Issued Date

2009/07/25

Deciphered Date

2010/07/25

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

N11P-GS1(1/5)PCIE/STRAPS/THERM
Size

Document Number

Rev
1.0

LA-5811P
Date:

Tuesday, December 29, 2009

1

Sheet

21

of

58

U11D

Straps

Part 4 of 7

+3VS_DELAY

1
R397

HDMI_SCL
2
4.7K_0402_5%

1
R399

HDMI_SDA
2
4.7K_0402_5%

IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

AM7
AM6
AL5
AM5
AM3
AM4
AP1
AR2

31 VGA_DVI_TXD2+
31 VGA_DVI_TXD231 VGA_DVI_TXD1+
31 VGA_DVI_TXD131 VGA_DVI_TXD0+
31 VGA_DVI_TXD031 VGA_DVI_TXC+
31 VGA_DVI_TXC-

HDMI

AP13
AN13
AN8
AP8
AP10
AN10
AR11
AR10
AN11
AP11

AR8
AR7
AP7
AN7
AN5
AP5
AR5
AR4

32
32
32
32
32
32
32
32

DP

AH6
AH5
AH4
AG4
AF4
AF5
AE6
AE5

DISP_A0P_VGA
DISP_A0N_VGA
DISP_A1P_VGA
DISP_A1N_VGA
DISP_A2P_VGA
DISP_A2N_VGA
DISP_A3P_VGA
DISP_A3N_VGA

AL2
AL3
AJ3
AJ2
AJ1
AH1
AH2
AH3

HDMI

31 VGA_DVI_SCLK
31 VGA_DVI_SDATA

0_0402_5%
0_0402_5%

2
2

1
1

R431
R432

HDMI_SCL
HDMI_SDA

AP2
AN3
AP4
AN4

DP

32 DP_DDC_CLK
32 DP_DDC_DATA

DP_DDC_CLK
DP_DDC_DATA

AE4
AD4
AF3
AF2
A7
B7
C7
D6
D7

IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC

LVDS
D

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N

LVDS/TMDS

28 VGA_TXCLK+
28 VGA_TXCLK28 VGA_TXOUT0+
28 VGA_TXOUT028 VGA_TXOUT1+
28 VGA_TXOUT128 VGA_TXOUT2+
28 VGA_TXOUT2-

AM11
AM12
AM8
AL8
AM10
AM9
AK10
AL10
AK11
AL11

AB5
STRAP0
STRAP1
STRAP2

W5
W7
V7

MULTI LEVEL STRAPS

STRAP0
STRAP1
STRAP2
ROM_SI
ROM_SO
ROM_SCLK

+3VS_DELAY

@
1
2
R742 5.1K_0402_5%

1
2
R741 45.3K_0402_1%

strap0

@
1
2
R743 10K_0402_1%

1
2
R744 35.7K_0402_1%

strap1

@
1
2
R745 10K_0402_1%

1
2
R746 45.3K_0402_1%

strap2
ROM_SI

R207 15K_0402_5%

@
1
2
R202 5.1K_0402_5%

1
2
R208 10K_0402_1%

@
1
2
R203 5.1K_0402_5%

ROM_SO
ROM_SCLK

R204 15K_0402_5%

@
R205 15K_0402_5%

strap1

strap2

ROM_SI

64MX16
Samsung

strap0
H
45K

H
35K

H
30K

L
20K

ROM_SO
L
10K

L
15K

64MX16
Hynix

H
45K

H
35K

H
30K

L
15K

L
10K

L
15K

ROM_SCLK

SSI --> Hynix

PT --> Hynix
ST --> Hynix(main),Samsung(second)
Hynix:SA0000032400
Samsung:SA0000035700

VDD_SENSE_0
VDD_SENSE_1
VDD_SENSE_2

NC
NC
NC
NC
NC
NC
NC
NC

GND_SENSE_0
GND_SENSE_1
GND_SENSE_2

R735 1
R144 1
R736 1

D35
P7
AD20

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

R190 1
R737 1
R152 1

AD19
E35
R7

+NVVDD_SENSE 50

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N

TEST

IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N

TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

NC
NC
DBG_DATA0
DBG_DATA1
DBG_DATA2
DBG_DATA3
DBG_DATA4

1 R739
2
10K_0402_5%

AP35
AP14
AN14
AN16
AR14
AP16

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST

PAD
PAD
PAD
PAD
PAD

T55
T41
T40
T49
T45

@
@
@
@
@

2 R738
1
10K_0402_5%

DBG

SERIAL
ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK

GENERAL
A4

A2
C5
D5
E5
E7
F4
G5
G11
G12
G14
G15
G27
G28
G24
G25
H32
J18
J19
J25
J26
L29
M7
M29
P6
P29
R29
U7
V6
Y4
AA4
AB4
AB7
AC5
AD6
AD29
AE29
AF6
AG6
AG20
AG29
AH29
AJ5
AK15
AL7

NC
BUFRST_N
MULTI_STRAP_REF0_GND
NC
MULTI_STRAP_REF1_GND
STRAP0
STRAP1
STRAP2

THERMDP
THERMDN

R740
C3
D3
C4
D4

ROM_CS#
10K_0402_5%1
ROM_SI
ROM_SO
ROM_SCLK

2 @

+3VS_DELAY

A5
N9
M9
B5
B4

R199
2
1
40.2K_0402_1%
2
1
40.2K_0402_1%
R200

GPU_THERMAL_D+ 21
GPU_THERMAL_D- 21

N11P-GS1-A2_BGA969~D
A

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

N11P-GS1(2/5) IO

Size

Document Number

Rev
1.0

LA-5811P
Date:

Tuesday, December 29, 2009

Sheet
1

22

of

58

U11E
Part 5 of 7

1K_0402_1% 2
R748

IFPAB_PLLVDD
AK9
IFPAB_RSET AJ11
1
IFPA_IOVDD
IFPB_IOVDD

AG9
AG10

220 mA

IFPC_PLLVDD
1 IFPC_RSET
R750 1K_0402_1%
IFPC_IOVDD

AJ9
AK7

285 mA

+1.8VSDGPU

150mA

1K_0402_1%

C177
2

IFPB_IOVDD

IFPC_IOVDD
C206

220 mA

1K_0402_1%

IFPC_PLLVDD
IFPE_RSET
1 R216
IFPC_IOVDD

285 mA

IFPC_IOVDD
IFPD_PLLVDD
IFPD_RSET

AK8

IFPD_IOVDD

AJ6
AL1

IFPEF_PLLVDD
IFPEF_RSET

AE7

IFPE_IOVDD

AD7

P9
R9
T9
U9

BLM18PG181SN1D_0603

1
C232

NC

C209

1
C312

C261

1
C215
2

1
C237
2

1
C314

C315

+3VS_DELAY

R214
0_0603_5%

+3VS_DELAY

1
C268
2

1
C173
2

1
C176
2

1
C174
2

1
C210
2

1
C230
2

1
C242
2

1
C211
2

1
C240
2

1
C239
2

1
C264
2

Q11
SI7121DN-T1-GE3_POWERPAK8-5

+3VS
1
2
3

+1.8VSDGPU

1
C267
2

R213

19,40,47,50
C168
0.22U_0603_10V7K

1
C183
2

0.022U_0402_16V7K

1
C180

+3VS_DELAY

3VS_Dgate

DGPU_PWR_EN

2
1K_0402_5%
1

C207
0.1U_0402_16V4Z~D

AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
AD24
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M12
M14
M16
M18
M20
M22
M24
P11
P13
P15
P17
P19

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55

Part 7 of 7

VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85
VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98
VDD_99
VDD_100
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110

P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24

N11P-GS1-A2_BGA969~D

Q10

Q12
SSM3K7002FU_SC70-3

1 1

D
D

2
G

2
G

3VS_Dgate

S
3

2
G
Q34
2N7002_SOT23

C494
2

R210
470_0603_5%
1

2
G
1

DGPU_PWR_EN#

1
R211

100K_0402_5%
R118
68K_0402_1%
2

1
C181

1380mA

SSM3K7002FU_SC70-3

Compal Secret Data

Security Classification

1
C182

0.022U_0402_16V7K

+3VS_DELAY

300mA

1
C263

1U_0603_10V4Z

C179

Q35
AO3414_SOT23-3
D

40 DGPU_PWR_EN#

+1.8V

1
C262

4.7U_0805_10V4Z

C499

22U_0805_6.3V6M

10U_0805_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6M

+1.05VSDGPU

0.22U_0402_10V4Z

22U_0805_6.3V6M

C498

C497

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C496

C484

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C483

0.1U_0402_16V4Z

1U_0402_6.3V6K

22U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_6.3V6M

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

1
C243

0.22U_0402_10V4Z

C204
2

C489

0.047U_0402_16V7K

C252

0.047U_0402_16V7K

C194
2

0.047U_0402_16V7K

120mA

IFPC_IOVDD
1

C488

0.1U_0402_16V4Z

C486

C187
2

+1.8V to +1.8VSDGPU Transfer

+5VS

570 mA

BLM18PG181SN1D_0603
1

L50

4.7U_0603_6.3V6M

C178

1U_0402_6.3V6K

0.1U_0402_16V4Z

C205
2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C186
2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C185
2

0.1U_0402_16V4Z

+1.05VSDGPU

1
L52
LLQ1608-FR10G_0603

C253

440 mA
0.1U_0402_16V4Z

4.7U_0603_6.3V6M

C491

IFPC_PLLVDD

1U_0402_6.3V6K

C255

L4

U11G

C495

+VGA_CORE

AA9
AB9
W9
Y9

follow the DS04644

+3VS_DELAY

+1.05VSDGPU

+VGA_CORE
MIOB_VDDQ_0
MIOB_VDDQ_1
MIOB_VDDQ_2
MIOB_VDDQ_3

C241

C250
2

+3VS_DELAY

N11P-GS1-A2_BGA969~D

0.022U_0402_16V7K

C184
2

+3VS_DELAY

C493

0.022U_0402_16V7K

NC
NC
NC
NC

J10
J11
J12
J13
J9

470P_0402_50V7K

0.1U_0402_16V4Z

150mA

AJ8
AC6
AB6

C485
2

0.01U_0402_25V7K

C208
2

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4

IFPC_PLLVDD
IFPC_RSET

PEX_SVDD_3V3

2
1

0.01U_0402_25V7K

IFPC_PLLVDD
IFPD_RSET
1 R749

IFPA_IOVDD
IFPB_IOVDD

AG19
F7

0.01U_0402_25V7K

4.7U_0603_6.3V6M

L7
BLM18PG181SN1D_0603

IFPA_IOVDD
0.1U_0402_16V4Z

1U_0402_6.3V6K

PEX_SVDD_3V3_0
PEX_SVDD_3V3_1

PEX_PLLDVDD

PEX_SVDD_3V3

IFPAB_PLLVDD
IFPAB_RSET

1.920 Amps

POWER

C445
@

C245
2

4.7U_0603_6.3V6M

C254

1U_0603_10V4Z

220 mA

PEX_PLLDVDD

C248
2

4700P_0402_25V7K

C444
2

AG14

0.1U_0402_16V4Z

C446
2

PEX_PLLVDD

C251

4700P_0402_25V7K

1U_0402_6.3V6K

PEX_IOVDD

0.1U_0402_16V4Z

IFPAB_PLLVDD

AK16
AK17
AK21
AK24
AK27

C272
2

600 mA

0.1U_0402_16V4Z

follow the DS04644

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4

C244
2

PEX_IOVDD

0.1U_0402_16V4Z

0.01U_0402_25V7K

220mA

C197

0.047U_0402_16V7K

C195

0.1U_0402_16V4Z

BLM18PG181SN1D_0603
1
L51
4.7U_0603_6.3V6M

0.1U_0402_16V4Z

+1.05VSDGPU

C193

0.01U_0402_16V7K

FBVDDQ
1

C459
2

1U_0402_6.3V6K

C249
2

0.1U_0402_16V4Z

C191

0.047U_0402_16V7K

C192

0.047U_0402_16V7K

C188

C189

0.01U_0402_16V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

FBVDDQ

+1.05VSDGPU

PEX_IOVDDQ

0.01U_0402_25V7K

AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24
AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16

1U_0402_6.3V6K

C200

C201

PEX_IOVDDQ

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18
PEX_IOVDDQ_19
PEX_IOVDDQ_20
PEX_IOVDDQ_21
PEX_IOVDDQ_22
PEX_IOVDDQ_23
PEX_IOVDDQ_24

0.1U_0402_16V4Z

0.01U_0402_16V7K

C202

C203

0.01U_0402_16V7K

0.1U_0402_16V4Z

C199

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37

4.7U_0603_6.3V6M

J23
J24
J29
AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27
AJ28
B18
E21
G17
G18
G22
G8
G9
H29
J14
J15
J16
J17
J20
J21
J22
N27
P27
R27
T27
U27
U29
V27
V29
V34
W27
Y27

0.01U_0402_25V7K

FBVDDQ
FBVDDQ

POWER

+1.5VSDGPU

Issued Date

2009/07/25

Deciphered Date

2010/07/25

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.

N11P-GS1(3/5) POWER

Size

Document Number

Rev
1.0

LA-5811P
Date:

Wednesday, December 30, 2009

1

Sheet

23

of

58

U11F

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96

Part 6 of 7

GND

B3
B6
B9
B12
B15
B21
B24
B27
B30
B33
C2
C34
E6
E9
E12
E15
E18
E24
E27
E30
F2
F31
F34
F5
J2
J5
J31
J34
K9
L9
M2
M5
M11
M13
M15
M17
M19
M21
M23
M25
M31
M34
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P12
P14
P16
P18
P20
P22
P24
R2
R5
R31
R34
T11
T13
T15
T17
T19
T21
T23
T25
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
V2
V5
V9
V12
V14
V16

GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192

V18
V20
V22
V24
V31
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
AA2
AA5
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD2
AD5
AD11
AD13
AD15
AD17
AD21
AD23
AD25
AD31
AD34
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG5
AG31
AG34
AK2
AK5
AK14
AK31
AK34
AL6
AL9
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AN2
AN34
AP3
AP6
AP9
AP12
AP15
AP18
AP21
AP24
AP27
AP30
AP33

N11P-GS1-A2_BGA969~D
A

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

N11P-GS1(4/5) GND

Size

Document Number

Rev
1.0

LA-5811P
Date:

Tuesday, December 29, 2009

Sheet
1

24

of

58

U11C

MDA[0..63]

Part 2 of 7
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

L32
N33
L33
N34
N35
P35
P33
P34
K35
K33
K34
H33
G34
G33
E34
E33
G31
F30
G30
G32
K30
K32
H30
K31
L31
L30
M32
N30
M30
P31
R32
R30
AG30
AG32
AH31
AF31
AF30
AE30
AC32
AD30
AN33
AL31
AM33
AL33
AK30
AK32
AJ30
AH30
AH33
AH35
AH34
AH32
AJ33
AL35
AM34
AM35
AF33
AE32
AF34
AE35
AE34
AE33
AB32
AC35

FB_PLLAVDD

AG27
AF27

FB_VREF
+1.5VSDGPU

J27

2
1
T30
R226 10K_0402_5%@

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

V32
W31
U31
Y32
AB35
AB34
W35
W33
W30
T34
T35
AB31
Y30
Y34
W32
AA30
AA32
Y33
U32
Y31
U34
Y35
W34
V30
U35
U30
U33
AB30
AB33
T33
W29

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MAA15
MAA16
MAA17
MAA18
MAA19
MAA20
MAA21
MAA22
MAA23
MAA24
MAA25
MAA26
MAA27
MAA28
MAA29
MAA30

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

P32
H34
J30
P30
AF32
AL32
AL34
AF35

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

L35
G35
H31
N32
AD32
AJ31
AJ35
AC34

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

L34
H35
J32
N31
AE31
AJ32
AJ34
AC33

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

DQMA#[0..7]

MEMORY INTERFACE
A

26

MDA[0..63]

MAA[0..30]

DQMA#[0..7]

QSA#[0..7]

QSA[0..7]
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

26

27

MDB[0..63]

MDB[0..63]

26

QSA#[0..7]

26

QSA[0..7]

26

2
R249
2
R242
2
R255

+1.5VSDGPU

FB_DLLAVDD
FB_PLLAVDD

FBA_CLK0
FBA_CLK0_N

FB_VREF
FBA_CLK1
FBA_CLK1_N

FBA_DEBUG

CLKA0
CLKA0#

T32
T31

CLKA0
CLKA0#

B13
D13
A13
A14
C16
B16
A17
D16
C13
B11
C11
A11
C10
C8
B8
A8
E8
F8
F10
F9
F12
D8
D11
E11
D12
E13
F13
F14
F15
E16
F16
F17
D29
F27
F28
E28
D26
F25
D24
E25
E32
F32
D33
E31
C33
F29
D30
E29
B29
C31
C29
B31
C32
B32
B35
B34
A29
B28
A28
C28
C26
D25
B25
A25

1
K27
40.2_0402_1%
1
L27
40.2_0402_1%
1
M27
40.2_0402_1%

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

C17
B19
D18
F21
A23
D21
B23
E20
G21
F20
F19
F23
A22
C22
B17
F24
C25
E22
C20
B22
A19
D22
D20
E19
D19
F18
C19
F22
C23
B20
A20

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAB15
MAB16
MAB17
MAB18
MAB19
MAB20
MAB21
MAB22
MAB23
MAB24
MAB25
MAB26
MAB27
MAB28
MAB29
MAB30

NC
NC
NC
NC
NC
NC
NC
NC

A16
D10
F11
D15
D27
D34
A34
D28

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

NC
NC
NC
NC
NC
NC
NC
NC

B14
B10
D9
E14
F26
D31
A31
A26

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

C14
A10
E10
D14
E26
D32
A32
B26

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

CLKA1
CLKA1#

MAB[0..30]

26
26

DQMB#[0..7]

QSB[0..7]

FBCAL_PD_VDDQ

NC
NC

FBCAL_PU_GND
NC
NC

FBCAL_TERM_GND

E17
D17

CLKB0
CLKB0#

D23
E23

CLKB1
CLKB1#

G19

2
R240

27

QSB#[0..7]

NC
NC
NC
NC
NC
NC
NC
NC

27

DQMB#[0..7]

NC

CLKA1
CLKA1#

AC31
AC30

26
26

MAB[0..30]
Part 3 of 7

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

MEMORY INTERFACE C

MAA[0..30]

U11B

CLKB0
CLKB0#

27
27

CLKB1
CLKB1#

27
27

1
10K_0402_5%

QSB#[0..7]

27

QSB[0..7]

27

+1.5VSDGPU

R758
N11P-GS1-A2_BGA969~D
@

N11P-GS1-A2_BGA969~D

60.4_0402_1%

1
+1.05VSDGPU
L8
BLM18PG181SN1D_0603

+1.5VSDGPU
1

C259

Place Components Close to BGA

2
R229 @
1K_0402_1%

Rt

C258

4.7U_0603_6.3V6M

C260
0.01U_0402_25V7K

C257

1U_0402_6.3V6K

0.1U_0402_16V4Z

FB_PLLAVDD

R228 @
1K_0402_1%

Rb

0.1U_0402_16V4Z

FB_VREF
1

Memory/PKG

FBVDDQ

DDR3 (11P)

+1.5VS

FBCAL_PU_GND
40.2 ohm

FBCAL_PD_VDDQ

FBCAL_TERM_GND

40.2 ohm

40.2 ohm

C256
@

Must be used 1% resister for driver calibration

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

N11P-GS1(5/5) MEMORY

Size

Document Number

Rev
1.0

LA-5811P
Date:

Tuesday, December 29, 2009

Sheet
1

25

of

58

A1
A8
C1
C9
D2
E9
F1
H2
H9

MAA30
MAA29
MAA1
MAA10
MAA11

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

F3
C7

DQSL
DQSU

QSA0
QSA2

F3
C7

DQSL
DQSU

DQMA#3
DQMA#1

E7
D3

DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#0
DQMA#2

E7
D3

DML
DMU

QSA#3
QSA#1

G3
B7

QSA#0
QSA#2

G3
B7

MAA15

T2

RESET

ZQ0

L8

ZQ/ZQ0

MAA15

T2

RESET

ZQ1

L8

ZQ/ZQ0

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

DQSL
DQSU

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

R756
243_0402_1%~OK

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

F3
C7

DQSL
DQSU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#7
DQMA#4

E7
D3

DML
DMU

QSA#7
QSA#4

G3
B7

MAA15

T2

RESET

ZQ2

L8

ZQ/ZQ0

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

1
2

1
2

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSA5
QSA6

F3
C7

DQSL
DQSU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#5
DQMA#6

E7
D3

DML
DMU

QSA#5
QSA#6

G3
B7

MAA15

T2

RESET

ZQ3

L8

ZQ/ZQ0

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

R616
243_0402_1%~OK

+1.5VSDGPU

MEM_VREF2
1
C159
2

MEM_VREF3
1
C412
2

+1.5VSDGPU

C800
1U_0402_6.3V6K~D

2009/07/25

B1
B9
D1
D8
E2
E8
F9
G1
G9

C799
1U_0402_6.3V6K~D

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

R400
1K_0402_1%

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

C798
1U_0402_6.3V6K~D

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

C797
1U_0402_6.3V6K~D

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

+1.5VSDGPU

C796
1U_0402_6.3V6K~D

C811
10U_0603_6.3V6M~D

A1
A8
C1
C9
D2
E9
F1
H2
H9

DQSL
DQSU

Compal Secret Data

Security Classification
Issued Date

C810
10U_0603_6.3V6M~D

C809
10U_0603_6.3V6M~D

C808
10U_0603_6.3V6M~D

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CK
CK
CKE/CKE0

+1.5VSDGPU

C807
10U_0603_6.3V6M~D

B2
D9
G7
K2
K8
N1
N9
R1
R9

C795
1U_0402_6.3V6K~D

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

C794
1U_0402_6.3V6K~D

MDA48
MDA53
MDA50
MDA54
MDA51
MDA55
MDA49
MDA52

+1.5VSDGPU

C792
1U_0402_6.3V6K~D

D7
C3
C8
C2
A7
A2
B8
A3

R402
1K_0402_1%

C790
1U_0402_6.3V6K~D

MDA40
MDA41
MDA43
MDA44
MDA45
MDA47
MDA42
MDA46

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96

C789
1U_0402_6.3V6K~D

C788
1U_0402_6.3V6K~D

C787
1U_0402_6.3V6K~D

C786
1U_0402_6.3V6K~D

C784
1U_0402_6.3V6K~D

C783
1U_0402_6.3V6K~D

C782
1U_0402_6.3V6K~D

MAA28
MAA8
MAA1
MAA10
MAA11

J1
L1
J9
L9

E3
F7
F2
F8
H3
H8
G2
H7

+1.5VSDGPU

A1
A8
C1
C9
D2
E9
F1
H2
H9

+1.5VSDGPU

C781
1U_0402_6.3V6K~D

DQSL
DQSU

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

+1.5VSDGPU

R12
1K_0402_1%

C806
10U_0603_6.3V6M~D

CLKA1#

CLKA1#

C805
10U_0603_6.3V6M~D

C804
10U_0603_6.3V6M~D

C803
10U_0603_6.3V6M~D

25

J7
K7
K9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

+1.5VSDGPU

C802
10U_0603_6.3V6M~D

R407
243_0402_1%

CLKA1
CLKA1#
MAA7

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96

C780
1U_0402_6.3V6K~D

C779
1U_0402_6.3V6K~D

M2
N8
M3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

B2
D9
G7
K2
K8
N1
N9
R1
R9

MEM_VREF1
1
C158

C778
1U_0402_6.3V6K~D

MAA12
MAA3
MAA27

VREFCA
VREFDQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VRAM P/N :
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )

+1.5VSDGPU

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

0.1U_0402_10V6K~D

QSA7
QSA4

R572
243_0402_1%~OK

MDA35
MDA39
MDA32
MDA36
MDA33
MDA38
MDA34
MDA37

M8
H1

MAA19
MAA25
MAA4
MAA6
MAA5
MAA13
MAA21
MAA16
MAA23
MAA20
MAA17
MAA9
MAA14
MAA26

R18
1K_0402_1%

R11
1K_0402_1%

C776
1U_0402_6.3V6K~D

C775
1U_0402_6.3V6K~D

C774
1U_0402_6.3V6K~D

C773
1U_0402_6.3V6K~D

C772
1U_0402_6.3V6K~D

CLKA1

C771
1U_0402_6.3V6K~D

1
CLKA0#

CLKA1

ODT/ODT0
CS/CS0
RAS
CAS
WE

CK
CK
CKE/CKE0

1
C770
1U_0402_6.3V6K~D

25

K1
L2
J3
K3
L3

J1
L1
J9
L9

D7
C3
C8
C2
A7
A2
B8
A3

MEM_VREF3

C791
0.1U_0402_10V6K~D 1U_0402_6.3V6K~D

+1.5VSDGPU

CLKA0#

MAA28
MAA8
MAA1
MAA10
MAA11

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

MEM_VREF0
1
C407

R403
243_0402_1%

25

A1
A8
C1
C9
D2
E9
F1
H2
H9

+1.5VSDGPU

MDA57
MDA63
MDA61
MDA58
MDA56
MDA60
MDA62
MDA59

+1.5VSDGPU

BA0
BA1
BA2

R17
1K_0402_1%

CLKA0

CLKA0

J7
K7
K9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

+1.5VSDGPU

R401
1K_0402_1%

R398
1K_0402_1%
25

CLKA1
CLKA1#
MAA7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

M2
N8
M3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2
2
2
2
2

MAA12
MAA3
MAA27

+1.5VSDGPU

VREFCA
VREFDQ

B2
D9
G7
K2
K8
N1
N9
R1
R9

CK
CK
CKE/CKE0

1
1
1
1
1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

R19
R106
R25
R20
R21

MDA20
MDA22
MDA23
MDA21
MDA17
MDA19
MDA18
MDA16

M8
H1

MAA19
MAA25
MAA4
MAA6
MAA5
MAA13
MAA21
MAA16
MAA23
MAA20
MAA17
MAA9
MAA14
MAA26

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96

+1.5VSDGPU
MAA7
MAA18
MAA28
MAA30
MAA15

J1
L1
J9
L9

D7
C3
C8
C2
A7
A2
B8
A3

MEM_VREF2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

+1.5VSDGPU

MDA4
MDA1
MDA5
MDA0
MDA7
MDA3
MDA6
MDA2

QSA3
QSA1

R761
243_0402_1%~OK

J7
K7
K9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

ODT/ODT0
CS/CS0
RAS
CAS
WE

J1
L1
J9
L9

CLKA0
CLKA0#
MAA18

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B2
D9
G7
K2
K8
N1
N9
R1
R9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

DQMA[7..0]

M2
N8
M3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQMA#[7..0]

MAA12
MAA3
MAA27

+1.5VSDGPU

VREFCA
VREFDQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

MAA30
MAA29
MAA1
MAA10
MAA11

QSA#[7..0]

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

25

QSA[7..0]

MDA8
MDA9
MDA10
MDA11
MDA14
MDA13
MDA15
MDA12

M8
H1

MAA19
MAA25
MAA22
MAA24
MAA0
MAA2
MAA21
MAA16
MAA23
MAA20
MAA17
MAA9
MAA14
MAA26

QSA#[7..0]

MAA[30..0]

D7
C3
C8
C2
A7
A2
B8
A3

MEM_VREF1

25

J7
K7
K9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDA24
MDA27
MDA25
MDA29
MDA26
MDA31
MDA28
MDA30

QSA[7..0]

CLKA0
CLKA0#
MAA18

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

U53

MAA[30..0]

25

M2
N8
M3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

MDA[63..0]

MDA[63..0]

25

MAA12
MAA3
MAA27

VREFCA
VREFDQ

25

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

MAA19
MAA25
MAA22
MAA24
MAA0
MAA2
MAA21
MAA16
MAA23
MAA20
MAA17
MAA9
MAA14
MAA26

U52

MEM_VREF0 M8
H1

U36

U54

Title

Compal Electronics, Inc.

VRAM DDR3 / Channel A

Size

Document Number

Rev
1.0

LA-5811P
Date:

Tuesday, December 29, 2009

Sheet
1

26

of

58

U56
MEM_VREF4 M8
H1

MAB12
MAB3
MAB27

M2
N8
M3

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

CLKB0
CLKB0#
MAB18

J7
K7
K9

MAB12
MAB3
MAB27

M2
N8
M3

BA0
BA1
BA2

CLKB0
CLKB0#
MAB18

J7
K7
K9

+1.5VSDGPU

CK
CK
CKE/CKE0

E7
D3

QSB#3
QSB#1

G3
B7

MAB15

T2

ZQ4

L8

J1
L1
J9
L9

DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

MAB30
MAB29
MAB1
MAB10
MAB11

K1
L2
J3
K3
L3

QSB0
QSB2

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMB#0
DQMB#2

E7
D3

QSB#0
QSB#2

G3
B7

MAB15

T2

ZQ5

L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R771
243_0402_1%~OK

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB35
MDB39
MDB32
MDB36
MDB33
MDB38
MDB34
MDB37

M2
N8
M3

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

CLKB1
CLKB1#
MAB7

J7
K7
K9

CK
CK
CKE/CKE0

+1.5VSDGPU

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

MAB12
MAB3
MAB27

M2
N8
M3

BA0
BA1
BA2

CLKB1
CLKB1#
MAB7

J7
K7
K9

CK
CK
CKE/CKE0

A1
A8
C1
C9
D2
E9
F1
H2
H9

MAB28
MAB8
MAB1
MAB10
MAB11

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

QSB5
QSB6

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMB#5
DQMB#6

E7
D3

QSB#5
QSB#6

G3
B7

MAB15

T2

ZQ7

L8

+1.5VSDGPU

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

A1
A8
C1
C9
D2
E9
F1
H2
H9

MAB28
MAB8
MAB1
MAB10
MAB11

K1
L2
J3
K3
L3

QSB7
QSB4

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMB#7
DQMB#4

E7
D3

QSB#7
QSB#4

G3
B7

MAB15

T2

ZQ6

L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

J1
L1
J9
L9

R767
243_0402_1%~OK

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

+1.5VSDGPU

B1
B9
D1
D8
E2
E8
F9
G1
G9

R787
243_0402_1%~OK

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB40
MDB41
MDB43
MDB44
MDB45
MDB47
MDB42
MDB46

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB51
MDB53
MDB48
MDB54
MDB49
MDB55
MDB50
MDB52

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VSDGPU

+1.5VSDGPU

VRAM P/N :
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )

+1.5VSDGPU

2
1

1
2

2
+1.5VSDGPU

R109
1K_0402_1%

MEM_VREF6
1
C161
2

C852
1U_0402_6.3V6K~D

MEM_VREF7
1
C413

C851
1U_0402_6.3V6K~D

C850
1U_0402_6.3V6K~D

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

C849
1U_0402_6.3V6K~D

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

C848
1U_0402_6.3V6K~D

ZQ/ZQ0

C847
1U_0402_6.3V6K~D

C846
1U_0402_6.3V6K~D

C844
1U_0402_6.3V6K~D

C843
1U_0402_6.3V6K~D

2009/07/25

RESET

C863
10U_0603_6.3V6M~D

C862
10U_0603_6.3V6M~D

Compal Electronics, Inc.

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

R414
1K_0402_1%

Compal Secret Data

Security Classification
Issued Date

C861
10U_0603_6.3V6M~D

C860
10U_0603_6.3V6M~D

C859
10U_0603_6.3V6M~D

C858
10U_0603_6.3V6M~D

C857
10U_0603_6.3V6M~D

C856
10U_0603_6.3V6M~D

C842
1U_0402_6.3V6K~D

+1.5VSDGPU

C841
1U_0402_6.3V6K~D

C840
1U_0402_6.3V6K~D

C839
1U_0402_6.3V6K~D

C838
1U_0402_6.3V6K~D

C836
1U_0402_6.3V6K~D

C835
1U_0402_6.3V6K~D

C834
1U_0402_6.3V6K~D

C833
1U_0402_6.3V6K~D

C832
1U_0402_6.3V6K~D

C831
1U_0402_6.3V6K~D

C830
1U_0402_6.3V6K~D

C828
1U_0402_6.3V6K~D

C827
1U_0402_6.3V6K~D

C826
1U_0402_6.3V6K~D

C825
1U_0402_6.3V6K~D

C824
1U_0402_6.3V6K~D

CLKB1#

C855
10U_0603_6.3V6M~D

CLKB1#

DQSL
DQSU

+1.5VSDGPU

+1.5VSDGPU

C854
10U_0603_6.3V6M~D

R418
243_0402_1%

C823
1U_0402_6.3V6K~D

CLKB1

C822
1U_0402_6.3V6K~D

CLKB0#

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

R413
1K_0402_1%

+1.5VSDGPU

DML
DMU

0.1U_0402_10V6K~D

MEM_VREF5
1

DQSL
DQSU

+1.5VSDGPU

R108
1K_0402_1%

C160

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96

0.1U_0402_10V6K~D

0.1U_0402_10V6K~D

R107
1K_0402_1%

J1
L1
J9
L9

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96

0.1U_0402_10V6K~D

MEM_VREF4
1
C408

+1.5VSDGPU

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

R26
1K_0402_1%

R409
1K_0402_1%

CLKB0

ODT/ODT0
CS/CS0
RAS
CAS
WE

+1.5VSDGPU

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

2
2
2
2
2

25

MAB12
MAB3
MAB27

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96

1
1
1
1
1

R417
243_0402_1%

CLKB1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M8
H1

MAB19
MAB25
MAB4
MAB6
MAB5
MAB13
MAB21
MAB16
MAB23
MAB20
MAB17
MAB9
MAB14
MAB26

DQMB#3
DQMB#1

DQSL
DQSU

2
R219
R110
R265
R232
R266

CLKB0

25

B2
D9
G7
K2
K8
N1
N9
R1
R9

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

MEM_VREF7

F3
C7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

R408
1K_0402_1%

CLKB0#

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

MDB57
MDB63
MDB58
MDB62
MDB56
MDB60
MDB59
MDB61

QSB3
QSB1

ODT/ODT0
CS/CS0
RAS
CAS
WE

+1.5VSDGPU

25

MDB20
MDB18
MDB23
MDB19
MDB22
MDB17
MDB21
MDB16

E3
F7
F2
F8
H3
H8
G2
H7

DQMB[7..0]

K1
L2
J3
K3
L3

96-BALL
SDRAM DDR3
K4W1G1646E-HC12_FBGA96

25

D7
C3
C8
C2
A7
A2
B8
A3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

QSB#[7..0]

MAB30
MAB29
MAB1
MAB10
MAB11

R782
243_0402_1%~OK

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

M8
H1

MAB19
MAB25
MAB4
MAB6
MAB5
MAB13
MAB21
MAB16
MAB23
MAB20
MAB17
MAB9
MAB14
MAB26

QSB[7..0]

MAB7
MAB18
MAB28
MAB30
MAB15

MEM_VREF6

+1.5VSDGPU

CK
CK
CKE/CKE0

+1.5VSDGPU

MDB3
MDB7
MDB0
MDB5
MDB2
MDB6
MDB1
MDB4

DQMB#[7..0]

MDB15
MDB8
MDB13
MDB10
MDB12
MDB11
MDB14
MDB9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

25

D7
C3
C8
C2
A7
A2
B8
A3

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

QSB#[7..0]

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VREFCA
VREFDQ

25

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M8
H1

MAB19
MAB25
MAB22
MAB24
MAB0
MAB2
MAB21
MAB16
MAB23
MAB20
MAB17
MAB9
MAB14
MAB26

QSB[7..0]

MAB[30..0]

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

MEM_VREF5

25

MAB[30..0]

MDB27
MDB26
MDB29
MDB25
MDB30
MDB28
MDB31
MDB24

U58

25

MDB[63..0]

E3
F7
F2
F8
H3
H8
G2
H7

MDB[63..0]

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

MAB19
MAB25
MAB22
MAB24
MAB0
MAB2
MAB21
MAB16
MAB23
MAB20
MAB17
MAB9
MAB14
MAB26

U57

25

U55

Title

VRAM DDR3 / Channel B

Size Document Number
Custom

Rev
1.0

LA-5811P

Date:

Tuesday, December 29, 2009

Sheet
1

27

of

58

+3VS

C1464
1
2

Q119A

0.1U_0402_16V4Z
1

P
A

I2CC_SDA

I2CC_SDA

U20
Y

LVDS_DDC2_DATA

LVDS_DDC2_DATA 29

2N7002DW-T/R7_SOT363-6
4
5

18,30 DGPU_EDIDSEL#

R486
1
2
0_0402_5%

NC

21

Q119B

NC7SZ14P5X_NL_SC70-5
21

I2CC_SCL

I2CC_SCL

LVDS_DDC2_CLK

LVDS_DDC2_CLK 29

2N7002DW-T/R7_SOT363-6

+3VS
+3VS
10
1

SG For LVDS

52
5
54
51

57

NC
NC
NC
NC
Thermal_GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

1
2
R419 4.7K_0402_5%

5
2

LVDS_DDC2_CLK

1
2
R392 4.7K_0402_5%

2N7002DW-T/R7_SOT363-6
C

LVDS_A_0-_R 29
LVDS_A_0+_R 29
LVDS_A_1-_R 29
LVDS_A_1+_R 29
LVDS_A_2-_R 29
LVDS_A_2+_R 29
LVDS_A_C-_R 29
LVDS_A_C+_R 29

DGPU_SELECT#

R490
1
2
0_0402_5%

+3VS
C1467
0.1U_0402_16V4Z
1
2

R491
1
2
0_0402_5%
@

18 DGPU_PWMSEL#

DGPU_SELECT#

1
6
9
13
16
21
24
28
33
39
44
49
53
55

Q120B

C1470
4.7U_0603_6.3V6K

17

DDC2_CLK

DDC2_CLK

SEL

+3VS_DELAY

R493
0_0402_5% @
1
2

21 VGA_PNL_PWM
10

TS3DV520ERHUR_WQFN56_11X5

R329
0_0603_5%

R492
2.2K_0402_5%
@

U23
Y

IGPU_PWM_SELECT#

NC7SZ14P5X_NL_SC70-5

+5VS
1

U24

29,37 INV_PWM
DPST_PWM

1
R494

2
0_0402_5%

2
5
1
7

For SSI shortage issue

1A
2A
1OE#
2OE#

VCC
1B
2B
GND

C1471
2
0.1U_0402_16V4Z

8
3
6
4

LVDS_INV_PWM 29
B

SN74CBTD3306CPWR_TSSOP8

P/N from SA00001RM00 change to SA00001RM0L

0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2

2
3
7
8
11
12
14
15
19
20

10

NC

46
45
41
40
35
34
30
29
25
26

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

LVDS_A_0-_R
LVDS_A_0+_R
LVDS_A_1-_R
LVDS_A_1+_R
LVDS_A_2-_R
LVDS_A_2+_R
LVDS_A_C-_R
LVDS_A_C+_R

LVDS_DDC2_DATA

LVDS_A_0LVDS_A_0+
LVDS_A_1LVDS_A_1+
LVDS_A_2LVDS_A_2+
LVDS_A_CLVDS_A_C+

0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1

LVDS_A_0LVDS_A_0+
LVDS_A_1LVDS_A_1+
LVDS_A_2LVDS_A_2+
LVDS_A_CLVDS_A_C+

48
47
43
42
37
36
32
31
22
23

10
10
10
10
10
10
10
10

VGA_TXOUT0VGA_TXOUT0+
VGA_TXOUT1VGA_TXOUT1+
VGA_TXOUT2VGA_TXOUT2+
VGA_TXCLKVGA_TXCLK+

2N7002DW-T/R7_SOT363-6

VGA_TXOUT0VGA_TXOUT0+
VGA_TXOUT1VGA_TXOUT1+
VGA_TXOUT2VGA_TXOUT2+
VGA_TXCLKVGA_TXCLK+

0.1U_0402_16V4Z

22
22
22
22
22
22
22
22

VCC
VCC
VCC
VCC
VCC
VCC
VCC

+3VS_SWITCH
1
C1469

DDC2_DATA

0_0402_5%

0.5A
U19
4
10
18
27
38
50
56

DDC2_DATA

R489

Q120A

+3VS_DELAY

R497
2.2K_0402_5%
@

+5VS
1

U26

21 DGPU_L_BKL_EN
10 IGPU_L_BKLT_EN
17,29,30 DGPU_SELECT#
29 IGPU_VCCEN_SEL#

R498

2 0_0402_5%

2
5
1
7

1A
2A
1OE#
2OE#

VCC
1B
2B
GND

8
3
6
4

C1472
2
0.1U_0402_16V4Z
1
2
R499
0_0402_5%

ENABLT

37

SN74CBTD3306CPWR_TSSOP8

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

LVDS Switch

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Wednesday, December 30, 2009

Sheet
1

28

of

58

+LCDVDD

+3VS
Q22
SI2301BDS_SOT23

+LCDVDD

+LCDVDD

0.1U_0402_16V4Z

2
G
3

28,37

A
3

INV_PWM

R506
1
2
0_0402_5%

17,28,30 DGPU_SELECT#

NC

37

1
R507

C1479

4.7U_0805_10V4Z

C1480
4.7U_0603_6.3V6K

C1481
1U_0402_6.3V4Z

U27
Y

IGPU_VCCEN_SEL# 28

2
0_0402_5%

BKOFF#

C1482 0.1U_0402_16V4Z
1
2
R504
2
1
2
0_0402_5%
CH751H-40PT_SOD323-2

100K_0402_5%

+3VS

R505
GMCH_INV_PWM 1 @

NC7SZ14P5X_NL_SC70-5

2
LVDS_INV_PWM 28
0_0402_5%
+5VS
2 220P_0402_50V7K
2 220P_0402_50V7K

R508 1
R509 1

21 ENVDD
10 ENAVDD

2 0_0402_5%
2
2 0_0402_5%
5
DGPU_VCCEN_SEL# 1
7

C1484

U28
1A
2A
1OE#
2OE#

2
0.1U_0402_16V4Z

8
3
6
4

VCC
1B
2B
GND

SN74CBTD3306CPWR_TSSOP8

B+

Q24
2N7002_SOT23

2
G

GMCH_INV_PWM 1
C1483
DISPLAYOFF#
1
C1485

R510
100K_0402_5%

D15
1

R502

Q23 D

4.7K_0402_5%

100K_0402_5%

2N7002_SOT23

DISPLAYOFF#

C1478
0.1U_0402_16V4Z

R501

+3VS

R503

+5VALW
2

R500
110_0603_5%
C1477

1800P_0402_50V7K
2

1 0.1U_0402_16V4Z
1
C1475
C1476

C1474

C1473

1 +LCDVDD_R

390P_0402_50V7K

10U_0805_10V4Z

+3VS

2
G

37 LCD_VCC_TEST_EN

LCD_VCC_TEST_EN 1
R177
@

2
0_0402_5%

SI3457BDV-T1-E3_TSOP6~D

6
5
2
1

+3VS

68P_0402_50V8J
2
1 C1494

+3VS_LCD
R729
1
2
0_0603_5%

1
R513
100K_0402_5%~D

LVDS and USB CAM connector

INVPWR_B+

C1487
0.1U_0603_50V4Z~D

0.1U_0603_25V7K
2
1 C1495

C1486
1000P_0402_50V7K~D

40mil

Q25

40mil

JLVDS1
C399
0.1U_0402_16V4Z~D

W=40mils

INVPWR_B+

W=60mils

+LCDVDD

PWR_SRC_ON
Q26
3

2
1
100K_0402_5%~D

1
R515

W=20mils

+5VS

+3VS_LCD

Q27
SI2301BDS-T1-E3_SOT23-3 +5VS_CAM

DISPLAYOFF#

19 USB20_N7

USB20_P7

L27 @
1

USB20_N7

1
4

USB20_P7_R

USB20_N7_R

Q28
2N7002_SOT23-3

2
G

LVDS_A_2+_R
LVDS_A_2-_R
LVDS_A_C+_R
LVDS_A_C-_R

28 LVDS_A_C+_R
28 LVDS_A_C-_R
C238
2.2P_0402_50V8C

R517

3
36

DMIC_CLK

2 0_0402_5%
2 0_0402_5%

+5VS_CAM

Close to CONN

2009/07/25

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11

41
42
43
44
45
46
47
48
49
50
51

2010/07/25

Deciphered Date

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

I-PEX_20439-040E-01_40P
CONN@

Compal Secret Data

Security Classification
Issued Date

C1493

R728 1
R727 1

100P_0402_50V8J~D

DMIC_DATA

C231
2.2P_0402_50V8C

C1492
100P_0402_50V8J~D

W=20mils

2
1
A

37 LVDS_CONN
38 STATUS_BOARD_CONN

DMIC_DATA
DMIC_CLK

DMIC_DATA
36
DMIC_CLK

D31
@
PJDLC05C_SOT23-3

2
0_0402_5%

USB20_P7_R
USB20_N7_R

WCM2012F2S-900T04_0805

1
R516

LVDS_A_1+_R
LVDS_A_1-_R

28 LVDS_A_2+_R
28 LVDS_A_2-_R

D16 @
PJDLC05C_SOT23-3

LVDS_A_0+_R
LVDS_A_0-_R

28 LVDS_A_1+_R
28 LVDS_A_1-_R

CAM_ON/OFF

2 0_0402_5%

LVDS_DDC2_CLK
LVDS_DDC2_DATA

28 LVDS_A_0+_R
28 LVDS_A_0-_R

37 CAM_ON/OFF#

19 USB20_P7

R518
1

GMCH_INV_PWM
R519 2 0_0402_5%

LCD_TEST

28 LVDS_DDC2_CLK
28 LVDS_DDC2_DATA

C1490
0.1U_0402_16V4Z

1K_0402_5%~D

R512 1

37

100K_0402_5%~D
2
1

2
G

1
1

1
C1491

0.1U_0402_10V6K~D

2N7002W-7-F_SOT323-3~D

37 EN_INVPWR
B

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

Title

Compal Electronics, Inc.

LCD CONN

Size

Document Number

Rev
1.0

LA-5811P
Date:

Tuesday, December 29, 2009

Sheet
1

29

of

58

+5VS

+RCRT_VCC
D17
2

+CRTVDD

W=40mils

F1
1

CH491D_SC59

1.1A_6VDC_FUSE

C1497
0.1U_0402_16V4Z

+5VS

5
1

CRT_VSYNC_R

U30
SN74AHCT1G125GW_SOT353-5
4 VSYNC_G_A

2 0_0603_5%

R532
1

2 0_0603_5%

1
2

R528
3VDDCDA_R 2
1
0_0402_5%

CRT_DDC_DATA

R530
3VDDCCL_R 2
1
0_0402_5%

CRT_DDC_CLK

DVSYNC

Q29B
2N7002DW-T/R7_SOT363-6

1 @
C1506

R534
51K_0402_5%

1 @
C1507

5P_0402_50V8C

BLUE
GREEN
RED

5P_0402_50V8C

@ D20
DAN217_SC59

@ D19
DAN217_SC59

+3VS

@ D18
@D18
DAN217_SC59

R533
51K_0402_5%

+3VS

Q29A
2N7002DW-T/R7_SOT363-6
3

DHSYNC

R531
1

R523
100K_0402_5%

D_DDCCLK
U29
SN74AHCT1G125GW_SOT353-5
HSYNC_G_A
Y 4

D_DDCDATA

C1505
0.1U_0402_16V4Z
1
2

P
OE#

CRT_HSYNC_R

P
OE#

5
1

2
1
R529
10K_0402_5%

16
17

R525

2.2K_0402_5% 2.2K_0402_5%
2

C1504
0.1U_0402_16V4Z
1
2

G
G

+CRTVDD

1
R524

+CRTVDD

SUYIN_070546FR015M21TZR CRT_DET#
+CRTVDD

+5VS

CRT Connector

1
2

1
2

BLUE
C1503
10P_0402_50V8J

GREEN

C1502
10P_0402_50V8J

C1501
10P_0402_50V8J

C1500
10P_0402_50V8J

C1499
10P_0402_50V8J

C1498
10P_0402_50V8J

R522
150_0402_1%

R521
150_0402_1%

R520
150_0402_1%

CRT_B

RED

CRT_G

L30
1
2
FCM2012CF-800T06_2P
L31
1
2
FCM2012CF-800T06_2P
L32
1
2
FCM2012CF-800T06_2P

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

CONN@
JCRT1
CRT_R

+CRTVDD

1
C1509
2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1
C1508

1
C1510
U61
+3VS

21 VGA_CRT_R
21 VGA_CRT_G
21 VGA_CRT_B
21 VGA_CRT_HSYNC
21 VGA_CRT_VSYNC
21 VGA_DDC_CLK
21 VGA_DDC_DATA

+3VS

1 R527
1 R526

10
10

10
2 2.2K_0402_5% 10
10
2 2.2K_0402_5% 10
10

M_RED
M_GREEN
M_BLUE
CRT_HSYNC
CRT_VSYNC

3VDDCCL
3VDDCDA

4
16
23
29
32
27
25
22
20
18
12
14
26
24
21
19
17
13
15

VDD
VDD
VDD
VDD
VDD
0B1
1B1
2B1
3B1
4B1
5B1
6B1
0B2
1B2
2B2
3B2
4B2
5B2
6B2

A0
A1
A2
A3
A4
SEL1
A5
A6
SEL2

GND
GND
GND
GND
GPAD

CRT_R
CRT_G
CRT_B
CRT_HSYNC_R
CRT_VSYNC_R

1
2
5
6
7
8

Place close to JCRT1

DGPU_SELECT# 17,28,29

NOTE:

CRT_DDC_CLK
CRT_DDC_DATA

9
10
30

L : B1, EXT
H: B2, INT

DGPU_EDIDSEL# 18,28

3
11
28
31
33

PI3V712-AZLEX_TQFN32_6X3~D

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

CRT CONN

Size

Document Number

Rev
1.0

LA-5811P
Date:

Tuesday, December 29, 2009

Sheet
1

30

of

58

@
R570
0_0402_5%
1
2
+3VS_DELAY

+HDMI_5V_OUT

5V Level
+3VS

+HDMI_5V_OUT

W=40mils

F2

R569
R571
2.2K_0402_5%

+5VS

SS1040_SOD123

DVI_SDATA_L

1
2
L36
FCM2012CF-800T06_2P

DVI_SDATA

DVI_SCLK_L

1
2
L37
FCM2012CF-800T06_2P

DVI_SCLK

21

HDMI_DET

Q31

R574

1
2
10K_0402_5%

2N7002_SOT23
19

HDMI_HPD#
1

@
R577
0_0402_5%

C1538

10P_0402_50V8J

C1539

10P_0402_50V8J

Place closed to JHDMI1

2N7002DW-T/R7_SOT363-6

Q30A

+HDMI_5V_OUT

Q32

L38
MBK1608221YZF_2P
1
2

HP_DETECT

D22
BAV99-7-F_SOT23-3
@

R578
100K_0402_5%

2
G

C1541
220P_0402_50V7K

VGA_DVI_SCLK

22 VGA_DVI_SCLK

1.1A_6VDC_FUSE

Q30B
2N7002DW-T/R7_SOT363-6

VGA_DVI_SDATA
2

22 VGA_DVI_SDATA

C1536
0.1U_0402_16V4Z

R568
2.2K_0402_5%
2

R576

D21
1

DDC to HDMI CONN

2.2K_0402_5%
2
1

2.2K_0402_5%
2
1

2
1

2N7002_SOT23
+3VS

DVI_TXD1-_R
DVI_TXD1+_R

2
2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

DVI_TXD0-_R
DVI_TXD0+_R

1
R579

2
0_0402_5%

C_DVI_R_TXD2-

DVI_TXD0-_R

1
R580

WCM-2012-900T_4P
1

4 4
L40

4 4
L39

JHDMI1
HP_DETECT

DVI_TXD2+_R

1
R581

2
0_0402_5%

C_DVI_R_TXD2+

DVI_TXD0+_R

1
R588

2
0_0402_5%

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

DVI_SDATA
DVI_SCLK
C_DVI_R_TXD0+
C_DVI_R_TXC-

R594
100K_0402_5%

+HDMI_5V_OUT

C_DVI_R_TXC+
C_DVI_R_TXD01
R591

2
G

Q33
S
2N7002_SOT23

3
2

+3VS_DELAY

C_DVI_R_TXD0-

WCM-2012-900T_4P

2
0_0402_5%

C_DVI_R_TXD1-

DVI_TXC-_R

1
R592

WCM-2012-900T_4P
0_0402_5%

2
0_0402_5%

DVI_TXD1-_R

1
R593

1
2

499_0402_1%
R590

499_0402_1%
R589

499_0402_1%
R587

499_0402_1%
R586

499_0402_1%
R585

499_0402_1%
R584

499_0402_1%
R583

499_0402_1%
R582

HDMI Connector
DVI_TXD2-_R

DVI_TXC-_R
DVI_TXC+_R

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

2
2

C1548
C1549

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

VGA_DVI_TXCVGA_DVI_TXC+

2
2

C1546
C1547

DVI_TXD2-_R
DVI_TXD2+_R

C1544
C1545

VGA_DVI_TXD0VGA_DVI_TXD0+

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

22 VGA_DVI_TXC22 VGA_DVI_TXC+

VGA_DVI_TXD1VGA_DVI_TXD1+

2
2

22 VGA_DVI_TXD022 VGA_DVI_TXD0+

C1542
C1543

22 VGA_DVI_TXD122 VGA_DVI_TXD1+

VGA_DVI_TXD2VGA_DVI_TXD2+

22 VGA_DVI_TXD222 VGA_DVI_TXD2+

DVI_TXD1+_R
2

1
R595

2
0_0402_5%

C_DVI_R_TXCC_DVI_R_TXD0+
C_DVI_R_TXD1-

WCM-2012-900T_4P

1
L41

2
0_0402_5%

C_DVI_R_TXD1+

DVI_TXC+_R

3
2

1
R596

C_DVI_R_TXD1+
C_DVI_R_TXD2-

1
L42

C_DVI_R_TXD2+

2
0_0402_5%

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21
22
23

LOTES_ABA-HDM-029-P01
C_DVI_R_TXC+

Compal Secret Data

Security Classification
Issued Date

2009/07/25

Deciphered Date

2010/07/25

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

HDMI

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Wednesday, December 30, 2009

1

Sheet

31

of

58

Co-lay
F3

DP_DDC_DATA_R

R600
0_0402_5%~D
1

DISP_DDC_DAT_C

C1557
0.1U_0402_10V6K~D

R601
100K_0402_1%~D

C1552 2
C1553 2

1
1

0.1U_0402_10V6K~D
0.1U_0402_10V6K~D

DISP_A0N
DISP_A0P

22 DISP_A1N_VGA
22 DISP_A1P_VGA

C1555 2
C1556 2

1
1

0.1U_0402_10V6K~D
0.1U_0402_10V6K~D

DISP_A1N
DISP_A1P

22 DISP_A2N_VGA
22 DISP_A2P_VGA

C1558 2
C1559 2

1
1

0.1U_0402_10V6K~D
0.1U_0402_10V6K~D

DISP_A2N
DISP_A2P

22 DISP_A3N_VGA
22 DISP_A3P_VGA

C1560 2
C1561 2

1
1

0.1U_0402_10V6K~D
0.1U_0402_10V6K~D

DISP_A3N
DISP_A3P

DISP_A1N
DISP_A2P
DISP_A2N
DISP_A3P
DISP_A3N
DISP_EN
DISP_CEC
DISP_DDC_CLK_C

+5VS

Q124B
2N7002DW-7-F_SOT363-6~D

DISP_DDC_DAT_C
DISP_HD

+5VS

3
6

DISP_A3N

Q125A
2N7002DW-7-F_SOT363-6~D

Close connect

3
8

19

DISP_A3N

DISP_A3P
1

DISP_A0P

2
0.1U_0402_10V6K~D

DISP_A3P

22U_0805_6.3V6M~D

DISP_A0P

C1563

10 DISP_A0N

1M_0402_5%~D

5.1M_0402_5%

DISP_A0N

C1564

R605

C1562
0.1U_0402_10V6K~D

@ D23

R604

100K_0402_1%~D
Q125B
2N7002DW-7-F_SOT363-6~D
5

Place close JDP1

R613

21
22
23
24

R614
100K_0402_1%~D
DISP_DDC_EN

JDP1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

DISP_A0N
DISP_A1P

+3VS_DELAY

DISP_A0P

R603
100K_0402_1%~D
DISP_DDC_EN
2

R602
100K_0402_1%~D

DISP_DDC_CLK_C

Q124A
2N7002DW-7-F_SOT363-6~D

22 DISP_A0N_VGA
22 DISP_A0P_VGA

C1554
0.1U_0402_10V6K~D
2
1

R598
100K_0402_1%~D

22 DP_DDC_DATA

22 DP_DDC_CLK

DP_DDC_CLK_R

1 0_1206_5%~D

1
4
5

C1551
0.1U_0402_16V4Z~D

R597 2

Q123B
2N7002DW-7-F_SOT363-6~D

R599
0_0402_5%~D
1
2

+3VS_DP

C1550
10U_0805_10V4Z~D

DISP_DDC_EN

1.5A_6V_1206L150PR~D

D
LANE0_P
GND
LANE0_N
LANE1_P
GND
LANE1_N
LANE2_P
GND
LANE2_N
LANE3_P
GND
LANE3_N
CONFIG1

CONFIG2

AUXCH_P
GND
AUXCH_N
HPD
RETURN

DP_PWR

GROUND

+3VS

Q123A
2N7002DW-7-F_SOT363-6~D

+3VS_DP

MOLEX_105088-0001
CONN@

DP_HPD_SB

RCLAMP0524P.TCT~D

+3VS_DELAY

DISP_A1N

DISP_A2P

DISP_A2P

DISP_A2N

DISP_A2N

R606
150K_0402_5%
1
2

Q37
MMBT3904_NL_SOT23-3

21

1 R607

DP_HPD

2
B

2 0_0402_5%~D

R608
1M_0402_5%~D

10 DISP_A1P

DISP_A1N

@ D24
DISP_A1P

R609
10K_0402_5%~D
2

RCLAMP0524P.TCT~D

+3VS

2
VEN
VIN
VO
VSET

GND
GND
GND
GND

8
7
6
5

RT9027BPS SO 8P

+3VS
1

+FAN_POWER

R610
10K_0402_5%
A

40mil

23
24

JFAN1
1
2
3

1
2 G
3 G

4
5

MOLEX_53398-0371

37 FAN_SPEED1
1

C1577
0.01U_0402_16V7K

Pin1 GND
Pin2 CLK
Pin3 DATA

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
GND1
VCC12
GND2
VCC12
VCC12

SATA_IRX_DTX_N0_C
SATA_IRX_DTX_P0_C

SATA_ITX_DRX_P0 18
SATA_ITX_DRX_N0 18

C1568 0.01U_0402_16V7K
1
2 SATA_IRX_DTX_N0
1
2 SATA_IRX_DTX_P0

19,36

FFS_INT2

Q118
SSM3K7002FU_SC70-3~D

SATA_IRX_DTX_N0 18
SATA_IRX_DTX_P0 18

FFS_INT2_Q

D10
SDM10U45-7_SOD523-2~D

C1569 0.01U_0402_16V7K

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

@
J3
2
HDD_DET#
+5VS

HDD_DET#

40 mils

FFS_INT2_Q

19

+3VS
1

JUMP_43X118

+5VS

Pleace near HDD CONN (JHDD1)

1

FOX_LD2122H-S4SL6~D
CONN@

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

FFS_INT2

C1576
1000P_0402_25V8J

1
2
3
4

SATA_ITX_DRX_P0
SATA_ITX_DRX_N0

C1575
0.1U_0402_16V4Z

EN_DFAN1

EN_DFAN1

@ R344
100K_0402_5%~D

C1574
0.1U_0402_16V4Z

C1567
10U_1206_16V4Z
2

C1573
10U_0805_10V4Z

1
2
3
4
5
6
7

GND
HTX+
HTXGND
HRXHRX+
GND

+5VS

U37

37

Near CONN side.

JHDD1
C1566

HDD Connector

C1634
0.1U_0402_16V4Z

C1565
2

FAN Control circuit

1000P_0402_50V7K

+5VS

10U_1206_16V4Z

40mil

+FAN_POWER

C1628
10U_0805_10V4Z

Title

Compal Electronics, Inc.

DP/FAN/HDD

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

32

of

58

SIM Card

0_0402_5%
0_0402_5%

GND1

WWAN_SMB_CK_R
WWAN_SMB_DA_R

C1184

C1517

47P_0402_50V8J~D

C1522

C1521
330U_D2E_6.3VM_R25M

C1516

C1515

4.7U_0805_10V4Z

C1514

0.047U_0402_16V4Z~D

C1520
0.1U_0402_16V4Z

110 mils

UIM_DATA
D

SRV05-4.TCT_SOT23-6~D

+UIM_PWR

ICH_SMBCLK 14,15,16,19,36
ICH_SMBDATA 14,15,16,19,36

JSIM1
R5441

USB20_N5_R

L33 @
1

USB20_P5_R

54

GND2

2 0_0402_5%
2 0_0402_5%

1
1

+3VS

+UIM_PWR

LOTES_AAA-PCI-041-K01
R657
100K_0402_5%

2 0_0402_5%

5
6
7
8
9

UIM_VPP
UIM_DATA

USB20_N5

USB20_P5

USB20_N5 19

GND
VPP
I/O
GND
GND

VCC
RST
CLK
NC

1
2
3
4

UIM_RESET
UIM_CLK

HB_5680629-SICR11

USB20_P5 19

WCM2012F2S-900T04_0805

R542
R543

USB20_N5_R
USB20_P5_R

53

WWAN_RADIO_OFF# 37

UIM_CLK

UIM_VPP

C1527

2
2

1U_0603_10V4Z~D

R545 1
R546 1

EC_TX
EC_RX

WWAN_RADIO_OFF#
PLT_RST#_Buff

33P_0402_50V8J~D

37
37

C1525

+3VS

+UIM_PWR

UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP

UIM_RESET

C1526
33P_0402_50V8J~D

19 PCIE_ITX_WWANRX_N4
19 PCIE_ITX_WWANRX_P4

U34 @
1

33P_0402_50V8J~D

19 PCIE_IRX_WWANTX_N4
19 PCIE_IRX_WWANTX_P4

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

C1523

16 CLKREQ_WWAN#
16 CLK_PCIE_WWAN#
16 CLK_PCIE_WWAN

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

C1524
33P_0402_50V8J~D

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

C1518
0.047U_0402_16V4Z~D

PCIE_WAKE#

19 PCIE_WAKE#

C1519
4.7U_0805_10V4Z

+1.5VS
JWWAN1
D

0.1U_0402_16V4Z

WWAN PCIE MiniCard

0.01U_0402_25V7K

0.01U_0402_25V7K

+1.5VS

2 0_0402_5%

19 PCIE_WAKE#
16 CLKREQ_WLAN#
16 CLK_PCIE_WLAN#
16 CLK_PCIE_WLAN
16 CLK_DEBUG_PORT_1
19 PCIE_IRX_WLANTX_N2
19 PCIE_IRX_WLANTX_P2
19 PCIE_ITX_WLANRX_N2
19 PCIE_ITX_WLANRX_P2

2
+3V_WLAN
+1.5VS

Normal

+-9%

1000

750

+3.3Vaux

+-9%

330

250

+1.5V

+-5%

500

375

JWLAN1

PCIE_WAKE#
COEX2_WLAN_ACTIVER551 1
BT_ACTIVE
R549 1
CLKREQ_WLAN#

1
2 0_0402_5%3
2 0_0402_5%5
7
9
11
13
R558
0_0402_5%
15
PLT_RST#_Buff 1
2
17
1
2
19
R559
0_0402_5%
21
PCIE_IRX_WLANTX_N2
23
PCIE_IRX_WLANTX_P2
25
27
29
PCIE_ITX_WLANRX_N2
31
PCIE_ITX_WLANRX_P2
33
35
37
39
+3V_WLAN
41
43
45
47
49
51
53

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

Aux Power
Normal

250 (Wake enable)

5 (Not wake enable)
NA

C1136

Peak

+3.3V

C1535
47P_0402_50V8J~D

C1533

4.7U_0805_10V4Z

C1532

0.1U_0402_16V4Z

C1116

0.01U_0402_25V7K

C1530
4.7U_0805_10V4Z

C1529
0.1U_0402_16V4Z

+1.5VS

C1531
47P_0402_50V8J~D

C1528
0.047U_0402_16V4Z~D

+3VS

0.01U_0402_25V7K

+3V_WLAN

2
1
R548
0_1206_5%

Voltage
Tolerance

C1534

40 mils WLAN/WIMAX PCIE Mini Card

20 mils

Primary Power

PWR
Rail

0.047U_0402_16V4Z~D

R5471

R550 1

For Compal LPC debug card

R552
R553
R554
R555
R556

1
1
1
1
1

2
2
2
2
2

WLAN_RADIO_OFF#
PLT_RST#_Buff

WLAN_SMB_CLK_R
WLAN_SMB_DAT_R

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

19

USB20_P6

19

USB20_N6

USB20_P6

L34 @
1

USB20_N6

LPC_LFRAME#
LPC_FRAME# 18,37
LPC_AD3
LPC_AD3 18,37
LPC_AD2
LPC_AD2 18,37
LPC_AD1
LPC_AD1 18,37
LPC_AD0
LPC_AD0 18,37

USB20_N4_R

L35 @
1

USB20_P4_R

USB20_P6_R

USB20_N6_R

R560
R561

1
1

2 0_0402_5%
2 0_0402_5%

USB20_N4

USB20_P4

USB20_N4_R
USB20_P4_R

2 0_0402_5%

JBT1
37

BT_DET#
COEX2_WLAN_ACTIVE
BT_OFF#
BT_RADIO_OFF#

BT_DET#

37 BT_OFF#
37 BT_RADIO_OFF#

1
3
5
7
9
11
13

1
3
5
7
9
11
13

2
4
6
8
10
12
14

GNDGND

2 BT_ACTIVE
4
6 USB20_P6_R
8 USB20_N6_R
10
12
14

+3VS

16

HRS_DF12(3.0)-14DP-0.5V(86)~D
SP01000SL0L
CONN@

USB20_N4 19

Compal Secret Data

Security Classification
USB20_P4 19

2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2 0_0402_5%

Bluetooth

ICH_SMBCLK 14,15,16,19,36
ICH_SMBDATA 14,15,16,19,36

15

WCM2012F2S-900T04_0805
R5631

R557 1

2 0_0402_5%

WLAN_RADIO_OFF# 37
PLT_RST#_Buff 34,37

LOTES_AAA-PCI-041-K01
R562 1

WCM2012F2S-900T04_0805

54

GND2

2 0_0402_5%

Title

Compal Electronics, Inc.

WLAN/WWAN/SIM/BT

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

33

of

58

C1631, C1632, L45 Close to pin 1 60mil

4.7K_0402_5%

1
R664
10K_0402_5%
@

U44

2
6

+2.5V_VDDH

PLT_RST#_Buff
EC_PME#

3
4
7

16 CLK_PCIE_LAN

CLK_PCIE_LAN

16 CLK_PCIE_LAN#

CLK_PCIE_LAN#

2
C1705
2
C1706

1
1

41

0.1U_0402_16V7K~D

40

0.1U_0402_16V7K~D

PCIE_ITX_LANRX_P1

19 PCIE_ITX_LANRX_P1

43

PCIE_ITX_LANRX_N1

19 PCIE_ITX_LANRX_N1
19 PCIE_IRX_LANTX_P1
19 PCIE_IRX_LANTX_N1

PCIE_IRX_LANTX_P1
PCIE_IRX_LANTX_N1

44
PCIE_IRX_LANTX_P1_C
0.1U_0402_16V7K~D
PCIE_IRX_LANTX_N1_C
1
0.1U_0402_16V7K~D

2
C1640
2
C1642

Place Close to Chip

LAN_X1
LAN_X2

38
37
9
10
31
33

LX
VDD3V

VDD25V

CLKREQn

PERSTn
WAKEn

TRXP0
TRXN0
TRXP1
TRXN1

SEL_25 MHz
REFCLKP

RX_P
RX_N
TX_P

SMCLK
SMDATA

2
R671
1

1
2.37K_0402_1%~D

C1645
15P_0402_50V8J

C1646
18P_0402_50V8J

12
34
49

13
14
17
18

1
R666
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-

11
42

AVDDVCO1
AVDDVCO2

RBIAS
TESTMODE

NC
NC
NC
NC

GND

NC

28
32
45
46

+1.2_DVDDL

CLKREQ_LAN#
0_0402_5%~D

CLKREQ_LAN#

16

8
16
22
36
39

+1.2_AVDDL

R668
1

1
2
R667
0_0603_5%~D

1
C1638
1U_0402_6.3V4Z~D

0_0603_5%~D
2
1

15
19
25

VDDHO
AVDDH
AVDDH

LAN_X2

25MHZ_12PF_X5H025000FC1H-H
1

DVDDL
DVDDL
DVDD_REG
DVDD_REG

VDD11_ REG
AVDDL
AVDDL
AVDDL
AVDDL

XTLO
XTLI

LAN_SK_LAN_LINK100#
LAN_SK_LAN_LINK10#

+1.2_AVDDL

AR8132 10/100 LAN

TX_N

LAN_ACTIVITY

27

AVDD_ REG
AVDDL

Atheros

REFCLKN

Y4
LAN_X1

47
48
26

LED0
LED1
LED2

VDD17

+3V_LAN

C1637

+2.5V_VDDH/VDD17

29
30

TWSI_CLK
TWSI_DATA

R662
10K_0402_5%
@
10U_0805_10V4Z~D

+3V_LAN

33,37 PLT_RST#_Buff
17,37 EC_PME#

C1630
0.1U_0402_16V4Z~D

Layout Notice : Place as close

chip as possible.

the common mode voltage of the input pcie clock must be lower than 0.5V

2
0.1U_0402_16V4Z~D

1
C1629
0.1U_0402_16V4Z~D

+3V_LAN

+2.5V_VDDH/VDD17

+1.8_VDD/LX

C1633 1

30mil

R661
0_0603_5%~D

R661 close to TR1

49.9_0402_1%~D
49.9_0402_1%~D
49.9_0402_1%~D
49.9_0402_1%~D

+AVDD_CEN 1

2
2
2
2

R663
D

1
1
1
1

C1639

1CLKREQ_LAN#

R656
R658
R659
R660

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-

0.1U_0402_16V4Z~D

20mil

C1632

Place Close to Chip

+1.8_VDD/LX
2
4.7UH_1008HC-472EJFS-A_5%_1008

1
L45

1
0.1U_0402_16V4Z~D

C1631

1
10U_0805_10V4Z~D

+3VS

2
C1643
1U_0402_6.3V4Z~D

C1636
0.1U_0402_16V4Z~D

If overclocking, R668 stuffed and R667 removed.

If not overclocking, R667 suffed and R668 removed.
AR8132:C72=0.1uF.

Place C1636 close to Pin19

35

C1644
0.1U_0402_16V4Z~D

Place C1641 close to Pin11

AVDDVCO2

+2.5V_VDDH

20
21
23
24

AVDDVCO1
C1641
0.1U_0402_16V4Z~D

SA000036Y00

AR8132-AL1E_QFN48_6X6

Place C1650 close to Pin8. C1651,C1652,C1653 close to Pin16, Pin36, Pin39

TR1
LAN_MDI1+
LAN_MDI1+AVDD_CEN
1
C1648

1U_0402_6.3V4Z~D

C1647
0.1U_0402_16V4Z~D

C1649
0.1U_0402_16V4Z~D
LAN_MDI0+
2
LAN_MDI0-

1
2
3
4
5
6
7
8

RD+
RDCT
NC
NC
CT
TD+
TD-

16
15
14
13
12
11
10
9

RX+
RXCT
NC
NC
CT
TX+
TX-

R672
1
1
R673

75_0402_5%~D
2
+TRCT
2
75_0402_5%~D

C1654
1000P_1206_2KV7~D

C1650
0.1U_0402_16V4Z~D

C1652
0.1U_0402_16V4Z~D

Place C1655 close to Pin46. C1656,C1657,C1658 close to Pin28, Pin32, Pin45

C1656
0.1U_0402_16V4Z~D
JLAN1

R675
5.1K_0402_1%~D

C1659
@

13
LAN_ACTIVITY_R

470P_0402_50V7K

LAN_ACTIVITY

12
8
7

RJ45_MIDI1-

6
5
4

RJ45_MIDI1+

RJ45_MIDI0-

RJ45_MIDI0+

LAN_SK_LAN_LINK100#

11

LAN_SK_LAN_LINK10#

2 R676

1+3V_LAN_LED

2
C1182
@

470P_0402_50V7K

10

511_0402_1%~D

Yellow LED-

C1655
1U_0402_6.3V4Z~D

Yellow LED+

C1658
0.1U_0402_16V4Z~D

TX3TX3+
TX1-

Place C1660 close to Pin15, C1661 close to Pin25

TX2TX2+

+2.5V_VDDH

TX1+
C1660
1U_0402_6.3V4Z~D

TX0TX0+
Orange LED-

GND
GND

15
14

C1662

2 0.1U_0402_16V4Z~D

C1663

2 0.1U_0402_16V4Z~D

C1661
0.1U_0402_16V4Z~D

Green LEDGreen-Orange LED+

TYCO_2041633-1
CONN@

Compal Secret Data

Security Classification
2009/07/25

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

C1657
0.1U_0402_16V4Z~D

+1.2_DVDDL

Issued Date

C1653
0.1U_0402_16V4Z~D

SP050001210

R674
511_0402_1%~D

+3V_LAN

RJ45_CT1
RJ45_MIDI0+
RJ45_MIDI0-

C1651
0.1U_0402_16V4Z~D
+1.2_AVDDL

350uH_NS0013LF

Pull down circuit:

more power saving in no-overclocking mode
vendor suggestion

RJ45_MIDI1+
RJ45_MIDI1RJ45_CT0

Title

Compal Electronics, Inc.

LAN

Size
Document Number
Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

34

of

58

3 in 1 Card Reader CONN

+3V_MCVCC

1
C1672
2

C1673
@

1
C1674
@
2
R701
33_0402_1%

XD_SD_MS_D2
XDCD1#_MSCD#
XD_SD_MS_D3
SDCMD_MSBS_XDWE#
XDCE_SDCLK_MSCLK

22P_0402_50V8J

C1512

XD_SD_MS_D3

R694
33_0402_1%

XD_SD_MS_D2
XDCD0#_SDCD#

22P_0402_50V8J
XIN
1

C1675 1
C1676 1

19 PCIE_IRX_CRTX_N5
19 PCIE_IRX_CRTX_P5

19 PCIE_ITX_CRRX_N5
19 PCIE_ITX_CRRX_P5

9
8

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_IRX_CRTX_N5_C
PCIE_IRX_CRTX_P5_C

R677 1
8.2K_0402_1%

R678
Y5 1M_0402_5%
24.576MHZ_16P_X8A024576FG1H

APREXT

APREXT 12 mil
XIN
XOUT

C1677
2

3
4

38
39

APCLKN
APCLKP
APRXN
APRXP
APTXN
APTXP

22P_0402_50V8J

C1679

2
0.1U_0402_16V7K

1
2

8,17,37 PLT_RST#

19

CR_CPPEN

R684 1

T71 PAD

GPIO PIN
+3VS
R688
1

4.7K_0402_1%
XDCD1#_MSCD#
2

1
R690

XDCD0#_SDCD#
2
4.7K_0402_1%

30

2 0_0402_5% 13
14
@

XDCD1#_MSCD#
XDCD0#_SDCD#
+3V_MCPWR

15
16
17
21

APVDD
APV18

5
10

DV33
DV33
DV33
DV18
DV18

19
20
44
18
37

APREXT
TXIN
TXOUT

JMB380

XOUT

1
C1678

+3VS

11
12

TAV33
XRSTN
XTEST
SEEDAT
SEECLK

MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

TPA1P
TPBIAS_1
TREXT

CR1_CD1N
CR1_CD0N

APGND
CR1_PCTLN
TCPS
TPB1N
TPB1P
TPA1N

CR1_LEDN

TPAD

22P_0402_50V8J

48
47
46
45
43
42
41
40
29
28
27
26
25
23
22

+1.8VS_APVDD
+3V_MCVCC
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
SDCMD_MSBS_XDWE#
MDIO5
R681 1
XDWP_SDWP

SDCMD_MSBS_XDWE# 1
R679
XDWP_SDWP
1
R680

2
10K_0402_5%
2
10K_0402_5%

MDIO7
+3VS
MDIO12
MDIO13
MDIO14

MDIO7

2
10K_0402_5%
2
1K_0402_1%

R682
MDIO13

IEEE1394_TPAP0
IEEE1394_TPBIAS0 R686
1

12K_0402_1%
2

MDIO12

R685

MDIO14

2200K_0402_1%

2
200K_0402_1%

R687
IEEE1394_TPBN0
IEEE1394_TPBP0
IEEE1394_TPAN0

1
R689

2
10K_0402_1%
R6910_0402_5%~D
IEEE1394_TPBN0_R
1
2
R6920_0402_5%~D
IEEE1394_TPBP0_R
1
2

49

Layout Note:
Add GND shield for 1394.

DLW21SN121SQ2L_4P~D
@ 4
4
3 3

IEEE1394_TPBN0

1394 CONN

GND

J1
IEEE1394_TPBP0

Memory Card Power Switch

IEEE1394_TPAP0

Q44 @
2N7002_SOT23

1
R693
1
R699

L48

GND
GND
GND
GND

8
7
6
5

FOX_UV31413-WS23P-7F~D
DC235000T0L
CONN@

2 IEEE1394_TPAN0_R
0_0402_5%~D
2 IEEE1394_TPAP0_R
0_0402_5%~D

IEEE1394_TPBIAS0

Layout Note: Shield GND for

IEEE1394_TPA and TPB

Minimize this distance between

IC and terminating resistor.

+3V_MCVCC

0_0805_5%
1

DELL CONFIDENTIAL/PROPRIETARY

C1685

4.7U_0805_10V4Z

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

TPBTPB+
TPATPA+

1
2

2
1

1 2
3

2
G

1
R704

C1684

+3V_MCPWR

4.7U_0805_10V4Z
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z

R703

+3V_MCPWR

C1682 1

R698
56.2_0402_1%~D

TPS2061DRG4_SO8
R700
@
300_0603_5%

C1681 1

0.33U_0402_10V6K
R697
56.2_0402_1%~D

C1680 1

R696

OUT
OUT
OUT
FLG

56.2_0402_1%~D 4.99K_0402_1%
C1683
R695

GND
IN
IN
EN#

40mil

8
7
6
5

56.2_0402_1%~D220P_0402_50V8K

+3V_MCPWR

1
2
3
4

GND

+3V_MCVCC
U46
1
2
3
4

1
2
L47
DLW21SN121SQ2L_4P~D
@ 4
4
3 3

GND
IEEE1394_TPAN0

+3VS

2 33_0402_1% XDCE_SDCLK_MSCLK

6
24
31
32
33

22
23

+3VS

R683
34
35
36

TAITW_R009-121-LK_RV
SP07000KT00
CONN@

C1511

+1.8VS_APVDD

JMB380-QGAZ0B_QFN48_7X7

SD-WP-SW
SD-DAT1
SD-DAT0
SD-GND
MS-GND
MS-BS
SD-CLK
MS-DAT1
MS-DAT0
SD-VCC
MS-DAT2
SD-GND
MS-INS
MS-DAT3
SD-CMD
MS-SCLK
MS-VCC
SD-DAT3
MS-GND
SD-DAT2 GND1
SD-CD-SWGND2

U45
16 CLK_PCIE_CR#
16 CLK_PCIE_CR

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

SDCMD_MSBS_XDWE#
XDCE_SDCLK_MSCLK
XD_SD_MS_D1
XD_SD_MS_D0

1
C1671

1
C1670

0.1U_0402_16V4Z

C1669

4.7U_0603_6.3V6M

1000P_0402_50V7K

C1664

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1
C1668

0.1U_0402_16V4Z

1
C1667

22U_0805_6.3V6M

1
C1666

0.1U_0402_16V4Z

XDWP_SDWP
XD_SD_MS_D1
XD_SD_MS_D0

40mil
0.1U_0402_16V4Z

1
C1665

JCARD1

+1.8VS_APVDD

40mil
0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VS

Title

Compal Electronics, Inc.

CARD READER/1394

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

35

of

58

IO Board CONN
RTCVREF

+1.5VS

NC
A

2
2

R1238
1

D52
SDMK0340L-7-F

37,38

Q57
2N7002_SOT23

2
G

R1145
100K_0402_5%~D

USB20_N1 19
USB20_P1 19

LID_SW#

39,43

U60
TC7SZ14FU_SSOP5~D

+3VALW

1
2

USB20_N0 19
USB20_P0 19

51ON#

2.2U_0603_10V7K~D

DMIC_CLK
29
DMIC_DATA 29

CLOSE TO U48
C1068
0.1U_0402_16V4Z~D

C1105
2

USB_DETECT#

37
18
18
18
18
19

BEEP#
HDA_SYNC
HDA_SDOUT
HDA_SDIN0
HDA_RST#
SB_SPKR

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

D51
SDMK0340L-7-F

14,15,16,19,33 ICH_SMBDATA
14,15,16,19,33 ICH_SMBCLK
17 ACCEL_INT#
19,32 FFS_INT2

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

R1144
220K_0402_5%

USB_EN_R#
USB_OC#0
USB_OC#1

51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

R1143
10K_0402_1%~D

37
EC_EAPD
37
EC_MUTE#
38 IO_BOARD_CONN
18 HDA_BITCLK
37
19
19

RTCVREF

+5VS
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

+3VS +5VALW

RTCVREF

RTCVREF

JBTB1

0_0402_5%~D
2
2

USB_DET#_DELAY 37

D58
SDMK0340L-7-F

E-T_1001-F50C-02R

fix +3VALW leakage on Batt mode

Power share

+5V_CHGUSB

2.0A

USB20_N2

1D+

2
USB_CHARGE_D+

USB_CHARGE_D-

1D-

2D+

D+

2D-

D-

GND

OE#

10

+3VALW

PWRSHARE_OE#

USBP2_D+_C

R617 1

R308
49.9K_0402_1%~D

2 0_0402_5%

PWRSHARE_OE# 37
L43 @
R307
100K_0402_5%~D

USBP2_D-_C

USBP2_D-_C

USBP2_D+_C

VCC

+
C1578
2

1
C1579
2

JUSB1
1
2
3
4

USBP2_DUSBP2_D+

2
3

USB_DETECT#

WCM2012F2S-900T04_0805
R309
49.9K_0402_1%~D

0.1U_0402_16V4Z

19

150U_B2_6.3V-M~D

USB20_P2

19

2
R302
75K_0402_1%

R301
43.2K_0402_1%~D

C466
0.1U_0402_16V4Z~D
1
2

U51

+5V_CHGUSB

TS3USB221RSER_QFN10_2x1P5~D

POS
POS

R618 1

2 0_0402_5%

S Logic"1" Work from BKT

S

OE#

Function

Disconnect

L
H

L
L

GND
GND
GND
GND

7
8
9
10

FOX_UB1112C-RADAG-7F
CONN@

1
1

5
6

PJDLC05C_SOT23-3

VBUS
DD+
GND

3
@ D25

D=1D
D=2D

2.0A
+5V_CHGUSB

+5VALW
U38
1
2
3
4

37 PWRSHARE_EN#

GND
IN
EN1#
EN2#

OC1#
OUT1
OUT2
OC2#

8
7
6
5

USB_OC#2

19

10U_1206_16V4Z

C1581

0.1U_0402_16V4Z

TPS2062ADR_SO8~D
C1580

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

USB/LID SW/IO CONN

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

36

of

58

RSMRST circuit

CLK_PCI_EC

PLT_RST#_Buff

Y
A

PLT_RST#_Buff 33,34

R634

R633
100K_0402_5%
1 0_0402_5%

38 WLAN_BT_LED#

+3VALW
EC_PME#
1
10K_0402_5%
2 EC_MUTE#
10K_0402_5%
EC_SMI#
2
8.2K_0402_5%
EC_SCI#
2
8.2K_0402_5%

42
42
4,21
4,21

19,38 SLP_S3#
19,38 SLP_S5#
19
EC_SMI#
36,38 LID_SW#
33 BT_RADIO_OFF#
29 LVDS_CONN
17,34 EC_PME#
16 EC_FSB_SEL
32 FAN_SPEED1
29 CAM_ON/OFF#
33
EC_TX
33
EC_RX
39 ON/OFF_EC#
38 3V_F347_ON
36 PWRSHARE_OE#

47K_0402_5%
KSO1
2
KSO2

47K_0402_5%

+3VALW
1
10K_0402_5%
1
10K_0402_5%

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

EC_SMI#
LID_SW#
BT_RADIO_OFF#
LVDS_CONN
EC_PME#
EC_FSB_SEL
FAN_SPEED1
CAM_ON/OFF#
EC_TX
EC_RX
ON/OFF_EC#
3V_F347_ON
PWRSHARE_OE#

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

LVDS_CONN

XCLKI
XCLKO

@ 20M_0603_5%
32.768KHZ_12.5P_1TJE125DP1A000M

+5VALW

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PS2 Interface

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

INV_PWM
BEEP#

63
64
65
66
75
76

BATT_TEMP
BATT_OVP
ADP_I
AD_BID
BT_DET#

68
70
71
72
83
84
85
86
87
88
97
98
99
109

SPI Flash ROM

SM Bus

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

122
123

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

GPI

XCLK1
XCLK0

11
24
35
94
113

1
C1617
18P_0402_50V8J

C1616
18P_0402_50V8J

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
V18R

R627
20K_0402_5%
2
1

R626
9.09K_0402_1%
2
1

R625
0_0402_5%
2

INV_PWM
28,29
BEEP#
36
PWRSHARE_EN# 36
ACOFF
43,44

ACOFF

EN_DFAN1
IREF
CHGVADJ
EC_MUTE#
USB_EN_R#

BATT_TEMP
BATT_OVP
ADP_I

42
42
44

BT_DET#

33

EN_DFAN1
IREF
CHGVADJ

32
44
44

EC_MUTE#
USB_EN_R#

36
36

CHRG_STATE#
TP_CLK
TP_DATA

EN_WOL#
BT_OFF#
VGATE

Rb

ID

BOARD ID

0
1
2
3

0.1(X00)
0.2(X01)
0.3(X02)
1.0(A00)

Ra

Rb

NC
100K
100K
100K

0
9.09K
20K
37.4K

Vab
0V
0.25V
0.50V
0.82V

+5VS

R629
4.7K_0402_5%

R630
4.7K_0402_5%
C

CHRG_STATE# 38
TP_CLK
39
TP_DATA 39

EN_WOL#
BT_OFF#
VGATE

SPI Device Interface

GPIO

67
AVCC

AD Input

KB926QFD3_LQFP128_14X14

X1
EC_SMB_CK1
2
4.7K_0402_5%
EC_SMB_DA1
2
4.7K_0402_5%

2
A

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

MISC

LID_SW#
R647

1
R645
1
R646

PWM Output

Ra

BOARD ID Table

21
23
26
27

119
120
126
128

FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#

73
74
89
90
91
92
93
95
121
127

WLAN_RADIO_OFF#
USB_DET#_DELAY
FSTCHG
EN_INVPWR
CAPS_LED#
BATT_LOW_LED
LCD_TEST
SYSON
VR_ON
ACIN

100
101
102
103
104
105
106
107
108

RSMRST#
EC_LID_OUT#
EC_ON
EC_SWI#
PM_PWROK
BKOFF#
WWAN_RADIO_OFF#
LCD_VCC_TEST_EN
PSID_DISABLE#

110
112
114
115
116
117
118

SLP_S4#
ENABLT
EC_EAPD
EC_THERM#
SUSP#
PBTN_OUT#
PS_ID

124

V18R

System SPI Flash ROM (16Mb)

40
33
19,51

+3VALW
U41
INT_SPI_CS#
SPI_SO
1
2

+3VALW

R632

1
2
3
4
10K_0402_5%

CS#
SO
WP#
GND

VCC
HOLD#
SCLK
SI

8
7
6
5

R631 10K_0402_5%
1
2
SPI_CLK_R
SPI_SI
C1591

MX25L1605AM2C-12G_SO8

AGND

2
R651
2
R665 @

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

1
0_0402_5%

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

R623 2

C1606

WLAN_RADIO_OFF# 33
USB_DET#_DELAY 36
FSTCHG
44
EN_INVPWR
29
CAPS_LED#
38
BATT_LOW_LED 38
LCD_TEST
29
SYSON
40,48
VR_ON
51
ACIN
19,38,43

EC Team request
ACIN

SLP_S4#
ENABLT
EC_EAPD
EC_THERM#
SUSP#
PBTN_OUT#
PS_ID

EC_LID_OUT# 19
EC_ON
39
EC_SWI#
19
PM_PWROK
8,19,51
BKOFF#
29
WWAN_RADIO_OFF# 33
LCD_VCC_TEST_EN 29
PSID_DISABLE# 43
19
28
36
19
40,44,46,49
19
43

FSEL#SPICS# 2
R635
FWR#SPI_SI
2
R637
FRD#SPI_SO 2
R640
SPI_CLK
2
R641
33_0402_5%

INT_SPI_CS#
1
0_0402_5%
SPI_SI
1
0_0402_5%
SPI_SO
1
0_0402_5%
SPI_CLK_R
1
1

Close EC pin 126

C1593
12P_0402_50V8J

KSO8

@ C1594

100P_0402_25V8K

100P_0402_25V8K

C1595@

KSI7

KSI3

@ C1596

100P_0402_25V8K

100P_0402_25V8K

C1597@

KSI6

KSO9

@ C1598

100P_0402_25V8K

100P_0402_25V8K

C1599@

KSI5

KSI2

@ C1600

100P_0402_25V8K

100P_0402_25V8K

C1601@

KSO0

KSI1

@ C1602

100P_0402_25V8K

100P_0402_25V8K

C1603@

KSO1

KSO10 @ C1604

100P_0402_25V8K

100P_0402_25V8K

C1605@

KSO2

KSO11 @ C1608

100P_0402_25V8K

100P_0402_25V8K

C1609@

2 4.7U_0603_6.3V6K

KSI4

KSI0

@ C1611

100P_0402_25V8K

100P_0402_25V8K

C1610@

KSO3

KSO12 @ C1612

100P_0402_25V8K

100P_0402_25V8K

C1613@

KSO4

KSO13 @ C1614

100P_0402_25V8K

100P_0402_25V8K

C1615@

KSO5

KSO14 @ C1618

100P_0402_25V8K

100P_0402_25V8K

C1619@

KSO6

KSO15 @ C1620

100P_0402_25V8K

100P_0402_25V8K

C1621@

KSO7

KSO16 @ C1622

100P_0402_25V8K

+3VS
1
R648
1
R649
1
R650
2
R652
1
R653

2 EC_SMB_CK2
2.2K_0402_5%
EC_SMB_DA2
2
2.2K_0402_5%
BT_RADIO_OFF#
2
4.7K_0402_5%
PLT_RST#
1
4.7K_0402_5%
BT_DET#
2
10K_0402_5%

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

C1607

0.1U_0402_16V4Z
69

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

12
13
37
20
38

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &

ECAGND

R644

ECAGND

GND
GND
GND
GND
GND

R643

AD_BID

4.7U_0603_6.3V6K

C1592

+3VALW

0.1U_0402_16V4Z

0.1U_0402_16V4Z

5
P

2 0.1U_0402_16V4Z

@ U40
MC74VHC1G08DFT2G SC70 5P

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16

+3VALW

R622
100K_0402_5%

27
26

1
2
3
4
5
7
8
10

CLK_PCI_EC
PLT_RST#_Buff
EC_RST#
EC_SCI#
19
EC_SCI#
1
2
19 PM_CLKRUN#
R267 @ 0_0402_5%
16 CLK_PCI_EC

@ C1590

C1588

C1589

GATEA20
KB_RST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

0.1U_0402_16V4Z

PLT_RST#

2
R636
1
@R638
@
R638
1
R639
1
R642

C1587

1
47K_0402_5%
R624

ACES_88502-2501
SP01000MZ00
CONN@

8,17,35 PLT_RST#

18 GATEA20
18 KB_RST#
19 SERIRQ
18,33 LPC_FRAME#
18,33
LPC_AD3
18,33
LPC_AD2
18,33
LPC_AD1
18,33
LPC_AD0

+3VALW

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
GND

U39

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

TYCO_2041070-6~D
SP01000V80L
CONN@

JKB1
KSI7
KSI6
KSI4
KSI2
KSI5
KSI1
KSI3
KSI0
KSO5
KSO4
KSO7
KSO6
KSO8
KSO3
KSO1
KSO2
KSO0
KSO12
KSO16
KSO15
KSO13
KSO14
KSO9
KSO11
KSO10

9
22
33
96
111
125

38 KB_LED_R_DRV#
38 KB_LED_G_DRV#
38 KB_LED_B_DRV#

GND
GND
6
5
4
3
2
1

VCC
VCC
VCC
VCC
VCC
VCC

8
7
6
5
4
3
2
1

+5VS

C1586
0.1U_0402_16V4Z

KEYBOARD
CONN.

@ C1582
22P_0402_50V8J

C1585
0.1U_0402_16V4Z

JKBBL1

C1584
0.1U_0402_16V4Z

+3VALW

L44

0_0402_5%
EC_RSMRST# 19

Board ID

+3VALW

FBMA-L11-160808-601LMT_2P

+EC_AVCC

R621
10_0402_5%

C1583

R620

R619 0_0402_5%

+3VALW

RSMRST#

4.7U_0603_6.3V6K

1
POK 2

POK

45

0.1U_0402_16V4Z

R628
37.4K_0402_1%
2
1
1

Title

Compal Electronics, Inc.

EC/KB CONN

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

37

of

58

+3.3V_F347
+3.3V_F347

0.1U_0402_16V4Z

R777
4.7K_0402_1%

R753
4.7K_0402_1%

R778
4.7K_0402_1%

R757
4.7K_0402_1%

U42

+5VS

19
19

W=40mils

2
R140
0_0603_5%
C1850
1U_0805_10V7

4
5
7
8

+3.3V_F347

+3.3V_F347

USB20_P3
USB20_N3

USB20_P3
USB20_N3

9
10

R277
1K_0402_1%

C1849

18
17
16
15
14
13
12
11

0.1U_0402_16V4Z

D+
DREGIN
VBUS
RST#/C2CK
P3.0/C2D
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7

2
1
32
31
30
29
28
27

SPI_MOCLK
SPI_MOSO
SPI_MOSI
SPI_MOCS#
I2C_DAT
I2C_CLK
C1857 @ 1
2

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

26
25
24
23
22
21
20
19

SLP_S3
CHRG_STATE
ACIN#
LID_SW#

GND

0.1U_0402_16V4Z
1

SLP_S5
C1858 @ 1
C1859 @ 1

R776
1K_0402_5%
2
R754
4.7K_0402_1%

LID_SW#
36,37
BATT_LOW_LED 37

AD1
0

INT#_1

22

I2C_CLK
I2C_DAT

19
20

SCL
SDA

AD1_0
AD1_1
AD1_2

18
23
24

AD0
AD1
AD2

14
15
16
17

P12
P13
P14
P15

R755
4.7K_0402_1%

+3.3V_F347

INT#/O16

GND

V+

21

P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
GND

1
2
3
4
5
6
7
8
10
11
12
13
25

KB_LED_R_DRV# 37
KB_LED_G_DRV# 37
KB_LED_B_DRV# 37

MAX7313ATG+T_TQFN24_4X4

0.1U_0402_16V4Z
0.1U_0402_16V4Z

2
2

AD0
1

U6

+3.3V_F347

+5VALW

VDD

6
@
R279
0_0603_5%
1
2

AD2
0

1
C313
22P_0402_50V8J

0.1U_0402_16V4Z

C1843

C1842

1U_0805_10V7

2 0_0603_5%

R139 1
C1846

K/B Backlight

+3.3V_F347

C8051F347-GQ_LQFP32_7X7

JP3

LID_SW#

18

+3.3V_F347
+5VALW
+5VS
SATA_LED#

37

CAPS_LED#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

I2C_DAT
I2C_CLK
2

Status Board CONN

C1864
0.1U_0402_16V4Z

C1860
0.1U_0402_16V4Z

C1865
0.1U_0402_16V4Z

C1866
0.1U_0402_16V4Z

MOLEX_53398-0471~D
@

C1867
0.1U_0402_16V4Z

5
6

1
2
3
4

C1861
0.1U_0402_16V4Z

JP4
1
2
G1 3
G2 4

C1862
0.1U_0402_16V4Z

C1863
0.1U_0402_16V4Z

1
+3.3V_F347

D30
PESD5V2S2UT_SOT23-3~D
+3.3V_F347

37 WLAN_BT_LED#
39 ON/OFFBTN#

+3.3V_F347
1

+3.3V_F347

29 STATUS_BOARD_CONN
36 IO_BOARD_CONN

1
1
SLP_S3#

SLP_S3

CE#
WP#
HOLD#
VSS

VDD
SCK
SI
SO

1
3
7
4

8
6
5
2

R764 1
R765 1
R766 1

SPI_MOCLK
SPI_MOSI
SPI_MOSO

15_0402_5%
15_0402_5%
15_0402_5%

2
2
2

Q42
2N7002_SOT23

Close to CONN
C1851
22P_0402_50V8J~D

+3.3V_F347 behavior
STATE

+3VALW
@
J2

+3.3V_F347
1

C1853

ON

ON

BAT only

ON

ON

OFF OFF

1
R772
100K_0402_1%

0.1U_0402_16V4Z

D
Q43
2N7002_SOT23

Reference

AD2

AD1

AD0

MAX7313

DB

L/R Headlight , Logo

DB

CAP , Wireless
Power Button , Eyes/Rim

U6

K/B Backlight

C1854

S
2

Q55
2N7002_SOT23
3

R773
100K_0402_1%
2

2
G

2
G

ON

ADDRESS
000b
001b
000b

AC mode battery full in S5:turn off ELC controller

C170
4.7U_0603_6.3V

G
3

2
1
1

Q38
2N7002_SOT23

2
G

0.1U_0402_16V4Z

R774
100K_0402_1%

S
2

37 CHRG_STATE#

37 3V_F347_ON

B+

1
2

CHRG_STATE

ON

SMBUS
0100
0100
1010

R775
100K_0402_1%

R762
100K_0402_1%

AC IN

DEVICE
MAXIM - LED
MAXIM - GPIO
I2C EEPROM

6
5
2
1

+3.3V_F347

S5

SLP_S5
Q39
2N7002_SOT23

+3VALW

S4

2
SLP_S5#

S3

Q49
SI3456BDV-T1-E3 1N TSOP6

2
G
3

19,37

ACIN

19,37,43

ACIN#
D
Q40
2N7002_SOT23

JUMP_43X118

R759
100K_0402_1%

R763
100K_0402_1%

S0
+3.3V_F347

+3.3V_F347

2
G

17
18

D33
PESD24VS2UT_SOT23-3~D

MX25L8005M2C-15G_SOP8

2
G
3

19,37

0.1U_0402_16V4Z

U59
SPI_MOCS#

GND
GND

FCI_10089708-016010LF~D
CONN@

R760
100K_0402_1%

R770
10K_0402_5%

C1852

1
R769
10K_0402_5%

+3.3V_F347

R768
10K_0402_5%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

ELC/STATUS CONN

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Wednesday, December 30, 2009

Sheet
1

38

of

58

C1625

D27
ON/OFFBTN#

38 ON/OFFBTN#

P-TWO_196047-04041
CONN@

100K_0402_5%

ON/OFF_EC#

37

51ON#

36,43

1
DAN202UT106_SC70-3

C1626

2
1

0.1U_0402_25V6

Q41
3

2
R655

1 @
C1627
1000P_0402_50V7K

2
G

37 EC_ON

R654

1
2
3
4
G1
G2

@
D28
RLZ20A_LL34

1
C1624

100P_0402_50V8J

100P_0402_50V8J

3
1

D26
PJDLC05C_SOT23-3

C1623
1U_0402_6.3V4Z

JTP1
1
2
3
4
5
6

TP_CLK
TP_DATA
2

37
37

MB_Power On/Off SW

Touch pad Connector

+5VS

+3VALW

2N7002LT1G_SOT23-3
1

10K_0402_5%
C

For Debug Only

@
SW1
SMT1-05_4P
3

ON/OFFBTN#

6
5

H_3P8 *3
FD4

H17
H_2P3
@

H_2P0X2P3N *1

H22
H_3P0

H14
H15
H_4P2N H_4P2N
@
@

H_2P0 *1
H10
H_2P0

H24
H_2P0X3P0N

H13
H_1P2
@

H_3P0 *1

H20
H_3P0

H12
H_1P2
@

H16
H_2P3
@

H11
H_2P3
@

H8
H_2P3
@

H7
H_2P3
@

H_3P0 *1

H19
H_3P8
@

H6
H_2P3
@

H_4P2N *2

@
1

FIDUCIAL_C40M80

@
1

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

H18
H_3P8

H5
H_2P3
@

FD3

FD2

FD1

H4
H_2P3
@

H3
H_2P3
@

PCB-MB

SU7300@

S IC AV80577UG0133M SLGS6 R0 1.3G FCBGA

H2
H_2P3
@

H1
H_2P3
@

H_1P2 *2

ZZZ

U1

H_2P3 *10

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

SW/TP/SCREW

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

39

of

58

+5VALW to +5VS Transfer

1
2
S

Q47
SSM3K7002FU_SC70-3

2
G

C1698
2

R710
1.5M_0402_5%

EN_WOL#

2200P_0402_50V7K~D

37

EN_WOL
D

2 @

C1695

0.1U_0402_16V7K~D
C1694

Q46
SSM3K7002FU_SC70-3

5VS_GATE

22U_0805_6.3V6M
C1693

47K_0402_5%

+3V_LAN

W=40mils

R706
1
2
0_0603_5%

R709

100K_0402_5%

6
5
2
1

22U_0805_6.3V6M

3VS_GATE

470K_0402_5%

Q45
SI3456BDV-T1-E3 1N TSOP6

C1692

1U_0603_10V6K~D

B+_BIAS

C1697

+3VALW
C1691

W=40mils
1

0.01U_0402_25V7K~D

10U_0805_10V4Z~D
C1690

0.1U_0402_16V7K~D

C1686

10U_0805_10V4Z~D

C1689

10U_0805_10V4Z~D
C1688

0.01U_0402_25V7K~D

2
G

+3VALW to +3LAN Transfer

+5VS

U48
SI4800BDY-T1-E3_SO8
8
1
7
2
6
3
5

R708
1

C1696

RUNON

R707
RUNON

SUSP

0.1U_0402_16V7K~D

R705

330K_0402_5%

1
C1687

10U_0805_10V4Z~D

B+_BIAS

+3VS

U47
SI4800BDY-T1-E3_SO8
8
1
7
2
6
3
5

+5VALW
+3VALW

+3VALW to +3VS Transfer

+1.5V to +1.5VSDGPU Transfer

+5VALW

C1702
0.01U_0402_25V7K~D

330K_0402_5%

2
G
Q48
S
2N7002_SOT23

1
SUSP

R725
2M_0402_5%~D

SUSP#

1
2
3
Q54B
SUSP

2N7002DW-7-F_SOT363-6

Q54A
SYSON#

470_0402_5%
2N7002DW-7-F_SOT363-6

2
6

2
3
5

+RTCVCC

Q53B
SUSP

R723

470_0402_5%
2N7002DW-7-F_SOT363-6

R722

2
6

2
2

Q53A
SUSP

+0.75VS

R721
470_0402_5%
2N7002DW-7-F_SOT363-6

1
R719
1K_0402_5%~D

+1.8V

1
R720
470_0402_5%

D29
BAT54CW_SOT323-3~D

+VCCP

+1.5VS

RTCVREF

+3VS

37,44,46,49

BATT1.1

Q52
SSM3K7002FU_SC70-3

SUSP#

1
1 2
2
G
3

Q51B

R717

SUSP

SUSP

10K_0402_5%

+5VS

C1703
0.01U_0402_25V7K~D

100K_0402_5%
2N7002DW-7-F_SOT363-6
4
3
2

2
6
Q51A

SYSON

R716
2N7002DW-7-F_SOT363-6

SYSON#

2
G
3

R715

R718
470_0402_5%

+5VALW

100K_0402_5%

SYSON

C1183

+5VALW

37,48

+1.5VS_GATE

R712
100K_0402_5%

Q36
S
2N7002_SOT23

C1193

C1185

R724

0.1U_0402_16V4Z~D

1
D13

19,23,47,50 DGPU_PWR_EN

CH751H-40PT_SOD323-2

10U_0805_10V4Z

R714

37,44,46,49 SUSP#

Q50
S PMF3800SN_SC70-3

+1.5VS
U13
SI4800BDY-T1-E3_SO8
8
1
7
2
6
3
5

B+_BIAS
DGPU_PWR_EN#

23 DGPU_PWR_EN#

2
G

1
DGPU_PWR_EN#

+1.5V

2M_0402_5%~D

1
2

1
SI4392DY-T1-E3_SO8~D

C1701
10U_0805_10V4Z~D

3
2
1

C1700
0.1U_0402_16V4Z~D

330K_0402_5%

C1699
10U_0805_10V4Z~D

R711

+1.5V to +1.5VS Transfer

R713
100K_0402_5%

8A

U49
8
7
6
5

10U_0805_10V4Z

+1.5VSDGPU

B+_BIAS
C

+1.5V

SB54392008L EOL, P/N change to SB54800038L

1 2

R726
470_0402_5%
1

2
G

Q56
3

SUSP

C1704
1U_0603_10V4Z

2009/07/25

Issued Date

SSM3K7002FU_SC70-3

Compal Secret Data

Security Classification

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

Compal Electronics, Inc.

DC/DC INTERFACE

Size Document Number

Custom LA-5811P
Date:

Rev
1.0

Tuesday, December 29, 2009

Sheet
1

40

of

58

Power block

Battery OVP

CPU OTP

Page 43

Turn Off
Input
Switch Page 45

DC IN

Page 43

Turn Off
B+
+3VALWP: TDC:5.1A
+5VALWP: TDC:5.8A
TPS51427

CHARGER
CC:0A~3A
CV:12.6V(3cell)
ISL6251AHAZ-T

Always
C

Page 46

+1.8VP: Ipeak:0.42A
RT9025

SUSP#
Page 50

Page 45

Battery

DGPU_PWR_EN

+VGA CORE
TDC:21.525A
TPS51218DSCR

SUSP#

+VCCP:TDC:13.57A
TPS51218DSCR

Page 47

+1.05VCCP:TDC:2.681A
TPS51218DSCR

Page 48

DGPU_PWR_EN
B

+1.5VSP TDC:11.77A
TPS51218DSCR

SYSON

Page 51

Page 49

+0.75VSP: TDC:0A
RT9026
VR_ON

CPU CORE
Ipeak:19A
ISL6261ACRE

+3VALW
Page 50

Page 52

Title

POWER BLOCK DIAGRAM

Size
Date:
5

Document Number

Rev

Tuesday, December 29, 2009

Sheet
1

41

of

58

PD20
PJSOT24C_SOT23-3
@

BATT+

OTP
PH1 under CPU botten side :
CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

CPU

PD21
PJSOT24C_SOT23-3
@

VS

+3VALWP
1
2

Place clsoe to EC pin

BATT_TEMP

37

PR39
10.7K_0402_1%~D

VL
PR40
147K_0402_1%~D
1
2

3S/4S#

44

+3VALWP

VL

OTP_IN+

OTP_IN-

1
1 OTP_OUT
1

MAINPWON

43,45

1SS355TE-17_SOD323-2
PU11A
LM358ADR_SO8

EC_SMB_DA1 37

PC22
1000P_0402_50V7K~D

PR47
150K_0402_1%~D
2

PR219
100_0402_5%~D

PJP31

PH1
100K_0402_1%_NCP15WF104F03RC

PD11
0

PR45
150K_0402_1%~D

PR215
6.49K_0402_1%~D

PR43
61.9K_0402_1%~D
1
2

OTP_IN

1K_0402_5%~D
2
1

1
PR217
3S/4S#

PR41
205K_0402_1%~D

11.BAT+
10.BAT+
9.BAT+
8.ID
7.B/I
6.TS
5.SMD
4.SMC
3.GND
2.GND
1.GND

PC198
0.1U_0402_16V7K~D

SMART
Battery:

MOLEX_87437-1173_11P-T
SP020907230
11
11
10 10
9 9
8
8
7 7
6 6
5 5
4 4
3 3
2 2
1 1

PJP31 battery connector

2 BATT_TEMP
PR213
1K_0402_5%~D

PR212
47K_0402_5%~D
1

PC193
1000P_0402_50V7K~D

PC195
0.01U_0402_25V7K~D

1
1
2

1
2

PC194
100P_0402_50V8J~D

VL
BATT++

PC196
100P_0402_50V8J~D

BATT+

PL14
SMB3025500YA_2P
1

BATT++

PC23
1U_0603_10V6K~D

EC_SMB_CK1 37

PR222
100_0402_5%~D

BATT+

PR223
453K_0402_1%~D

2
PR227
1

+
-

10K_0402_1%~D
PU11B
LM358ADR_SO8

5
6
1

BATT_OVP

37

PR229
86.6K_0402_1%~D

PC203
0.01U_0402_25V7K~D

BATT1.1

1
2

1
2

MOLEX_53261-0271~D
SP020009Z0L

2
1
1

PQ66
2
G

2
2
PR230
1

PJP32

1
1

PC202

B+_BIAS

0.1U_0805_25V7M~D

1SS355TE-17_SOD323-2 PR226
1
2

32.8

PD22

220K_0402_5%

2
PR228
1
PC204
0.1U_0603_25V7K~D
2
1

220K_0402_5%

+5VALW

100_0805_5%~D

470K_0402_5%~D

B+

PQ65
TP0610K-T1-E3_SOT23-3
1

PR224
499K_0402_1%~D

PR225

PC201
0.01U_0402_25V7K~D

COIN RTC Battery

B

VS

RHU002N06_SOT323-3

LI-3S :13.5V----BATT-OVP=1.126V
LI-4S :18V----BATT-OVP=1.5V
BATT-OVP=0.08338*BATT+

Security Classification
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

BATTERY CONN/OTP
Size Document Number
Custom
Date:

Rev

Tuesday, December 29, 2009

Sheet
1

42

of

58

PC1
2200P_0402_50V7K~D

Vin Detector

Min.
17.449
16.813

VS

PC6
1

2
8

PS_ID

@
PD4
SM24_SOT23

PD5
DA204U_SOT323~D

PQ3
MMST3904-7-F_SOT323~D
E

PR21
10K_0402_1%~D

1
1

PR23
1
@

PSID_DISABLE# 37

10K_0402_1%~D

VIN
2

+5VALW
+5VALW

2
B

37

PQ2
FDV301N_NL_SOT23-3~D

2
G

PR13
2.2K_0402_5%~D
1
2

PR17
33_0402_5%~D
1
2

PR22
PR19
15K_0402_1%~D 100K_0402_1%~D
1
2
1
2

PQ5
DTC115EUA_SC70-3

100K_0402_5%~D

PR20
1
1 2

BATT ONLY
Precharge detector
Min.
typ.
Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

44

+3VALW

PR12
1
2
0_0402_5%~D

DOCK_PSID

Precharge detector
Min.
typ.
Max.
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V

100K_0402_5%~D

PR18
1

PR16
1
2
1
2

ACOFF

B+

PQ4
DTC115EUA_SC70-3
37,44

3.3V

ACIN

PR15
1K_1206_5%~D
1
2

+5VALW

RTCVREF

PR14
1K_1206_5%~D
1
2

100K_0402_5%~D

RLS4148_LL34

19,37,38

PR8
10K_0402_5%~D

PD1
RLZ4.3B_LL34

PR10
10K_0402_5%~D
1

ACIN

PACIN

PQ1
TP0610K-T1-E3_SOT23-3
3

LM393DR_SO8

PR11
1K_1206_5%~D
1
2

PD2

PC7
1000P_0402_50V7K~D

PR9
1K_1206_5%~D
1
2

PR4
10K_0402_1%~D
2 ACIN

PU1A

PR5
10K_0402_5%~D
1

N35

N40

PR7
20.5K_0402_1%~D
2
1

1
2

PL2
FBM-L11-160808-601LMT 0603~D
2
1 DOCK_PSID

PR6
22K_0402_1%~D
2

2
N41

ACES_88299-0610

VIN

VIN

PR3
82.5K_0402_1%~D

PC8
0.1U_0402_16V7K~D

1
2

PC5
1000P_0402_50V7K~D

1
2

PC4
100P_0402_50V8J~D

1
2

1
2
3
4
5
6
7
8

1
2
3
4
5
6
GND
GND

PC3
100P_0402_50V8J~D

PJPDC1

PC2
1000P_0402_50V7K~D

VIN
D

PR2
1M_0402_1%~N
1
2

typ.
17.841
17.210

L-->H
H-->L

PL1
FBMJ4516HS720NT_1806~D
1
2

DC_IN_S1

Max.
18.234
17.597

VIN

PR1
56K_0402_5%~D

ADPIN

PD3
DA204U_SOT323~D

0.01U_0402_25V7K~D

PD6
RLS4148_LL34-2

BATT+

B+

PR24
2.2M_0402_5%~D
1

VL
B

PD7
RLS4148_LL34-2

1
2

PC10
0.1U_0603_25V7K~D

PC9
2
1

1
2

TP0610K-T1-E3_SOT23-3

2
1

MAX1615_#SHDN1
2
PR120 0_0402_5%~D

#SHDN

5/3+

MAX1615EUK+_SOT23-5~D

PC15
1U_0805_25V4Z~D

+5VALW

MAX1615_IN

GND

PQ8
DTC115EUA_SC70-3

IN
OUT

PC14
1

VS

PR34
200_0805_5%~D

PU2

PQ7
PR36
RHU002N06_SOT323-3 47K_0402_5%~D
PACIN
2
2
1
G

PR26
68_1206_5%~D

PQ6
N1

RTCVREF

4.7U_0805_6.3V6K~D

1
2

36,39 51ON#

PC13
0.01U_0402_25V7K~D

1
2

1
D

PR32
191K_0402_1%~D

PRG++ 2
1

PR35
34K_0402_1%~D
2
1

PR33
499K_0402_1%~D

RTCVREF

PC11
0.1U_0603_25V7K~D

6
PC12
1000P_0402_50V7K~D

PR31
22K_0402_5%~D
1
2

LM393DR_SO8
PU1B

1
2

RB715F_SOT323-3

P
7

1
3

ACON

PR28
200_0805_5%~D
1
2

PR30
100K_0402_5%~D

42,45 MAINPWON
44

PR29
100K_0402_1%~D
PD8

CHGRTCP

PR27
499K_0402_1%~D

VS

0.22U_0603_25V7K~D

PR25
68_1206_5%~D

Security Classification
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

DCIN/DETECTOR
Size Document Number
Custom
Date:

Rev

Tuesday, December 29, 2009

Sheet
1

43

of

58

Iada=0~3.333A(65W)
ADP_I = 19.5*Iadapter*Rsense

6251VREF 1

PC30
2200P_0402_25V7K~D
2
1

CSIN

20

VCOMP

CSIP

19

9
10

12

VREF

UGATE

CHLIM

BOOT

ACLIM

VDDP

VADJ

LGATE

GND

PGND

18
17
16
15
14
13

2
1

DL_CHG

2 6251VDD

PR81
4.7_0603_5%~D
PC50
4.7U_0805_6.3V6K~D

ISL6251AHAZ-T_QSOP24

PR75
PL4
0.02_2512_1%
4.7UH_PCMC063T-4R7MN_5.5A_20%
CHG 1
1
2
4

PQ24
SI4128DY_SO8

PD17
RB751V-40TE17_SOD323-2

PQ22
SI4128DY_SO8
CSOP

DH_CHG
PR78
PC44
2.2_0603_5%~D
0.1U_0603_25V7K~D
BST_CHG 1
2 BST_CHGA 2
1
6251VDDP

PQ20
RHU002N06_SOT323-3
2 PACIN
G

BATT+

3
PC45
10U_1206_25V6M~D
2 PC461
10U_1206_25V6M~D
2 PC741
10U_1206_25V6M~D
2 PC801
10U_1206_25V6M~D
2
1
PC47
10U_1206_25V6M~D
2
1

ICOMP

PC36
0.1U_0603_25V7K~D

PC38
0.047U_0603_16V7K~D
1
2
PR70
20_0603_5%
2
1
PR71
20_0603_5%
PC40
0.1U_0603_25V7K~D
1
2
PR73
2.2_0603_5%~D
LX_CHG

21

CSOP

PR77
4.7_1206_5%~D

CELLS

PD16
1SS355TE-17_SOD323-2
1
2
D

CSON

1 2

PR69
20_0603_5%
1
2

22

3
2
1

CSON

PHASE

5
6
7
8

EN

ICM

1
PQ18
DTC115EUA_SC70-3

DCIN

VIN

23

5
6
7
8

ACSET ACPRN

24

DCIN

VDD

100K_0402_1%~D

11

PR64
200K_0402_1%~D
1
2

PC49
680P_0402_50V7K~D

3
2
1

ACOFF

ACOFF

37,43

PR80
100K_0402_1%~D

6251aclim

37,40,46,49

PC35
0.1U_0603_25V7K~D
2
1

PQ25
DTC115EUA_SC70-3

PU4

PR72

SUSP#

RB715F_SOT323-3

37

6800P_0402_25V7K~D
2

PC48
0.01U_0402_25V7K~D
2
1

2
G

ACON

ACON

6251_EN

10K_0402_1%~D
2
PR74
0.01U_0402_25V7K~D
100_0402_1%~D
1
2
PC42
1
2
100P_0402_50V8J~D
PQ23
@
6251VREF
RHU002N06_SOT323-3
37
ADP_I
PC43
PR79
1
2
147K_0402_1%~D
0.1U_0402_16V7K~D
2
1
IREF

43

PACIN

43

PR76
22K_0402_5%~D
PACIN 1
2

PC41
1
2

SUSP#

100K_0402_1%~D

PC39
1

6251VDD

PR67

@PC37
@
PC37
680P_0402_50V7K~D
CSON 1
2

3S/4S#

PC29
0.1U_0603_25V7K~D
2
1

2
1

42

PR68
150K_0402_1%~D

2
G

21

VIN

PD14
1SS355TE-17_SOD323-2
ACOFF
1
2

PR63
10K_0402_1%~D

2 FSTCHG
1

PQ19
DTC115EUA_SC70-3

PQ15
DTC115EUA_SC70-3

8
7
6
5

PR60
47K_0402_1%~D
1
2

PD13

1
S PQ21
RHU002N06_SOT323-3

1
3

PQ17
DTC115EUA_SC70-3
D

DCIN

PR62
2

1
2
PC34
0.1U_0402_16V7K~D

PR66
47K_0402_5%~D

PR107
10_1206_5%~D
1
2

PR65
10K_0402_5%~D
2
1

FSTCHG

6251VDD 1
2

CSIP

PC32
5600P_0402_25V7K~D
1
2

PD15
1SS355TE-17_SOD323-2
1

37

P3

1
2
3

CSIN
PC28
10U_1206_25V6M~D
2
1

PC27
10U_1206_25V6M~D
2
1

PQ14
TP0610K-T1-E3_SOT23-3

PR59
200K_0402_1%~D

1
2
3

PC31
0.1U_0603_25V7K~D

1
PR58
47K_0402_1%~D

PQ16
DTA144EUA_SC70-3

8
7
6
5

PQ13
AO4407A_SO8

CHG_B+

1
2
3

1
2
3

8
7
6
5

B+

PR57
0.02_2512_1%

P3

PR61
100K_0402_1%~D
2
1

VIN
D

PQ12
AO4407A_SO8

P2

PC33
2.2U_0603_6.3V6K~D
2
1

PQ11
AO4407A_SO8

PR82
11.5K_0402_1%~D
B

PR83
2.74K_0402_1%~D
2

CP mode
Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05)
Vaclim=2.87*((11.5K//152K)/((2.87K//152K)+(11.5K//152K)))
CHGVADJ

PR84
25.5K_0402_1%~D
1
2

37

CC=3.3A
CHGVADJ

PR85
43.2K_0402_1%~D

CV mode

IREF=1*Icharge
IREF=0.25V~3.3V

0V

3.99V per cell

1.93V

4.2V per cell

3.3V

4.35V per cell

Security Classification
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

CHARGER
Size
Date:

Document Number

Rev

Tuesday, December 29, 2009

Sheet
1

44

of

58

TPS51427_B+

TPS51427_B+
D

PHASE2

PHASE1

LX5

18

DL5

LGATE2

LGATE1

FB3

30

@ PR93
10K_0402_1%~D
32

VL

PGND

OUT1

10

REFIN2
FB1

11

PC197
0.1U_0603_25V7K~D
2
1

PC56
2200P_0402_50V7K~D
2
1

PC55
4.7U_0805_25V6-K~D
2
1

PC54
4.7U_0805_25V6-K~D
2
1

5
6
7
8
3
2
1

22

OUT2

2VREF_TPS51427
PC67
1

16

1
+
2

FB5

PC66
330U_D2E_6.3VM_R25M
PC206
0.1U_0402_10V7K~D
2
1

23

PR92
61.9K_0402_1%~D
1
2

25

DL3

LX3

PC63
0.1U_0603_25V7K~D

17

DH5
PR89 2.2_0603_5%~D
BST5A 2
1

+5VALWP

PL6
1
2
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
PC65
PR91
680P_0402_50V7K~D 4.7_1206_5%~D

PC59
4.7U_0805_6.3V6K~D
2
1
BOOT1

PC62
0.1U_0603_25V7K~D

PQ29

5
6
7
8

VCC

15

SI4894BDY-T1-E3_SO8

BOOT2

19

PC60
1U_0603_10V6K~D
1
2

24

PVCC

UGATE1

UGATE2

LDO

6
VIN

PC58
1U_0603_10V6K~D
3
1
2

2
1
TP

26

1
2
3

1
2

PC64
680P_0402_50V7K~D

DH3
PR88 2.2_0603_5%~D
2
1 BST3A

+
2

PC61
330U_D2E_6.3VM_R25M

PC200
0.1U_0402_10V7K~D
2
1

33

SI4894BDY-T1-E3_SO8

PQ28

PR87
4.7_1206_5%~D
PR90
0_0402_5%~D

PC57
0.1U_0603_25V7K~D

PU5
8
7
6
5

PL5
1
2
2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%

+3VALWP

SI4800BDY-T1-E3_SO8~N

1
2
3

VL

3
2
1

PQ26

SI4800BDY-T1-E3_SO8~N

PQ27
8
7
6
5

PC199
0.1U_0603_25V7K~D
2
1

PC53
2200P_0402_50V7K~D
2
1

JUMP_43X118

PC52
4.7U_0805_25V6-K~D
2
1

PC51
4.7U_0805_25V6-K~D
2
1

1000P_0402_50V7K~D
PC145

1
2

1000P_0402_50V7K~D
PC144
2
1

B+

PR86
0_0805_5%~D
1
2

PJP5
2

PR94
0_0402_5%~D
1
2

REF

0.22U_0603_10V7K~D
8

BYP
SKIP

1
2

GND
21

TON

ILIM2

28
13
12

ILM1

31

ILIM2

POK

37

1
PR100
255K_0402_1%~D

TPS51427_QFN32_5X5

PR104
0_0402_5%~D

+5VALWP
Thermal Design current=5.8A
OCP min=10A
Fsw=400KHZ

@ PC71
@PC71
0.047U_0402_16V7K~D

PR99
267K_0402_1%~D
1

Low Side MOS RDS(on)=13m ohm(Typ) , 16m ohm(Max)

+3.3VALWP
Thermal Design current=5.1A
OCP min=9.46A
Fsw=300KHZ

ILIM1

VL

@ PR96 0_0402_5%~D
1
2
PR108 0_0402_5%~D
1
2 2VREF_TPS51427

PQ30
TP0610K-T1-E3_SOT23-3

EN2

NC

@ PR106
47K_0402_5%~D
1
2

+5VALWP

JUMP_43X118

PR105
0_0402_5%~D
2
1

JUMP_43X118 @
PJP8
1 1
2 2

+5VALW

42,43 MAINPWON

EN1

+3VALWP

POK1

EN_LDO

POK2

@ PR95 0_0402_5%~D
2
1

29

2VREF_TPS514272

JUMP_43X118 @
PJP9
1
2
1
2

2
PR102
0_0402_5%~D

+3VALW

@ PR101
0_0402_5%~D

PR103
806K_0603_1%~D

2VREF_TPS514271

PJP6

VL

NC

JUMP_43X118

27

PC70
.1U_0603_25V7K~D

PC68
0.22U_0603_25V7K~D

4
14

PJP7

PR98
200K_0402_1%~D
1
2

PD19
BAS316_SOD323-2

VS

PR97
100K_0402_1%~D
1
2

PC69
1U_0603_10V6K~D
1
2

20
PD18
RLZ5.1B_LL34-2
1
2

LDOREFIN

Low Side MOS RDS(on)=13m ohm(Typ) , 16m ohm(Max)

Security Classification
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

+5VALWP/+3VALWP
Size Document Number
Custom
Date:

Rev

Tuesday, December 29, 2009

Sheet
1

45

of

58

PJP28
+VCCPP_B+

B+

JUMP_43X118

PC185
10U_1206_25V6M~D
2
1

PC177
10U_1206_25V6M~D
2
1

PC176
10U_1206_25V6M~D
2
1

5
6
7
8
4
BST_VCCPP

PR205
PC178
2.2_0603_5%~D 0.22U_0603_10V7K~D
1
2
1
2
3
2
1

PQ47
SI4172DY-T1-GE3 1N SO8

100K_0402_1%~D
PR204

+3VALW

PC175
0.1U_0603_25V7K~D
2
1

PC174
2200P_0402_50V7K~D
2
1

PU15

LG_VCCPP

TP

TPS51218DSCR_SON10_3X3~D

PQ48

3
2
1

PR209
470K_0402_5%~D

11

+5VALW
1

PR210

PR211

20K_0402_1%~D
1
2

10K_0402_5%~D
2
1

4.7_1206_5%~D

1
+

2
2

680P_0402_50V7K~D

1
+
2

1
+
2

PC412
220U_B2_2.5VM_R15M

+VCCPP

PC183
220U_B2_2.5VM_R15M

V5IN
DRVL

V5IN_VCCPP

PL13
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2

PC182
220U_B2_2.5VM_R15M

RF

SW_VCCPP

PC181
10U_0805_6.3V6M~D

VFB

UG_VCCPP

PC180
0.1U_0402_10V7K~D
2
1

SW

PR208

RF_VCCPP

EN

10

FB_VCCPP

DRVH

VBST

TRIP

EN_VCCPP

PGOOD

PC184

SI7170DP-T1-GE3_POWERPAK8-5~D

TRIP_VCCPP

@ PC106
0.1U_0402_16V7K~D

37,40,44,49 SUSP#

PR207
0_0402_5%~D
1
2

PG_VCCPP

PC179
1U_0603_6.3V6M~D

PR206
69.8K_0402_1%~D
1
2

+VCCPP

PJP29
JUMP_43X118
1
2 2

+VCCP

PJP30
JUMP_43X118
1 1
2 2

+VCCPP
Thermal Design current=13.57A
OCPmin=25.2A
Fsw=290KHZ
Low Side MOS RDS(on)=3.6m ohm(Typ) , 4.5m ohm(Max)

+VCCPP
Security Classification
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Size Document Number

Custom
Date:

Rev

Tuesday, December 29, 2009

Sheet
1

46

of

58

+1.05VSP
Thermal Design current=2.681A
OCPmin=4.979A
Fsw=290KHZ

PJP34
+1.05VSP_B+

B+

PC207
10U_1206_25V6M~D
2
1

PC189
10U_1206_25V6M~D
2
1

PC191
0.1U_0603_25V7K~D
2
1

PC188
2200P_0402_50V7K~D
2
1
D
D
D
D

PQ49
AO4466_SO8

S
S
S

TP

LG_1.05VSP

TPS51218DSCR_SON10_3X3~D

3
2
1
4

4.7_1206_5%~D

1
+

2
2

680P_0402_50V7K~D

1
+
2

3
2
1

PR218
470K_0402_5%~D

11

+1.05VSP

+5VALW
PC419
220U_B2_2.5VM_R15M

V5IN_1.05VSP

PC418
220U_B2_2.5VM_R15M

DRVL

PL15
3.3UH_FDV0630-3R3M_4.3A_20%~D
1
2

PC190
10U_0805_6.3V6M~D

RF

SW_1.05VSP

PC187
0.1U_0402_10V7K~D
2
1

V5IN

UG_1.05VSP

VFB

PR221

SW

EN

10

RF_1.05VSP

DRVH

PC215

FB_1.05VSP

VBST

TRIP

PQ50
AO4710_SO8

EN_1.05VSP

PGOOD

5
6
7
8

TRIP_1.05VSP 2

PC192
1U_0603_6.3V6M~D

PG_1.05VSP

46.4K_0402_1%~D
1
2

4
PR231
PC214
2.2_0603_5%~D 0.22U_0603_10V7K~D
BST_1.05VSP 1
2
1
2

PU17

PR214

@ PC150
0.1U_0402_16V7K~D

100K_0402_1%~D
PR232

+3VALW

19,23,40,50 DGPU_PWR_EN

Low Side MOS RDS(on)=11.7m ohm(Typ) , 14.2m ohm(Max)

PR233
0_0402_5%~D
1
2

JUMP_43X118

5
6
7
8

PR216

PR220

20K_0402_1%~D
1
2

10K_0402_5%~D
2
1

+1.05VSP

PJP35
JUMP_43X118
1
2 2

+1.05VSDGPU

PJP33
JUMP_43X118
1 1
2 2

Security Classification
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Size Document Number

Custom

Rev

+1.05VSP

Date:

Tuesday, December 29, 2009

Sheet
1

47

of

58

+1.5VSP
Thermal Design current=11.77A
OCPmin=21.85A
Fsw=290KHZ
Low Side MOS RDS(on)=3.6m ohm(Typ) , 4.5m ohm(Max)
D

PJP16
+1.5VSP_B+

B+

JUMP_43X118

+1.5V

BST_1.5VSP

LG_1.5VSP

11

TPS51218DSCR_SON10_3X3~D

PR130

PR129
470K_0402_5%~D

PC115
10U_1206_25V6M~D
2
1

+1.5VP

PR128
4.7_1206_5%

PC114
680P_0402_50V7K~D

1
+

2
2

1
+
2

1
+
2

PC420
220U_B2_2.5VM_R15M

+5VALW

PC417
220U_B2_2.5VM_R15M

V5IN_1.5VSP

PC416
220U_B2_2.5VM_R15M

DRVL

PL8
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1
2

PC111
10U_0805_6.3V6M~D

RF

SW_1.5VSP

PC110
0.1U_0402_10V7K~D
2
1

V5IN

UG_1.5VSP

VFB

RF_1.5VSP

SW

EN

10

FB_1.5VSP

DRVH

SIS412DN-T1-GE3_POWERPAK8-5

PQ71
SI7170DP-T1-GE3_POWERPAK8-5~D

VBST

TRIP

3
2
1

EN_1.5VSP

PGOOD

TP

10K_0402_1%~D
1
2

TRIP_1.5VSP

@ PC108
@PC108
0.1U_0402_16V7K~D

PG_1.5VSP

61.9K_0402_1%~D
1
2

SYSON

PR125
PC107
2.2_0603_5%~D 0.22U_0603_10V7K~D
1
2
1
2
4

PU9

PR126

37,40

PC105
10U_1206_25V6M~D
2
1

PQ64

PR127
0_0402_5%~D
1
2

PC103
0.1U_0805_50V7M~D
2
1

@
PR140
0_0402_5%~D

PC109
1U_0603_6.3V6M~D

1
2

@
PC223
0.1U_0402_16V7K~D

PC102
2200P_0402_50V7K~D
2
1

PR139
0_0402_5%~D
1
2

SM_PWROK

100K_0402_1%~D
PR124

PR131
11.5K_0402_1%~D
2
1

+1.5VP

PJP17
JUMP_43X118
1
2 2

+1.5V

PJP18
JUMP_43X118
1 1
2 2

Security Classification
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Title

Deciphered Date

+1.5VSP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Size Document Number

Custom
Date:

Rev

Tuesday, December 29, 2009

Sheet
1

48

of

58

@
PJP20 JUMP_43X118

PU8

RT9025

NC
VOUT

EN

ADJ

VDD

PGOOD

PC154
0.1U_0402_16V7K~D
@

GND

GND
8

PC151
10U_1206_25V6M~D

PC155
10U_1206_25V6M~D
PC152
1U_0402_6.3V6K~D

PC153
0.1U_0402_16V7K~D
@

+5VALW

PR178 0_0402_5%~D

+1.8VP

VIN

PR179
2.37K_0402_1%~D

37,40,44,46 SUSP#

PR180
3.01K_0402_1%~D
2
1

+3VALW

@ PJP21
2

+1.8VP

+1.8V

PAD-OPEN 2x2m~D

+1.8VSP
Imax=0.42A

8
6

GND
VTTREF

1
0_0402_5%~D

PC168
0.1U_0402_16V7K~D
@

SUSP#

PC166
0.1U_0402_16V7K~D
37,40,44,46
2

PR182

S3

1
4

S5

VTTSNS

VTT

+3VALW

PC165
1U_0603_10V6K~D

10

VIN

VLDOIN

PGND

VDDQSNS

GND

10U_0805_10V6K~D
PC163
2
1

10U_0805_10V6K~D
PC169
2
1

+0.75VSP

RT9026_MSOP10
PU14
1

11

JUMP_43X118
@

4.7U_0805_6.3V6K~D

PC164
2
1

+1.5V

PC167
2
1

PJP24
1

4.7U_0805_6.3V6K~D

+0.75VSP
Imax=0A

PJP14
+0.75VSP

2
@

+0.75VS

JUMP_43X118

2009/07/25

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

+1.8VP

/ +0.75VSP

Size Document Number

Custom
Date:

Rev

Tuesday, December 29, 2009

Sheet
1

49

of

58

+VGA_COREP
ThermalDesigncurrent=21.525A
OCPmin=36.9A
Fsw=290KHZ
Low Side MOS RDS(on)=1.8m ohm(Typ) , 2.25m ohm(Max)
+VGA_COREP(N10P_GS1)

PR122=41.2K ohm

+VGA_COREP
GPU_VID0
GPU_VID1

0.85V
1
0

0.8V
0
0

0.9V
1
1

PJP37
+VGA_COREP_B+

B+

JUMP_43X118

19 DGPU_PWROK

PC219
10U_1206_25V6M~D
2
1

PC213
10U_1206_25V6M~D
2
1

PC209
10U_1206_25V6M~D
2
1

PC210
0.1U_0603_25V7K~D
2
1

3
D

PQ70
SI7686DP-T1-E3_SO8

BST_VGA

PQ67
SI7686DP-T1-E3_SO8

3
2

PR242
0_0402_5%~D
1
2

2
PR240
PC216
2.2_0603_5%~D 0.22U_0603_10V7K~D
1
2
1
2

+3VS
100K_0402_1%~D
PR239

@ PC224
0.1U_0402_16V7K~D

PC208
2200P_0402_50V7K~D
2
1

PU16

+
2

1
+
2

1
+
2

PC414
220U_B2_2.5VM_R15M

PC413
220U_B2_2.5VM_R15M

PC221
220U_B2_2.5VM_R15M

PC211
10U_0805_6.3V6M~D

PC186
0.1U_0402_10V7K~D
2
1

PR121
10_0402_1%~D

PC220
220U_B2_2.5VM_R15M

PR238
2.74K_0402_1%~D

1
2

+VGA_COREP

PR237
4.7_1206_5%~D

11

TPS51218DSCR_SON10_3X3~D

PC218
680P_0402_50V7K~D

TP
PR236
470K_0402_5%~D

+5VALW

LG_VGA

V5IN_VGA

PQ69
SI7170DP-T1-GE3

DRVL

SW_VGA

V5IN

RF

VFB

SW

PL16
0.45UH_ETQP4LR45XFC_25A_-25+20%
1
2
3

RF_VGA

DRVH

EN

UG_VGA

FB_VGA

TRIP

10

PQ68
SI7170DP-T1-GE3

VBST

EN_VGA

PGOOD

@ PC112
0.1U_0402_16V7K~D

19,23,40,47 DGPU_PWR_EN

TRIP_VGA

PC212
1U_0603_6.3V6M~D

1
48.7K_0402_1%~D
1
2
PR234

PR241
0_0402_5%~D
1
2

PR119
261_0402_1%~D

@ PJP38
JUMP_43X118
1
2 2

PR235
19.6K_0402_1%~D

PQ33
BSS138W-7-F_SOT323~D

2
1

1
2

1
PR132
10K_0402_5%~D

PC142
0.01U_0402_16V7K~D

2
3

PR122
41.2K_0402_1%~D
2
1

1
D

2
G

PR133
2

@ PR123
10K_0402_5%~D

100K_0402_5%~D

@PC149
@
PC149
820P_0402_50V7K~D
1

1 2
2

PR135

PR137
10K_0402_5%~D

100K_0402_5%~D

PC143
0.01U_0402_16V7K~D

2
PR134
10K_0402_5%~D

+3VS_DELAY

PR136
37.4K_0402_1%~D
1

PR138
0_0402_5%~D
+3VS_DELAY

+NVVDD_SENSE 22

@ PC116
820P_0402_50V7K~D

PQ32
BSS138W-7-F_SOT323~D

2
G

1
A

+VGA_COREP

@ PJP36
JUMP_43X118
1 1
2 2

21

GPU_VID0

GPU_VID1
A

+VGA_CORE

@ PJP39
JUMP_43X118
1 1
2 2

Security Classification
Issued Date

@ PJP40
JUMP_43X118
1
2
1
2

21

Compal Electronics, Inc.

Compal Secret Data

Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

+VGA_COREP

Size Document Number

Custom
Date:

Rev

Tuesday, December 29, 2009

Sheet
1

50

of

58

+VCCP

PR144
0_0402_5%~D
1
2

VDD

NC

22

BOOT_CPU1

UGATE_CPU1

PHASE_CPU1

23

21

1000P_0402_50V7K~D
PC147

1
2

1000P_0402_50V7K~D
PC146
2
1

1
2

1
2

4.7U_0805_25V6-K~D
PC120

1
2

4.7U_0805_25V6-K~D
PC119

4.7U_0805_25V6-K~D
PC121

+VCC_F

1
PR156
7.68K_0805_1%~D
2

2
24

LGATE_CPU1

PR155
4.7_1206_5%~D

+VCC_CORE

PC128
680P_0402_50V7K~D

ISL6261ACRZ-T_QFN40_6X6

20

VSS
19

18

PC129
1000P_0402_50V7K~D

VIN

BOOT
VSUM

FB

27

25

28

26

1000P_0402_50V7K~D
PC118

0.1U_0603_25V7K~D
PC117

PC205
3
D
S

PR153
2.2_0603_5%~D

29

PL11
0.45UH_ETQP4LR45XFC_25A_-25+20%
4
1

PQ62
SI7170DP-T1-GE3-POWERPAK8-5

30

PQ63
SI7686DP-T1-E3_SO8

PC123
0.01U_0402_16V7K~D
2
1

PC124
1U_0603_10V6K~D
2
1

2200P_0402_50V7K~D
2
1

CPU_VID0

CPU_VID1

CPU_VID25

CPU_VID4
37
CPU_VID3
5
31
VID3

32
VID4

VID5

33

2 PR150 1
0_0402_5%~D
35

34
VID6

37

36
DPRSLPVR

38

39

B+

3V3

COMP

11

PR159
6.81K_0402_1%~D

40

UGATE

VW

17

9
10

PHASE

DFB

VSSP

OCSET

15

0.1U_0402_10V7K~D

SOFT

DROOP

7
PR158
10K_0402_1%~D
1
2

LGATE

14

VCCP

NTC

RTN

PC148
2

2 PC127
0.015U_0603_25V7K

VR_TT#

VSEN

VID0

PL10
HCB2012KF-121T50_0805
1
2

VSUM

4.22K_0402_1%~D

H_PROCHOT#
4
470K_0402_5%_TSM0B474J4702RE
5
2

VID2

RBIAS

13

@ PH2
1

PR146
1_0603_5%~D

PC126
0.22U_0603_10V7K~D

VID1

12

@
PR157
1

DPRSTP#

1 FDE
@ PR152 40.2K_0402_1%~D
2 PMON
1
2

PR154 147K_0402_1%~D
1
2

4 H_PROCHOT#

41
GND PAD

PC125
0.1U_0402_16V7K~D

VDIFF

1
2

2
8,19,37 PM_PWROK

@
1

PU10

PGOOD

CLK_EN

PC122

1U_0603_6.3V6M~D

VGATE

PR151
0_0402_5%~D

PR149
1.91K_0402_1%~D

PR171
2
1
0_0402_5%~D
19,37

+CPU_B+

PR148
0_0402_5%~D
1
2

+3VALW

CPU_VID5

H_PROCHOT#

VR_ON

5,8,18 H_DPRSTP#

+5VALW

VR_ON

PR145
0_0402_5%~D
1
2

VO

8,19 PM_DPRSLPVR

CPU_VID6

PR143
68_0402_5%~D

16

PC130
2
1

PR160 464K_0402_1%~D
1
2

150P_0402_50V8J~D
2

1
2

PC131 47P_0402_50V8J~D
PC133
390P_0402_50V7K~D
1
2

PR163
330_0402_1%~D
1
2

PR169
1K_0402_1%~D

PR170
7.87K_0402_1%~D

1
2 2

PC138 330P_0402_50V7K~D
1
2

PR166
3.57K_0402_1%~D

PH3
10KB_0603_5%_ERTJ1VR103J
1

PC137
330P_0402_50V7K~D

VSUM
4.53K_0402_1%~D
2
1

2
PR168
0_0402_5%~D

+CPU_B+

PC134
0.22U_0603_25V7K~D

PC140.068U_0402_10V7K~D
2
1

VSSSENSE

PC136
1000P_0402_50V7K~D

PC139 0.1U_0402_10V7K~D
1
2

2
PR165
0_0402_5%~D

PC135 1000P_0603_50V7K~D
1
2

VCCSENSE

PR164
2.21K_0402_1%~D
1
2

PR162
10_0603_5%~D
2

+5VALW

1
2
PR161
10_0603_5%~D
PC132
1U_0603_10V6K~D

PR167

1
B

+VCC_F
A

PC141
0.22U_0603_10V7K~D

Security Classification
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Title

Deciphered Date

CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Size Document Number

Custom
Date:

Rev

Tuesday, December 29, 2009

Sheet
1

51

of

58

V ersion Change L ist ( P. I. R . L ist )

Item Page#
D

Title

D ate

R equest
O w ner

Page 1

Issue D escription

Solution D escription

R ev.

50

VGA_COREP

8/17

Antony

Change output voltage

Change PR119 from SD02800008L(0 ohm) to SD03426108L(261 ohm)

X00

50

VGA_COREP

8/17

Antony

Change output voltage

Change PR122 from SD03424928L(24.9K ohm) to SD03419128L(19.1K ohm)

X00

50

VGA_COREP

8/17

Antony

Change output voltage

Change PR136 from SD03437428L(37.4K ohm) to SD03440228L(40.2K ohm)

X00

50

VGA_COREP

8/17

Antony

Change output voltage

Change PR238 from SD00000AP8L(2.67K ohm) to SD03427418L(2.74K ohm)

X00

50

VGA_COREP

8/17

Antony

Output voltage setting 0.85V (NVIDIA request)

non-populate PR123(reserve space)

X00

44

CHARGER

9/10

Antony

CP point 90% setting

Change PR83 from 2.87K ohm to 2.74K ohm

X01

44

CHARGER

9/10

Antony

Charger voltage setting

Change PR85 from 200K ohm to 43.2K ohm

X01

Antony

EE required that SM_PWROK should change to +1.5V

Change net name PR124.1 from +3VALW to +1.5V

48

+1.5VSP
9/16

X01

9
50

VGA_COREP

10

9/16

Antony

Change VID time sequence

Change net name PR134.2 and PR123.2 from +3VS to +3VS_DELAY

X01

9/16

Antony

NVIDIA command

interchange with PR121 and PR238

X01

VGA_COREP
50

11

50

VGA_COREP

9/16

Antony

NVIDIA command

Delete PR139, +NVVDD_SENCE connect to PR121.2

X01

12

50

VGA_COREP

9/16

Antony

NVIDIA command

Change PR121 from 0 ohm to 10 ohm

X01

13

50

VGA_COREP

9/24

Antony

NVIDIA command

Change PR121 from 19.1K ohm to 41.2K

14

45

3VALWP/5VALWP

9/24

Antony

follow PSL component

Change PD19 from CH355PT to BAS316

X01

15

51

CPU_CORE

9/24

Antony

follow PSL component

Change PC127 to PSL component

X01

ohm

X01

Compal Electronics, Inc.

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

PWR-PIR1
Size

Document Number

Date:

Tuesday, December 29, 2009

Rev
1.0
Sheet
1

52

of

58

V ersion Change L ist ( P. I. R . L ist )

Item Page#
D

16

46

17

48

18

50

Title

D ate

R equest
O w ner

Page 2

Issue D escription

Solution D escription

R ev.

+VCCPP

9/24

Antony

Change PN to 0 end

Change PQ48 from SB00000FO0L to SB00000FO00

X01

+1.5VP

9/24

Antony

Change PN to 0 end

Change PQ48 from SB00000FO0L to SB00000FO00

X01

VGA_COREP

10/1

Antony

EE required that PU16.1 pull high should change to +3VS

Change net name PR239.1 from +3VALW to +3VS

X01

19

48

+1.5VP

10/5

Antony

EMC request

Reserve PC223 space

X01

20

44

CHARGER

10/5

Antony

Quality enhancement

Reserve PQ22 from AO4466 to SI4128DY

X01

21

44

CHARGER

10/5

Antony

Quality enhancement

Reserve PQ24 from AO4466 to SI4128DY

X01

22

42

BATTERY CONN/OTP

11/13

Antony

OTP meet setting

Change PH1 100K ohm thermestor

X02

23

43

DCIN/DETECTOR

11/13

Antony

Change component size

Change PC9 to size 0603

X03

24

45

+5VALWP/+3VALWP

11/13

Antony

Change component size

Change PC68 to size 0603

X03

25

45

+5VALWP/+3VALWP

11/13

Antony

The quality improvement saggests by PCP

Change PR100

X03

26

48

+1.5VSP

11/13

Antony

Reserve 0 ohm space

Add PR139 0 ohm resistor

to 255K ohm

X03

27

48

+1.5VSP

11/13

Antony

28

50

VGA_COREP

11/13

Antony

Reserve RC space

Add PR242 0 ohm resistor and reserve PC223 space

29

45

+5VALWP/+3VALWP

12/21

Antony

Solve S3/S5 acoustic noise issue

PR96 de-populate

X03

30

45

+5VALWP/+3VALWP

12/21

Antony

Solve S3/S5 acoustic noise issue

Add PR108 0 ohm

X03

31

48

+1.5VSP

12/23

Antony

Reserve CCM mode resistor

Reserve PR140 space

X04

Change component size

Change PQ64 to SIS412DN

X03

X03

Compal Electronics, Inc.

Title

PWR-PIR2

Size

Document Number

Date:

Tuesday, December 29, 2009

Rev
1.0
Sheet
1

53

of

58

Version change list (P.I.R. List)

Item

Date

01

2009/09/07

02

Page 1 of 5

Fixed Issue

Rev.

PG#

Modify List

Enable N11P-GS1 +VGA_COREP when boot system

0.2

19

Mount R238 10K ohm pull high

2009/09/07

U3 pin SM_PWROK schematics error for DDR3

0.2

08

U3 pin SM_PWROK connect to +1.5V

03

2009/09/07

LVDS EDID can't switch select for panel

0.2

28

Modify U20,Q119,Q120 schematics and +LCDVDD change to +3VS

04

2009/09/07

GMCH L_BKLT_CTRL isn't inverted before MUXed 0.2

28

Remove U25 for net DPST_PWM

05

2009/09/07

Switch IC U4 pin1 can not enable

0.2

28

Remove R491 0 ohm and add mount R490 0 ohm

06

2009/09/07

Change HDMI connector

0.2

31

Change connector JHDMI1

07

2009/09/07

Change Display port connector

0.2

32

Change connector JDP1

08

2009/09/10

Change D-SUB connector

0.2

30

Change connector JCRT1

09

2009/09/10

Change SIM,WWAN,WLAN,FAN connector

0.2

33

Change connector JSIM1,JWWAN1,JWLAN1,JFAN1

10

2009/09/10

Change BTB connector

0.2

36

Change connector JBTB1

11

2009/09/10

Q26 footprint error

0.2

29

Change Q26 footprint

12

2009/09/10

Audio board move IHDA signal 33ohm to MB

0.2

18

Add R8,R46,R119,R120 33ohm

13

2009/09/16

LID switch move to audio board

0.2

36

Delete U2,C2,C3,R5

14

2009/09/16

Audio board ALC665 pin9 need +1.5VS

0.2

36

Change JBTB1 pin5,pin7,pin9 to +1.5VS

15

2009/09/17

Add +3VALW for ELC function LED power

0.2

36

Change JBTB1 pin8,pin10,pin12 to +3VALW

16

2009/09/17

LID SW move from MB to audio board

0.2

36

Change JBTB1 pin6 to LID_SW#

17

2009/09/17

Modify ELC schematics fllow DELL design

0.2

38

Modify ELC schematics

18

2009/09/17

Change D16,D25,D26,D31 to PJDLC05C for EMI

0.2

29

Change BOM D16,D25,D26,D31 to SCA00001100

19

2009/09/17

DGPU +3VS_DELAY

0.2

21

Modify Q21 schematics

20

2009/09/18

Change R681 to 33ohm for EMI request

0.2

35

Change BOM R681 from 22ohm to 33ohm

21

2009/09/18

BOM mount L39,L40,L41,L42 for EMI request

0.2

31

Change BOM R579,R580,R581,R588,R591,R592,R595,R596 to @

22

2009/09/22

JP3 pin6,pin7(I2C) add PJDLC05C for EMI

0.2

38

Add D30 to JP3 pin6 and pin7

23

2009/09/22

Add 0.1uF to SM_PWROK for EMI request

0.2

08

Add C190 0.1uF

24

2009/09/22

Modify JLAN1 GND for vender request for EMI

0.2

34

Add C1162,C1163 0.1uF

25

2009/09/22

For JMicro vender request

0.2

35

C1685 4.7uF near +3V_MCVCC

26

2009/09/22

DGPU +3VS_DELAY

0.2

21

Add Q58 and R389 to net VGA_CLKREQ#_R

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

HW Changed-List History-1

Size

Document Number

Rev
1.0

LA-5811P
Date:

Tuesday, December 29, 2009

Sheet
1

54

of

58

Version change list (P.I.R. List)

Item

Date

27

2009/09/23

28

Page 2 of 5

Fixed Issue

Rev.

PG#

Modify List

Modify screw H12,H13,H17 for ME request

0.2

39

Modify screw H12,H13,H17

2009/09/23

Add +5VS for LED board power budget

0.2

39

Change JP3 pin9 from GND to +5VS

29

2009/09/23

Add 1000pF for EMI request

0.2

14

Add C115 1000pF

30

2009/09/23

Add 1000pF for EMI request

0.2

15

Add C196 1000pF

31

2009/09/24

Add o.1uF on PCIE CLK for vender request

0.2

34

Add C1705,C1706 0.1uF

32

2009/09/24

Add 33ohm and 22pF for EMI request

0.2

35

Add 33ohm and 22pF to JCARD1 pin7,pin16

33

2009/09/24

Change crystal X1 cap. to 27pF

0.2

37

Change BOM C1616,C1617 from 15pF to 27pF(SE071270J8L)

34

2009/09/28

Modify USB powershre schematics

0.2

36

Move L43,R617,R618 near JUSB1

35

2009/09/28

Use the USB detect method for powershare

0.2

36

BOM need

36

2009/09/28

For CLKRUN# issue

0.2

37

Add U39 pin38 net PM_CLKRUN#

37

2009/09/28

Net SM_PWROK add 0.1uF near PU9 for EMC

0.2

48

Net SM_PWROK add C198 0.1uF

38

2009/09/28

Net SM_PWROK add 0.1uF near U3B for EMC

0.2

08

Net SM_PWROK add C190 0.1uF

39

2009/09/29

For RF request add 47pF for WLAN,WWAN +1.5VS 0.2

33

Add C1136,C1184 47pF to +1.5VS

40

2009/09/29

Intel request delete R27,R28,R29 for layout

0.2

05

Delete R27,R28,R29

41

2009/09/29

Add JLVDS1 connector detect pin

0.2

29

Add JLVDS1 pin32 LVDS_CONN,pin33 STATUS_BOARD_CONN

42

2009/09/30

Add JBTB1 connector detect pin

0.2

36

Add JBTB1 ppin33 IO_BOARD_CONN

43

2009/09/30

Add JP3 connector detect pin

0.2

38

Add JP3 pin15 STATUS_BOARD_CONN,pin16 IO_BOARD_CONN

44

2009/09/30

EC add JLVDS1,JBTB1,JP3 connector detect pin 0.2

37

Add LVDS_CONN to U39 pin18

45

2009/10/01

Add display port AUX schematics

0.2

32

Add Q123,Q124,Q125,R602,R603,R613,R614

46

2009/10/01

Add a FET for CPU overclocking

0.2

06

U39 pin25 add a net EC_FSB_SEL

47

2009/10/05

Add I2CB,I2CH pull high for NVIDIA request

0.2

15

Add R420,R421,R422,R423 pull high to +3VS_DELAY

48

2009/10/06

For Intel request change C1702 BOM

0.2

40

Change C1702 from 0.01uF to 0.1uF

49

2009/10/06

Change BOM error

0.2

23

Change C191,C192,C197,C261,C262,C263 from SE00000JM00 to SE00000MM1M

50

2009/10/08

Change Q35 Id to 300mA

0.2

23

Change Q35 from SB000008J00 to SB000003P10

51

2009/11/05

Change USB D+ and D-

0.3

36

Swap L43 USB signal USBP2_D-_C and USBP2_D+_C

52

2009/11/05

Change location R263 to C271

0.3

19

Change location R263 to C271 for layout.

mount U60,D52,D58

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

HW Changed-List History-2

Size

Document Number

Rev
1.0

LA-5811P
Date:

Tuesday, December 29, 2009

Sheet
1

55

of

58

Version change list (P.I.R. List)

Item

Date

53

2009/11/05

54

Page 3 of 5

Fixed Issue

Rev.

PG#

Modify List

Add 100K pull low for EC debug request

0.3

33

Add JWWAN1 pin49 R657 100K pull low to GND for net EC_TX

2009/11/05

Change BIOS ROM part to another PN

0.3

37

Change U41 BOM from SA00001IT0L to SA00002TO0L

55

2009/11/09

Change C189,C195,C202 BOM

0.3

23

Change C189,C195,C202 PN from SE00000IS0A to SE076104K80

56

2009/11/09

Change C1105 BOM

0.3

36

Change C1105 PN from SE000000GK0 to SE00000GC0L

57

2009/11/09

Change C191,C192,C197,C261,C262,C263 BOM

0.3

23

Change C191,C192,C197,C261,C262,C263 PN from SE00000MM1M to SE076473K8L

58

2009/11/10

Add 10K pull high for LAN LED leakage

0.3

34

Add R662,R664 10K pull high to +3V_LAN

59

2009/11/10

Reserved 10K pull high for LID_SW#

0.3

37

Add R665 10K pull high to +3VALW

60

2009/11/10

Modify board ID

0.3

37

Mount R622 100K,R627 20K

61

2009/11/10

Modify U4 pin13,pin14

0.3

16

change R142,R352 to 22ohm,1%

62

2009/11/11

Reserved GPIO49 for DGPU_PWR_EN

0.3

19

Add R263,R268 0 ohm to net DGPU_PWR_EN

63

2009/11/11

For ESD request change D30 PN

0.3

38

Change D30 PN from SCA00001100 to SCA00000200

64

2009/11/12

Change R500 to 110ohm for LCD panel EA

0.3

29

Change R500 from 300ohm to 110ohm

65

2009/11/16

Modify JTP1 footprint for layout

0.3

39

Modify JTP1 footprint

66

2009/11/17

Add a 0603 size 0ohm for LVDS SW thermal

0.3

28

U19 pin 57 add a R329 0ohm to GND

67

2009/11/17

Reserved a jump for HDD 3.3V

0.3

32

Add a J3 to +3VS and C1628,C1634

68

2009/11/17

Change U42 pin8 from +5VS to +5VALW

0.3

38

Change U42 pin8 to +5VALW

69

2009/11/18

Reserved 0.1uF,22P for U42 pin6

0.3

38

Add R139,C1843,C313 to U42 pin6

70

2009/11/20

Net VGA_CLKREQ#_R

0.3

21

BOM delete R406 10K ohm

71

2009/11/20

Change Q35 to AO3414 for +1.8VSDGPU 300mA

0.3

23

Change BOM Q35 from SB000003P10 to SB000007600

72

2009/11/20

Change Q11 to SI7121DN for +3VS_DELAY 1380mA 0.3

23

Change Q11 from SB923010020 to SB00000KI00

73

2009/11/20

U42 reserved 0.1uF for RF request.

0.3

38

Add C1857,C1858,C1859,C1860,C1861,C1862,C1863,C1864,C1865,C1866,C1867 0.1uF

74

2009/11/20

Change BOM error.

0.3

40

Change C1702 from 0.1uF to 0.01uF

75

2009/12/16

Modify board ID

1.0

37

Mount R628 37.4K and delete R627 20K

76

2009/12/16

Change DGPU_PWR_EN from GPIO18 to GPIO49

1.0

19

BOM mount R268 0 ohm and delete R263 0 ohm

77

2009/12/16

For DGPU thermal error modify power sequence 1.0

23

BOM mount R210,C207 and change R118 to 68K,C168 to 0.22uF

78

2009/12/16

For nVIDIA request change R571,R568 value

1.0

31

Change BOM R571,R568 from 10K(SD028100280) to 2.2K(SD028220180) or 4.7K

pull H to +3VS_DELAY

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

HW Changed-List History-3

Size

Document Number

Rev
1.0

LA-5811P
Date:

Wednesday, December 30, 2009

Sheet
1

56

of

58

Version change list (P.I.R. List)

Item
103

Date

2009/12/28

Fixed Issue

Change BOM for DELL

Page 5 of 5

Rev.

PG#

1.0

23

Modify List

Change C1664,C1694,C179,C245,C252,C492,C1564,C1693

104

2009/12/28

105

2009/12/28

106

2009/12/28

107

2009/12/28

108

2009/12/28

109

2009/12/28

110

2009/12/28

111

2009/12/28

112

2009/12/28

Change BOM for DELL

Change BOM for DELL
Change BOM for DELL
Change BOM for DELL
Change BOM for DELL
Change BOM for DELL

Change BOM for DELL

Change BOM for DELL

Change BOM for RF team request

from SC1H751H01L to SC1SS355010

1.0

11

Change C90 from SE000005T80 to SE000005T8L

1.0

11

Change C93 from SE000008L80 to SE000008L0L

1.0

11

Change C1117,C1142,C86 from SE049225Z80 to SE049225Z8L

1.0

34

Change C1654 from SE067102K80 to SE067102K8L

1.0

20

Change C286,C288,C289,C290,C293,C304 from SE070104Z80 to SE070104Z8L

1.0

08

Change C1514,C1519,C1528,C1532,C210,C211,C215,C232,C237 ,C241,C72,C74

from SE075103K80 to SE068103K8L
C

1.0

40

Change C1696,C1697 from SE075103ZN0 to SE068103K8L

1.0

07

Change C56,C57,C58 from SGA20221D40 to SGA20221E8L

1.0

29

Change C231,C238 from SE07150AC00 to SE07122AC8L

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

HW Changed-List History-5

Size

Document Number

Rev
1.0

LA-5811P
Date:

Wednesday, December 30, 2009

Sheet
1

56

of

58

Version change list (P.I.R. List)

Item

Date

79

2009/12/16

80

Page 4 of 5

Fixed Issue

Rev.

PG#

Modify List

Change L52 part number

1.0

23

Change BOM L52 from SHI00006N0L to SHI00005V0L

2009/12/17

Change Q11 Compal PN

1.0

23

Change Q11 from SB00000KI00 to SB00000MK00

81

2009/12/18

Change L39,L40,L41,L42 PN for EMI

1.0

31

Change L39,L40,L41,L42 from SM070000K00 to SM070000I00

82

2009/12/20

Change C1616,C1617 to 18PF

1.0

37

Change C1616,C1617 from SE071270J8L to SE071180J80

83

2009/12/20

Change BOM for cost

1.0

11

Change C5,C84,C146 from SGA19331D10 to SGA00002680

84

2009/12/20

Change BOM for cost

1.0

12

Change C153 from SE124474KT0 to SE124474K80

85

2009/12/20

Change BOM for cost

1.0

12

Change C153 from SE000000GK0 to SE000003H00

86

2009/12/21

Change BOM for DELL

1.0

23

Change C179,C245,C252,C492,C1664,C1693,C1694

87

2009/12/21

88

2009/12/22

Change BOM for DELL

Change BOM for DELL

Change BOM for DELL

from SE000000I10 to SE00000110L

C

1.0

11

Change C93 from SE000008L80 to SE000008L0L

1.0

23

Change C72,C74,C210,C211,C215,C232,C237,C241,C258,C1514,C1519,C1528,C1532

1.0

from SE075103K80 to SE068103K8L

1.0

40

Change C1696,C1697 from SE075103ZN0 to SE068103K8L

1.0

07

Change C56,C57,C58 from SGA20221D40 to SGA20221E8L

Change LVDS switch IC

1.0

28

Change U19 from SA00001RM0L to SA00003O900

2009/12/22

Modify BOM for cost

1.0

32

BOM @ C1628,C1634

93

2009/12/22

Modify JKB1 footprint for 2nd source DFX

1.0

37

Modify JKB1 LTCX0020V0L footprint to TYCO_2-2041084-5_25P-T

94

2009/12/23

Change BOM for DELL

1.0

17

Change U10 from SA007080B9L to SA007080B90

95

2009/12/23

1.0

29

Change Q23,Q34,Q36,Q59 from SB000008J00 to SB570020110

96

2009/12/23

1.0

23

Change Q10,Q12,Q46,Q47,Q52,Q56 from SB000009610 to SB00000960L

97

2009/12/28

1.0

28

Change Q119,Q120,Q21,Q29,Q30 from SB00000AR00 to SB57002528L

98

2009/12/28

1.0

19

Change Q8,Q9 from SB502060000 to SB50206008L

99

2009/12/28

1.0

29

Change Q28,Q58 from SB570020020 to SB57002008L

100

2009/12/28

1.0

29

Change Q26 from SB570020400 to SB57002041L

101

2009/12/28

1.0

40

Change Q51,Q53,Q54 from SB570025280 to SB57002528L

102

2009/12/28

1.0

11

Change D1,D13,D15,D5,D6 from SC1H751H01L to SC1SS355010

89

2009/12/22

90

2009/12/22

91

2009/12/22

92

Change BOM for DELL

Change BOM for DELL

Change BOM for DELL
Change BOM for DELL
Change BOM for DELL
Change BOM for DELL
Change BOM for DELL
Change BOM for DELL
Change BOM for DELL

Compal Secret Data

Security Classification
2009/07/25

Issued Date

2010/07/25

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

HW Changed-List History-4

Size

Document Number

Rev
1.0

LA-5811P
Date:

Wednesday, December 30, 2009

Sheet
1

57

of

58

NAP00 Power On Sequence

XDP_DBRESET#
(From Power Button)

ON/OFFBTN#

(to EC)

PBTN_OUT#

1.03s

(From EC to ICH)

SLP_S5# (From ICH to EC)

1.01s

SLP_S3# (From ICH to EC)

90.8us

SYSON (From EC to control +1.5V)

156ms

+1.5V

984us
47.2ms

+V_DDR3_DIMM_REF
SUSP# (From EC to control VS Power)

DGPU Power Sequence

+3VS_DELAY

186ms

+5VS

2.6ms

+3VS

2.87ms

+VGA_CORE
+1.8VSDGPU
+1.5VS_DGPU

DGPU_PWR_EN

(From ICH to control DGPU Power)

108ms

+3VS_DELAY

4.52us

+VGA_CORE
ONLY FOR DGPU

940us

+1.8VSDGPU

6.9ms

+1.5VS_DGPU

6.98ms

+1.05VSDGPU

980us

(can ramp up anytime)

PEG_RST#

1.2ms

+1.8V

1.33ms

+1.5VS

768us
B

+0.75VS

15.8us

+VCCP

980us

EN_WOL#

5.26ms

500us

+3V_LAN
VR_ON (From EC to IMVP)

58.8ms
568us

+VCC_CORE
VGATE (From IMVP to ICH & EC)

7.6ms

PM_PWROK (From EC to ICH)

A

40.7ms

PLT_RST#_BUFF (From ICH to CPU)

1.18ms

H_RESET# (Output from CPU)

1ms

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/07/25

Deciphered Date

2010/07/25

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Power Sequence
Size Document Number
Custom
Date:

Rev
1.0

LA-5811P

Tuesday, December 29, 2009

Sheet
1

58

of

58