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Features
Low Symmetrical Output Resistance, Typically 100 at VDD = 15V Built-In Low-Power RC Oscillator Oscillator Frequency Range . . . . . . . . . . DC to 100kHz External Clock (Applied to Pin 3) can be Used Instead of Oscillator Operates as 2N Frequency Divider or as a SingleTransition Timer Q/Q Select Provides Output Logic Level Flexibility AUTO or MASTER RESET Disables Oscillator During Reset to Reduce Power Dissipation Operates With Very Slow Clock Rise and Fall Times Capable of Driving Six Low Power TTL Loads, Three Low-Power Schottky Loads, or Six HTL Loads Over the Rated Temperature Range Symmetrical Output Characteristics 100% Tested for Quiescent Current at 20V 5V, 10V, and 15V Parametric Ratings Meets All Requirements of JEDEC Standard No. 13B, Standard Specications for Description of B Series CMOS Devices
[ /Title (CD45 41B) /Subject (CMO S Programmable Timer High Voltage Types (20V Rating)) /Autho r () /Keywords (Harris Semiconductor, CD400 0, metal gate, CMOS , pdip, cerdip, mil, military, mil
Ordering Information
PART NUMBER CD4541BF CD4541BE CD4541BH CD4541BM TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld PDIP Chip 14 Ld SOIC PKG. NO. F14.3 E14.3 M14.15
Pinout
CD4541B (CERDIP, PDIP, SOIC) TOP VIEW
RTC 1 CTC 2 RS 3 NC 4 AUTO RESET 5 MASTER RESET 6 VSS 7 14 VDD 13 B 12 A 11 NC 10 MODE 9 Q/Q SELECT 8 OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
File Number
1378.1
A B
R N P 1 OF 3 MUX 216 OR 28 8 Q
N P 3
Q/Q SELECT
RS
2
CTC RTC
1
VDD
AUTO RESET
VSS
MANUAL RESET
FIGURE 1. FREQUENCY SELECTION TABLE A 0 0 1 1 B 0 1 0 1 NO. OF STAGES N 13 10 8 16 TRUTH TABLE STATE PIN 5 6 9 10 0 Auto Reset On Master Reset Off Output Initially Low After Reset (Q) Single Transition Mode 1 Auto Reset Disable Master Reset On Output Initially High After Reset (Q) Recycle Mode FIGURE 2. RC OSCILLATOR CIRCUIT
RTC 1
CD4541B
Absolute Maximum Ratings
DC Supply - Voltage Range, VDD Voltages Referenced to VSS Terminal . . . . . . . . . . -0.5V to +20V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . 10mA Device Dissipation Per Output Transistor For TA = Full Package Temperature Range (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A CERDIP Package . . . . . . . . . . . . . . . . 90 36 SOIC Package . . . . . . . . . . . . . . . . . . . 120 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range (TSTG) . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) At Distance 1/16in 1/32in (1.59mm 0.79mm) from case for 10s Maximum . . . . . . . . . . . . . . . . . . . . . . . . 265oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range TA . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range For TA = Full Package Temperature Range . . . . . 3V (Min), 18V (Typ)
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specications
CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC) 25 PARAMETER Quiescent Device Current, (Note 2) IDD (Max) VO (V) Output Low (Sink) Current lOL (Min) 0.4 0.5 1.5 Output High (Source) Current, IOH (Min) 4.6 2.5 9.5 13.5 Output Voltage: Low-Level, VOL (Max) Output Voltage: High-Level, VOH (Min) Input Low Voltage, VIL (Max) 0.5, 4.5 1, 9 1.5, 13.5 VIN (V) 0, 5 0, 10 0, 15 0, 20 0, 5 0, 10 0, 15 0, 5 0, 5 0, 10 0, 15 0, 5 0, 10 0, 15 0, 5 0, 10 0, 15 VDD (V) 5 10 15 20 5 10 15 5 5 10 15 5 10 15 5 10 15 5 10 15 -55 5 10 20 100 1.9 5 12.6 -1.9 -6.2 -5 -12.6 -40 5 10 20 100 1.85 4.8 12 -1.85 -6 -4.8 -12 85 150 300 600 3000 1.26 3.3 8.4 -1.26 -4.1 -3.3 -8.4 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3 4 125 150 300 600 3000 1.08 2.8 7.2 -1.08 -3 -2.8 -7.2 MIN 1.55 4 10 -1.55 -5 -4 -10 4.95 9.95 14.95 TYP 0.04 0.04 0.04 0.08 3.1 8 20 -3.1 -10 -8 -20 0 0 0 5 10 15 MAX 5 10 20 100 0.05 0.05 0.05 1.5 3 4 UNITS A A A A A A A mA mA mA mA mA mA mA mA mA mA V V V
CD4541B
Electrical Specications
(Continued) CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC) 25 PARAMETER Input High Voltage, VIH (Min) VO (V) 0.5, 4.5 1, 9 1.5, 13.5 Input Current, lIN (Max) NOTE: 2. With AUTO RESET enabled, additional current drain at 25oC is: 7A (Typ), 200A (Max) at 5V; 30A (Typ), 350A (Max) at 10V; 80A (Typ), 500A (Max) at 15V VIN (V) 0, 18 VDD (V) 5 10 15 18 -55 0.1 0.1 -40 85 3.5 7 11 1 1 125 MIN 3.5 7 11 TYP 10-5 MAX 0.1 UNITS V V V A
TA = 25oC, Input tr , tf = 20ns, CL = 50pF, RL = 200k VDD (V) 5 10 15 MIN 900 300 225 TYP 3.5 1.25 0.9 6.0 3.5 2.5 100 50 40 180 90 65 300 100 85 1.5 4 6 Unlimited MAX 10.5 3.8 2.9 18 10 7.5 200 100 80 360 180 130 UNITS s s s s s s ns ns ns ns ns ns ns ns ns MHz MHz MHz s
5 10 15
Transition Time
tTHL
5 10 15
tTHL
5 10 15
5 10 15
fCL
5 10 15
tr , tf
5, 10, 15
NOTE: Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). FIGURE 4. DIMENSIONS AND PAD LAYOUT FOR CD4541B
-C-
A2 B B1 C D D1 E E1 e eA eB L N
eA eC
C
C A B S
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
2.93
eA
c1 D E e eA eA/2 L Q S1
e
D S
eA/2
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturers identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
A1 B C D E
A1 0.10(0.004) C
e
B 0.25(0.010) M C A M B S
e H h L N
NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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