T-Spice12 Examples Guide 1

T-Spice Examples GuideContents
1 2 Introduction Circuit Analysis Examples 3 5

The T-Spice Pro Circuit Simulation System . . . . . . . . . . . . . . . . . . . . 3
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Example 1: DC Operating Point Analysis . . . . . . . . . . . . . . . . . . . . . . . . 6 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

SPICE Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Export the Netlist to T-Spice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Run the Simulation In T-Spice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Open the Output File ..................................... 9
Example 2: DC Transfer Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Example 3: Transient Analysis: Inverter . . . . . . . . . . . . . . . . . . . . . . . . 13 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Example 4: AC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Example 5: Subcircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Example 6: Transient Analysis: CMOS D-Latch . . . . . . . . . . . . . . . . . . 21 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Example 7: Transient Analysis, Powerup Mode . . . . . . . . . . . . . . . . . . 24 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Example 8: Transient Analysis, Preview Mode. . . . . . . . . . . . . . . . . . . 27 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Example 9: Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Example 10: Table Model Evaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . 32 T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Example 11: Transistor Subthreshold Behavior . . . . . . . . . . . . . . . . . 33 T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Example 12: MOS Transconductance Amplifier. . . . . . . . . . . . . . . . . . 36
T-Spice12 Examples Guide
T-Spice Examples GuideContents

(Continued)
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T-Spice Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wide-Band GaAs IC Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Controlled Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .
36 36 37 38 38 39
Index Credits
40 47
T-Spice12 Examples Guide
Introduction
The T-Spice Pro Circuit Simulation System

T-Spice Pro is a complete circuit design and analysis system that includes: S-Edit schematic editor. S-Edit is a powerful design capture and analysis package that can generate netlists directly usable in T-Spice simulations. T-Spice circuit simulator. T-Spice performs fast and accurate simulation of analog and mixed analog/digital circuits. The simulator can analyze large, complex designs with hundreds of thousands of circuit elements. Included within T-Spice is the Advanced Model Package. The T-Spice Advanced Model Package includes the latest and best device models available, to help you get the most realistic simulation results possible. The Advanced Model Package also includes coupled line models and support for user-defined device models via tables or C functions. W-Edit waveform viewer. W-Edit displays T-Spice simulation output waveforms as they are being generated during simulation. The design cycle for the development of electronic circuits includes an important pre-fabrication verification phase. Because of the expense and time pressures associated with the fabrication step, accurate verification is crucial to an efficient design process. The role of T-Spice is to help design and verify a circuits operation by numerically solving the differential equations describing the circuit. T-Spice simulation results allow circuit designers to verify and fine-tune designs before submitting them for fabrication. T-Spice is in many ways like the industry-standard SPICE simulation program: Input language. T-Spice uses an extended version of SPICEs input language. Analysis modes. T-Spice performs the same basic analyses as does SPICE (DC, AC, transient, and noise). Device models. T-Spice incorporates all of SPICEs device models, and more: resistors, capacitors, inductors, mutual inductors, single and coupled transmission lines, current sources, voltage sources, controlled sources, and a full complement of semiconductor device models for p-n diodes, BJTs, JFETs, MESFETs, and MOSFETs. T-Spice also incorporates numerous innovations and improvements not found in other SPICE and SPICE-compatible simulators: Speed. T-Spice provides highly optimized code for evaluating device models, formulating the systems of linear equations, and solving those systems. In addition to the standard direct model evaluation, T-Spice also provides the option of table-base transistor model evaluation, in which the results of device model evaluations are stored in tables and reused. Because evaluation of device models can be computationally expensive, this technique can yield dramatic simulation speed increases. Convergence. T-Spice uses advanced mathematical methods to achieve superior numerical stability. Large circuits and feedback circuits, impossible to analyze with other SPICE products, can be simulated in T-Spice.
T-Spice 12 Examples Guide
Chapter 1: Introduction
The T-Spice Pro Circuit Simulation System
Accuracy. T-Spice uses very accurate numerical methods and charge conservation to achieve superior simulation accuracy. Advanced models. T-Spice incorporates the latest and best transmission-line and semiconductor device models to give you simulation results which are closer to real-world behavior, including the latest Berkeley, Philips Labs, and MOSFET. Macromodeling. T-Spice simulates circuits containing black box macrodevices. A macrodevice can directly use experimental data as its device model. Macrodevices can also represent complex devices, such as logic gates, for which only the overall transfer characteristics are of interest. Input language extensions. The T-Spice input language is an enriched version of the standard SPICE language. It contains many enhancements, including parameters, algebraic expressions, and a powerful bit and bus input wave specification syntax. External model interface. Users can develop custom device models using C or C++. Runtime waveform viewing. The W-Edit waveform viewer displays graphical results during simulation. T-Spice analysis results for voltages, currents, charges, and power can be written to single or multiple files. T-Spice maintains compatibility with traditional circuit simulation tools, while using the best available simulation technology to deliver results as quickly and accurately as possible.
Circuit Analysis Examples
Overview
This collection of examples provides a hands-on introduction to the integrated components of the T-Spice Pro circuit analysis suite. The most common types of analysis and simulation features will be demonstrated, including: DC operating point computations DC transfer sweeps Transient analysis AC and noise analysis Direct versus table-based model evaluation
Chapter 2: Circuit Analysis Examples
Example 1: DC Operating Point Analysis

DC operating point analysis finds a circuits steady-state condition, obtained (in principle) after the input voltages have been applied for an infinite amount of time. Schematic T-Spice Input Output
inverter_op inverter_op.sp inverter_op.out
Schematic
This CMOS inverter is also used in Example 2: DC Transfer Analysis, Example 3: Transient Analysis: Inverter, and Example 10: Table Model Evaluation. Each of the components visible in the schematic has properties associated with it. Properties are textual elements, created in S-Edit, that are attached to an object and provide key information about its design and simulation commands in T-Spice. For example, the physical dimensions of the component M1 are defined by the properties:
L = 5U W = 8U M1 is an instance of the symbol MOSFET_N, which represents an n-channel MOSFET transistor. Propertiess that describe the operation of a generic n-channel MOSFET are defined at the symbol level. Properties specific to component M1, such as length and width, are defined when M1 is created. Property values defined at the component level take precedence over default (symbol) values.
SPICE Simulation Setup

Prior to running the T-Spice simulation, the analysis commands and all processing options need to be established. This is accomplished through the Setup SPICE Simulation dialog.
Ensure that you are viewing the top level schematic. For this example, the top level cell is named inverter. Double clicking inverter in the Library Navigator window will open the proper schematic. Press the Setup Simulation toolbar icon to launch the Setup SPICE Simulation dialog. For the inverter_op example, the proper simulation settings have already been established for you. Note that the DC Operating Point Analysis box is checked. Also note the settings in the General options for File Search Path and Include file.
Export the Netlist to T-Spice

In the inverter_op schematic, use Tools > Design Checks to execute the Design Checker. The Design Checker will display any violation or errors in the Command window. If the file inverter_op is unaltered, there should not be any errors. Press the T-Spice icon ( ) to export a T-Spice netlist file named inverter_op.sp. S-Edit will launch T-Spice with the inverter_op.sp netlist open.
T-Spice Input
********* Simulation Settings - General section ********* .option search="C:\S-Edit v12\Examples\models" .include "ml2_125.md" ********* Simulation Settings - Parameters and SPICE Options ********* m1n out in Gnd Gnd nmos L=5u W=8u Vdd Vdd Gnd 3 m1p out in Vdd Vdd pmos L=5u W=12u c2 out Gnd 800f
vin in Gnd 1 ********* Simulation Settings - Analysis section ********* .op .end
Two transistors, M1N and M1P, are defined in inverter_op.sp. These are MOSFETs, as indicated by the key letter M that begins their names. Following each transistor name are the names of its terminals in the required order: draingatesourcebulk. Then the model name (nmos or pmos in this example) and physical characteristics, such as length and width, are specified. A capacitor C1 (signified by the key letter C) connects nodes OUT and GND with a capacitance of 800 femtofarads. (Strictly speaking, the capacitor could be omitted from the circuit for this example, since it does not affect the DC operation of the inverter.) Two DC voltage sources are defined: VDD, which sets node VDD to 3.0 volts relative to system ground, and VIN, which sets node IN to 1.0 volt relative to ground. Notice that the simulation settings which were entered in the SPICE Simulation Setup dialog resulted in .option, .include, and .op commands being written to the T-Spice input file. The .INCLUDE command causes T-Spice to read the contents of the model file ml2_125.md for the evaluation of transistors M1 and M2, and the search option identifies the path to the include (.include ...) and library (.lib ...) files. In this case, the model file contains two .model commands, describing MOSFET models nmos and pmos:
.model nmos nmos + Level=2 + Nsub=1.066E+16 + Gamma=.639243 + Uexp=4.612355E-2 + Vmax=177269 + Nfs=4.55168E+12 + Tpg=1.000 + Cgdo=2.89E-10 + Cjsw=1.74E-10 .model pmos pmos + Level=2 + Nsub=6.575441E+16 + Gamma=0.618101 + Uexp=8.886957E-02 + Vmax=63253.3 + Nfs=1.668437E+11 + Tpg=-1.000 + Cgdo=3.35E-10 + Cjsw=2.23E-10
Ld=0.0u Vto=0.622490 Phi=0.31 Ucrit=174667 Xj=.9u Neff=4.68830 Rsh=60 Cj=3.27E-04 Mjsw=0.195
Tox=225.00E-10 Kp=6.326640E-05 Uo=1215.74 Delta=0.0 Lambda=0.0 Nss=3.00E+10 Cgso=2.89E-10 Mj=1.067
Ld=.03000u Vto=-0.63025 Phi=.541111 Ucrit=637449 Xj=0.112799u Neff=0.64354 Rsh=150 Cj=4.75E-04 Mjsw=.307
Tox=225.000E-10 Kp=2.635440E-05 Uo=361.941 Delta=0.0 Lambda=0.0 Nss=3.00E+10 Cgso=3.35E-10 Mj=.341
ml2_125.md assigns values to various Level 2 MOSFET model parameters for both n- and p-channel devices. T-Spice uses these parameters to evaluate Level 2 MOSFET model equations, and the results are used to construct internal tables of current and charge values. Values read or interpolated from these tables are used in computations called for by the input file.
The .OP command performs a DC operating point calculation and writes the results to the file specified in the Simulation > Run Simulation dialog.
Run the Simulation In T-Spice

With inverter_op.sp open in T-Spice, use File > Save to save the file. Click the Run Simulation button ( ) in the T-Spice simulation toolbar.
In the Run Simulation dialog, click Start Simulation. T-Spice will open a new window displaying the simulation results.
Output
The output file lists the DC operating point information for the circuit. You can read the file in T-Spice or a text editor.
Open the Output File

Select View > Simulation Manager from the T-Spice menu to bring up the Simulation Manager (if not already displayed):
Select the inverter_op display line in the window, and then left-click on the Show Output button to open the output file, inverter_op.out, in a new T-Spice window. If you prefer to view the output in a text editor, simply open inverter_op.out as a text file. (It is located in the same directory as the input file.) The output file contains the following DC operating point information (in addition to comments of various kinds, not shown here):
DC ANALYSIS - temperature=25.0 v(in) = 1.0000e+000 v(out) = 2.9317e+000 v(Vdd) = 3.0000e+000 i(Vdd) = -5.8077e-006 i(vin) = 0.0000e+000
Example 2: DC Transfer Analysis

DC transfer analysis is used to study the voltage or current at one set of points in a circuit as a function of the voltage or current at another set of points. This is done by sweeping the source variables over specified ranges and recording the output. Schematic T-Spice Input Output
inverter_dc inverter_dc.sp inverter_dc.out
Schematic
This schematic includes a .print command, which measures and records voltages at the input and output nodes of the circuit. The command is contained within the DC analysis output cell.
T-Spice Input
.probe .option probev .include "C:\S-Edit v12\Examples\models\ml2_125.md" m1n out in Gnd Gnd nmos L=5u W=8u m1p out in Vdd Vdd pmos L=5u W=12u c2 out Gnd 800f vin in Gnd 1 vdd Vdd Gnd 3 .print dc v(in) v(out) .dc lin vin 0 3 .02 lin vdd 2 4 .5
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The .DC command, indicating transfer analysis, is followed by the parameter LIN, which specifies a linear sweep. Next is a list of sources to be swept, and the voltage ranges across which the sweeps are to take place. In this example, VIN will be swept from 0 to 3 volts in 0.02 volt increments, and VDD will be swept from 2 to 4 volts in 0.5 volt increments. The transfer analysis will be performed as follows: VDD will be set at 2 volts and V1 will be swept over its specified range; VDD will then be incremented to 2.5 volts and V1 will be reswept over its range; and so on, until VDD reaches the upper limit of its range. The .DC command ignores the values assigned to the voltage sources VDD and V1 in the voltage source statements; however, they must be declared in those statements. The resulting voltages for nodes IN and OUT are reported by the .PRINT DC command to the specified destination.
Output
When W-Edit launches, simulation results of the same data type, which in this case is voltage, are automatically plotted on a single chart. In this example, traces were separated into different charts and reorganized (according to data type) using the commands Chart > OptionsGeneral and Chart > OptionsAxes in the W-Edit menu. The following charts show input and output voltages to the circuit, with separate traces for each sweep of VIN. To view detailed information about a trace, double-click on the trace or on the trace label located in the upper right corner of the chart. The Trace Properties dialog displays the value of parameter VDD corresponding to each trace, as well as labels and line properties. For more information on trace properties, see Properties in the W-Edit User Guide.
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Example 3: Transient Analysis: Inverter

Transient analysis provides information on how circuit elements vary with time. The basic T-Spice command for transient analysis has three modes. In the op mode (default), the DC operating point is computed, and T-Spice uses this as the starting point for the transient simulation. Example 3 illustrates this option. (The other modes, powerup and preview, are treated in Example 7: Transient Analysis, Powerup Mode on page 24 and Example 8: Transient Analysis, Preview Mode on page 27.) Schematic T-Spice Input Output
invert_tran invert_tran.sp invert_tran.out
Schematic
T-Spice Input
.option search="C:\S-Edit v12\Examples\models" .probe .option probev .option probei .include "ml2_125.md" m1n out in Gnd Gnd nmos L=5u W=8u m1p out in Vdd Vdd pmos L=5u W=12u c2 out Gnd 800f vin in Gnd pwl (0ns 0V 100ns 0V 105ns 3V 200ns 3V 205ns 0V 300ns 0V 305ns 3V 400ns 3V 405ns 0V 500ns 0V 505ns 3V 600ns 3V) vdd Vdd Gnd 3 .print tran v(in) v(out)
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.tran 1n 600n .end
This circuit is identical to that of Example 1, except that voltage source VIN here generates a piecewise linear waveform input (indicated by the keyword PWL) to IN, rather than setting a constant value. The times and voltages that define legs of the waveform are specified in the arguments to PWL. Between 0 and 100 nanoseconds, the voltage at IN is zero; between 100 and 105 nanoseconds, the voltage is linearly interpolated (ramps up) between 0 and 3; between 105 and 200 nanoseconds, the voltage stays at 3; and so on. The .TRAN command specifies the characteristics of the transient analysis to be performed: it will last for 600 nanoseconds, with time steps no larger than 2 nanoseconds.
Output
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Example 4: AC Analysis
AC analysis characterizes the circuits behavior dependence on small-signal input frequency. It involves three steps: (1) calculating the DC operating point; (2) linearizing the circuit; and (3) solving the linearized circuit for each frequency. Example 4 involves a standard operational amplifier, consisting of seven MOSFETs (four n-channel and three p-channel) and two capacitors. Schematic T-Spice Input Output
opamp_ac opamp_ac.sp opamp_ac.out
Schematic
T-Spice Input
.option Accurate .option search="C:\S-Edit v12\New Examples\models" .probe .option probev .include "ml2_125.md" Vdd Vdd Gnd 5 cout out Gnd 2p mp1 vm1 vm1 Vdd Vdd pmos L=6u W=6u mp2 vf1 vm1 Vdd Vdd pmos L=6u W=6u mp3 out vf1 Vdd Vdd pmos L=6u W=20u mn1 vn1 vbias Gnd Gnd nmos L=10u W=6u
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vdiff in2 in1 -700u AC 1 90 mn2 vm1 in1 vn1 Gnd nmos L=6u W=6u mn3 vf1 in2 vn1 Gnd nmos L=6u W=6u mn4 out vbias Gnd Gnd nmos L=10u W=6u vin1 in1 Gnd 2 vbias vbias Gnd 800m ccomp vf1 out 2p .print ac vdb(out) vp(out) .op .ac dec 5 1 100meg .end
Three voltage sources (in addition to VDD) are defined.

VDIFF sets the DC voltage difference between nodes IN2 and IN1 to 0.0007 volts; its AC magnitude is 1 volt and its AC phase is 90 degrees. VIN1 sets node IN1 to 2 volts, relative to GND. VBIAS sets node BIAS to 0.8 volts, relative to GND.
The .AC command performs an AC analysis. Following the .AC keyword is information concerning the frequencies to be swept during the analysis. In this case, the frequency is swept logarithmically, by decades (DEC); 5 data points are to be included per decade; the starting frequency is 1 Hz and the ending frequency is 100 MHz. The .PRINT command writes the voltage magnitude (in decibels) and phase (in degrees), respectively, for the node OUT to the specified file.
Output
The AC simulation will automatically result in DC Operating Point information and AC small-signal model parameters being written to the output file, in addition to all output generated from .print statements.
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Example 5: Subcircuits
Subcircuit definitions allow arbitrarily complex arrangements of nodes and devices to be easily reused multiple times in a circuit. A subcircuit definition in S-Edit is contained within a cell definition, and is comprised of both a schematic view and a symbol view. Each instance of the symbol encapsulates the subcircuit schematic, allowing a simple but complete representation of subcircuit dynamics. Example 5 uses a NAND gate to illustrate the use of subcircuit definitions and subcircuit parameters. Schematic T-Spice Input Output
nandgate nandgate.sp nandgate.out
Schematic
An instance of the subcircuit NAND is created in the schematic and labeled XNAND1. To access nand from the main schematic, double-click on the NAND item in the Library Navigator window. As discussed in Example 1, symbol properties are used to define component properties such as length and width. This example introduces a new symbol property, SPICE.PARAMETER, which allows parameters to be passed through a hierarchical netlist. The symbol that represents nand has the property:
SPICE.PARAMETER = L NW PW
This statement specifies that the cell properties L, NW, and PW are subcircuit parameters of NAND. The cell also contains the 3 property definitions:
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L = 5u NW = 10u PW = 10u
These parameters define properties of all n-channel and p-channel MOSFETS within the subcircuit:
L represents the length property of both n- and p-channel MOSFETS. NW represents n-channel width. PW represents p-channel width.
Attaching these parameters to NAND allows component properties within the subcircuit definition to be controlled in the subcircuit call.
T-Spice Input
********* Simulation Settings - General section ********* .option search="C:\S-Edit v12\Examples\models" .probe .option probev .include "ml2_125.md" .ic nand1/nn1=2V *************** Subcircuits ***************** .subckt NAND in1 in2 out Gnd Vdd L=5u PW=10u NW=10u mt1 out in1 nn1 Gnd nmos L='l' W='nw' mt2 nn1 in2 Gnd Gnd nmos L='l' W='nw' mt3 out in1 Vdd Vdd pmos L='l' W='pw' mt4 out in2 Vdd Vdd pmos L='l' W='pw' .ends ********* Simulation Settings - Parameters and SPICE Options ********* Xnand1 a b outab Gnd Vdd NAND L=5u PW=12u NW=8u va a Gnd pwl(0 0 100n 0 105n 5 200n 5 205n 0 300n 0 305n 5 400n 5 405n 0 500n 0 505n 5 600n 5) vb b Gnd 5 vvdd Vdd Gnd 5 .print tran v(a) v(outab) v(nand1/nn1) ********* Simulation Settings - Analysis section ********* .op .tran 1n 600n .end
Subcircuits are defined by blocks of device statements bracketed with the .SUBCKT and .ENDS commands, and instanced by statements beginning with the key letter X. The .SUBCKT command includes the name of the subcircuit being defined (NAND), a list of terminals, and three subcircuit parameters. The terminals do not have a predefined order, but whatever order is used in the definition must be used in instances. Parameters can be written in any order in both the definition and the instances. Parameter values specified in the definition are used as defaults when not specified in instances. Within the subcircuit definition, four MOSFETs are defined in the usual manner (and in these statements the order of terminals is important: draingatesourcebulk). Node N1 is the source of transistor MT1 and the drain of transistor MT2. Subcircuit parameters, enclosed by single quotes, are used in place of numerical values. After the subcircuit is defined, you can create an instance of the subcircuit. The instance statement begins with the key letter X, but the name of the instance (by which it is to be identified in the rest of the input file) is NAND1, not XNAND1.
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The list of terminals in the instance statement must have the same order as on the first line of the subcircuit definition: A B OUT(instance) corresponds to IN1 IN2 OUT (definition). The next argument of the instance statement is the original subcircuit name (NAND). Two of the default subcircuit parameter values, as originally specified by the definition, are overridden by instance-specific assignments. These assignments may appear in any order. The parameter omitted from the instance statement (L) retains its default value. Initial conditions on node voltages and currents can be set for the purposes of computing the DC operating point. The .IC command sets node NAND1/N1 (that is, node N1 of instance NAND1) to 2 volts for the duration of the DC operating point calculation. When transient analysis begins, the node will return to a floating voltage state. Voltage source VA supplies a PWL (piecewise linear) input waveform to node A. Two analyses are carried out on this circuit: a DC operating point calculation (.OP) and a transient simulation (.TRAN) with a duration of 600 nanoseconds and a maximum timestep of 1 nanosecond. The .PRINT command reports simulation results for the voltages at nodes A, OUT, and NAND1/N1.
Output
20
Example 6: Transient Analysis: CMOS D-Latch

Transient analysis on a CMOS static D-latch demonstrates the analog D-latch characteristics of a digital circuit. The circuit has four inverters and four transmission gates. Schematic T-Spice Input Output
dlatch dlatch.sp dlatch.out
Schematic
T-Spice Input
MTG3P MINV3P MINV4P MINV3N MINV4N MTG4P MTG3N VDD VDATA VPHI1 VPHI2 MINV1N MINV1P MINV2P N3 Q N4 Q N4 N5 N3 PHI2 N5 N5 VDD Q VDD N5 GND Q GND PHI1 N4 PHI1 N5 VDD PMOS L=5U W=12U VDD PMOS L=5U W=12U VDD PMOS L=5U W=12U GND NMOS L=5U W=8U GND NMOS L=5U W=8U VDD PMOS L=5U W=12U GND NMOS L=5U W=8U
VDD GND 3V DATA GND BIT ({1000} ON=3 OFF=0 DELAY=0 PW=20N RT=1.25N FT=1.25N) PHI1 GND BIT ({0011} ON=3 OFF=0 DELAY=0 PW=10N RT=1.25N FT=1.25N) PHI2 GND BIT ({1100} ON=3 OFF=0 DELAY=0 PW=10N RT=1.25N FT=1.25N) N3 N3 N2 N1 N1 N3 GND GND NMOS L=5U W=8U VDD VDD PMOS L=5U W=12U VDD VDD PMOS L=5U W=12U
21
MINV2N MTG1N MTG2P MTG1P MTG2N MTG4N .TRAN
N2 N3 GND GND NMOS L=5U W=8U DATA PHI2 N1 GND NMOS L=5U W=8U N1 PHI2 N2 VDD PMOS L=5U W=12U DATA PHI1 N1 VDD PMOS L=5U W=12U N1 PHI1 N2 GND NMOS L=5U W=8U N5 PHI2 N4 GND NMOS L=5U W=8U 0.2N 200N
.INCLUDE ML2_125.MD .GLOBAL VDD .PRINT .PRINT .PRINT .PRINT .PRINT .PRINT .PRINT .END TRAN TRAN TRAN TRAN TRAN TRAN TRAN V(N3) V(Q) V(PHI1) V(DATA) V(N1) V(N5) V(PHI2)
Voltage source VDD sets the voltage between power and ground to 3 volts. The next three statements beginning with V define voltage sources for custom input waveforms. Following each voltage source name are the names of the input nodes and the type of waveform. Here, however, not piecewise linear but rather bit waveforms are used. Following the keyword BIT in parentheses are parameters specifying the waveform characteristics. The four-digit sequence in braces { } specifies the sequence of the waves states (either 1, on, or 0, off). This sequence will be repeated until the simulation is complete. The pulse width (PW) is 2 nanoseconds. The OFF voltage is zero, the ON voltage is 3 volts, and the rise (RT) and fall (FT) times are each one-quarter of a nanosecond. The .TRAN command instructs T-Spice to perform a 200-nanosecond simulation while printing node voltages at least every 0.2 nanoseconds. The .PRINT commands write simulation results for the voltages at each of seven nodes to the specified file.
Output
The following chart shows the seven output voltages measured during simulation, plotted across time. The traces have been expanded and reordered from the default setting. When a chart is expanded, the traces will be displayed in the same order in which they were loaded. Traces can be loaded or unloaded on a chart with the Chart > OptionsFormat dialog.
Note:
When a trace is added to an existing chart, the axes scaling is not automatically updated. To rescale the axes for optimal display, you can use the HOME key.
22
Select Chart > OptionsAxes to choose appropriate spacing of the major and minor tick marks.
23
Example 7: Transient Analysis, Powerup Mode

Some circuits do not have a DC steady state or quiescent point. Because such circuits are constantly fluctuating with time, finding the starting point for their simulation is a problem. More precisely, the challenge is to define the initial state of a circuit which has no definite DC steady-state condition. This is done in T-Spice with the powerup option of the .tran command. The powerup option essentially sets the entire circuit to zero for time equal to zero. As the simulation proceeds, the voltage sources are allowed to ramp up to their specified values. The ring oscillator is an example of such a time-dependent circuit. Schematic T-Spice Input Output
ring ring.sp ring.out
Schematic
T-Spice Input
.SUBCKT INVERT IN OUT M1 OUT IN GND GND NMOS L=5U W=8U M2 OUT IN VDD VDD PMOS L=5U W=12U C1 OUT GND 800FF .ENDS VDD XINV1 XINV2 XINV3 XINV4 VDD N1 N2 N3 N4 GND N2 N3 N4 N5 3V INVERT INVERT INVERT INVERT
24
XINV5 N5 N6 INVERT XINV6 N6 N7 INVERT XINV7 N7 N1 INVERT C1 N1 GND 400FF .TRAN/POWERUP 1N 1U .INCLUDE ML2_125.MD .GLOBAL VDD .PRINT TRAN V(N1) .PRINT TRAN V(N2) .PRINT TRAN V(N7) .END
A subcircuit named INVERT is defined with two terminals. (This inverter is structurally identical to the one used in Example 1 and Example 4.) Seven instances of the subcircuit, labeled INV1 through INV7, are defined next. The output of each inverter is connected to the input of the next in the ring. The POWERUP option of the .TRAN command eliminates the DC convergence problem for unstable circuits. If the POWERUP option were not specified, then T-Spice would try to calculate a DC operating point, which would lead to problems for this oscillator. This simulation example also introduces us to two of the more powerful advaanced features of T-Spice: parameter sweeping and the .measure command. In the T-Spice Simulation Setup, a parameter sweep is defined, in which the capacitor value is varied in a linear sweep from 200 femto-Farads to 1000 femto-Farads in increments of 200. This results in 5 sets of simulation results being generated, one for each capacitor value. The .measure command is a tool for capturing and summarizing the electrical behavior of a circuit. Information such as delay, rise and fall times, minimum and maximum signal values, and a host of other computed results can be aquired with these measurements. In this example, 3 measurements are computed, period, pulsewidth, and delay. Since the simulation also includes a parameter sweep, a seperate set of measurement values will be computed for each parameter value (capacitance), and displayed in a summary table at the end of the Simulation log.
25
Output
26
Example 8: Transient Analysis, Preview Mode

Before a lengthy transient simulation is run on a large circuit, the input waveforms can be examined using the preview option of the .tran command. This option instructs T-Spice to report only specified input stimuli, and to forego simulation of the remainder of the circuit. In addition to illustrating the preview mode, this simple wave circuit showcases the variety and flexibility of input patterns available to current and voltage sources in T-Spice. T-Spice Input Output
wave.sp wave.out
Note:
This example does not include a schematic. The T-Spice netlist is located in the spice subdirectory of the examples installation. In T-Spice, use File > Open to open the provided netlist directly.
Schematic
For a description of this circuit, see Input, below.
T-Spice Input
r1 n1 GND 2k r2 n2 GND 2k r3 n3 GND 2k r4 n4 GND 2k r5 n5 GND 2k r6 n6 GND 2k r7 n7 GND 2k r8 n8 GND 2k r9 n9 GND 2k v1 n1 GND pwl (0n 0 100n 0 101n 5 300n 5 301n 0 + 500n 0 680n 5 700n 0 880n 5 900n 0) v2 n2 GND pwl (0n 0 100n 0 101n 1 200n 1 201n 2 300n 2 301n 3 + 400n 3 401n 4 500n 4 501n 5 600n 5 601n 4 + 700n 4 701n 3 800n 3 801n 2 900n 2 901n 1) v3 n3 GND sin (2.5 2.5 30MEG 100n) v4 n4 GND bit ({01010 11011} on=5.0 off=0.0 pw=50n rt=10n ft=30n) v5 n5 GND bit ({5(01010 5(1))} pw=10n on=5.0 off=0.0) .vector bb {n6 n7 n8 n9} vb bb GND bus ({50(Ah) 30(7d4) 20(1000)} pw=5n on=5.0 off=0.0) .print tran n1 n2 n3 n4 n5 n6 n7 n8 n9 .tran/preview 1n 1u
Nine resistor/node/voltage source combinations, numbered 1 through 9, are defined. Each resistor has a resistance of 2 kilohms; each voltage source, connected across the corresponding resistor to ground, supplies its characteristic waveform to the corresponding node. Two voltage sources, v1 and v2, generate pwl (piecewise linear) inputs. v1 produces a single pulse followed by a pair of sawtooth cycles, and v2 produces a staircase waveform which takes 1-volt steps from zero up to 5 volts and back down to 1 volt.
27
Voltage source v3 generates a sin (sinusoidal) input. It has an amplitude of 2.5 volts, a frequency of 30 MHz, an offset of 2.5 volts from system ground, and a time delay of 100 nanoseconds after the start of the simulation before the wave begins. Voltage source v4 generates a bit input. Enclosed in braces { } are two binary-valued five-bit patterns specifying the waveform. The two patterns alternate in time. The on voltage value is 5.0 volts; the off voltage value is zero. The pulse width (pw), 50 nanoseconds, is the time the wave is either (ramping up and) on, or (dropping down and) off. The rise time (rt), 10 nanoseconds, is the time given for the wave to ramp from off to on; the fall time (ft), 30 nanoseconds, is the time given for the wave to drop from on to off. Voltage source v5 generates a repeating bit input. Two distinct patterns are given again, but now multiplier factors are included. The wave consists of two alternating patterns: the first pattern contains five bits, the second is a single bit. The five-bit pattern is followed by five successive repetitions of the single-bit pattern, and this sequence is repeated five times. (The same pattern could be described by {5(3(01) 4(1))}.) The pulse width and on and off voltages are again specified, but the rise and fall times take default values. The .vector command defines the bus waveform generated by voltage source vb. The command assigns the bus a name (bb) and specifies by name the number of bits the bus waveform will have (four: n6 through n9). The voltage source statement, which contains the bus keyword, specifies waveforms with one or more patterns, along with pulse width and level information. The patterns can be in binary, hexadecimal, octal, or decimal notation. (For decimal patterns the number of lower-order bits to be collected is also given.) The first pattern is Ah (hex) = 1010 (binary). Thus, using the names given on the .vector command, n6=1, n7=0, n8=1, and n9=0. The pattern is repeated 50 times (that is, maintained for a time period equal to the pulse width multiplied by 50). The next pattern is 7d4 that is, 7 (decimal) = 111 (binary), or, to four lower-order bits, 0111. So n6=0, n7=1, n8=1, and n9=1. The pattern is repeated 30 times. The last pattern is 1000 (binary), so n6=1, n7=0, n8=0, and n9=0. The pattern is repeated 20 times. The .print command writes the results at the output nodes of all nine voltage sources. The .tran/preview command reports the input waveforms in place of running the simulation.
28
Output
29
Example 9: Noise Analysis

Real circuits are never immune from small random fluctuations in voltage and current levels. In T-Spice, the influence of noise in a circuit can be simulated and reported in conjunction with AC analysis. The purpose of noise analysis is to compute the effect of the noise associated with various circuit devices on an output voltage or voltages as a function of frequency. Schematic T-Spice Input Output
opamp_noise opamp_noise.sp opamp_noise.out
Schematic
For a description of this circuit, see Example 4.
T-Spice Input
MN2 N1N4 IN1 VN1 GND NMOS L=6U W=6U MN3 N1N16 IN2 VN1 GND NMOS L=6U W=6U MP2 N1N16 N1N4 VDD VDD PMOS L=6U W=6U MN1 VN1 BIAS GND GND NMOS L=10U W=6U MP3 OUT N1N16 VDD VDD PMOS L=6U W=20U CCOMP N1N16 OUT 2PF MP1 N1N4 N1N4 VDD VDD PMOS L=6U W=6U MN4 OUT BIAS GND GND NMOS L=10U W=6U COUT OUT GND 2PF VBIAS BIAS GND 0.8V VDIFF IN2 IN1 DC -0.0007 AC 1 90 VIN IN1 GND 2V VDD VDD GND 5V .PRINT NOISE TRANS='TRANSFER' .PRINT NOISE DN(MN1) .NOISE V(OUT) VBIAS 5 .PRINT NOISE ONOISE INOISE DB(ONOISE) DB(INOISE) .AC DEC 5 1 100MEG .INCLUDE ML2_125.MD .GLOBAL VDD .END
Noise analysis is performed in conjunction with AC analysis; if the .AC command is missing, then the .NOISE command is ignored. With the .AC command present, the .NOISE command causes noise analysis to be performed at the same frequencies: starting at 1 Hz, ending at 100 MHz, with 5 data points per decade. The .NOISE command takes two required arguments: the output at which the effects of noise are to be computed, and the input at which the noise can be considered to be concentrated for the purpose of estimating equivalent noise spectral density. Additionally, a third optional argument specifies the frequency interval at which a noise report will be printed to the simulation log, listing every device noise contribution. The .PRINT NOISE command, with six arguments, writes to the output file eleven numbers for each frequency analyzed. Many other options are available.
30
Output
31
Example 10: Table Model Evaluation
Example 10: Table Model Evaluation

T-Spice employs two fundamental techniques of simulation: direct model evaluation and table-based evaluation. In direct model evaluation, values are computed as needed from analytical equations, returning results as accurate as the models used allow. In table-based evaluation, tables of values are precomputed from analytical equations at finite resolution, and needed values are linearly interpolated from stored values. This technique is slightly less accurate, but is significantly faster. Direct evaluation is T-Spices default simulation technique. Table-based model evaluation can be explicitly selected, as in Example 10, which repeats the transient analysis of Example 1: DC Operating Point Analysis on page 6. Schematic T-Spice Input Output
inverter_table inverter_table.sp inverter_table.out
T-Spice Input
M1 OUT IN GND GND NMOS L=5U W=8U M2 OUT IN VDD VDD PMOS L=5U W=12U C1 OUT GND 800FF VDD VDD GND 3V VIN IN GND PWL (0 0 100N 0 105N 3 200N 3 205N 0 300N 0 305N 3 400N 3 + 405N 0 500N 0 505N 3 600N 3) .OPTIONS DEFTABLES=0 ABSTOL=5.0E-10 RELTOL=1.0E-4 CHARGETOL=1.0E-14 + RELCHARGETOL=1.0E-4 ACCT=1 VERBOSE=2 MAXORD=4 .TRAN 2N 600N .INCLUDE ML2_125.MD .GLOBAL VDD .PRINT TRAN V(IN) .PRINT TRAN V(OUT) .END
This input file is identical to that of Example 3, with the added command .OPTIONS MODELMODE=CACHETABLE. This turns on the cache table generation in which model table are dynamically filled and interpreted during the simulation. Several other simulation options and default values are listed in the .OPTIONS command line.
Output
Compare inverter_table.out, obtained using internal table-based model evaluation, to invert_tran.out, obtained using direct modelevaluation. For the inverter or other digital circuits there will be only slight differences in the results. For analog circuits, however, there can be greater discrepancies between results from the two evaluation techniques.
32
Example 11: Transistor Subthreshold Behavior

Modern analog designs are required to meet strict specifications with tight tolerances. Designers therefore need models that can accurately simulate semiconductor device behavior over all regions of operation. It has been traditionally difficult to model the operation of MOSFETs in the subthreshold region, particularly through the transition from subthreshold to above threshold. This region is of special interest to designers of low-power and advanced analog designs, in which MOSFETs are sometimes intentionally biased to operate in this transition region. In subthreshold, the saturation drain current of a MOSFET is an exponential function of the gate voltage, and the drain current saturates at a drain voltage that is independent of gate voltage. Well above threshold, the transistor drain current is a quadratic function of the gate voltage, and the drain current saturates at a drain voltage which is a function of the gate voltage. T-Spice supports the simulation of MOSFETs in the subthreshold region in the following ways. The MOSFET Level 47, 49, and 53 models (BSIM3 Revisions 2 and 3) in the Advanced Model Package include subthreshold characteristics. The T-Spice simulation engine can accurately simulate low-current operation without convergence problems even when internal tables are used for improved speed.
33
Example 11 simulates the gate characteristics of a transistor in subthreshold by sweeping its gate voltage while holding drain voltage fixed. T-Spice Input Output
trangm.sp trangm.out
Note:
Because this example does not include a schematic, you will bypass the S-Edit project and open your input file directly from T-Spice. Launch T-Spice and use File > Open to open the netlist, which is located at ../spice/trangm.sp.
T-Spice Input
.include ml5_20.md mn5 drain gate GND GND nmos l=10u w=6u vdrain drain GND 5 vgate gate GND 0.85 .dc vgate .5 1.5 0.01 .print dc id(mn5) .options abstol=1E-14
Voltage source vgate is attached to the gate terminal of the MOSFET mn5 and is swept from 0.5 to 1.5 volts by the .dc command. Voltage source vdrain is attached to the drain terminal with a fixed value of 5 volts, which keeps the transistor well in saturation. The source and bulk terminals are grounded. The .print dc command reports current through the drain terminal of mn5. The .options accurate command changes several option values in order to increase the overall simulation accuracy, so that low-current and subthreshold behavior can be simulated accurately. .
Output
The logarithm of the current is a straight line for low gate voltages and shows a smooth transition between low-current exponential behavior and high-current quadratic behavior.
34
35
Example 12: MOS Transconductance Amplifier

The basic transconductance amplifier produces an output current proportional in magnitude to the difference between the input voltages. Proper modeling of the transconductance amplifiers output current behavior, over a broad range of differential voltages, requires accurate subthreshold modeling of its transistors. Otherwise, the predicted transconductance characteristics will be inaccurate. This circuit can be simulated correctly in subthreshold by T-Spice. Schematic T-Spice Input Output
transamp transamp.sp transamp.out
Schematic
T-Spice Input
.option Accurate .option search="C:\S-Edit v12\Examples\models" .include "ml5_20.md" ********* Simulation Settings - Parameters and SPICE Options ********* Vdd Vdd Gnd 5 mp1 vm1 vm1 Vdd Vdd pmos L=6u W=6u vout out Gnd 2.5 mp2 out vm1 Vdd Vdd pmos L=6u W=6u mn1 vn1 vbias Gnd Gnd nmos L=10u W=6u vdiff in2 in1 0 mn2 vm1 in1 vn1 Gnd nmos L=6u W=6u mn3 out in2 vn1 Gnd nmos L=6u W=6u
36
vin1 in1 Gnd 2 vbias vbias Gnd 700m .print dc i1(vout) id(mn3) id(mn2) ********* Simulation Settings - Analysis section ********* .op .dc lin vdiff -1 1 .01 .end
This circuit is identical to the one described in Example 4, except that the output stage (inverter) has been removed, and a voltage source has been connected to the output so that the transconductance characteristics of the amplifier can be measured. The .OPTIONS ACCURATE command changes, among other options, the absolute value of the current tolerance that T-Spice uses, allowing low-current and subthreshold behavior to be simulated accurately.
Output
37
Design Examples
Design Examples
Following are design examples created and simulated by T-Spice Pro. These examples are intended to provide a practical synthesis of the concepts presented in Examples 1-12, as well as to present some more advanced features of T-Spice. The design examples consist of two tutorial projects:
T-Spice Pro GaAs Amp
Files needed for simulation of a sample wide-band GaAs IC amplifier. Files needed for simulation of a sample voltage-controlled ring oscillator.
T-Spice Pro Ring VCO
Wide-Band GaAs IC Amplifier

This example project describes the design and performance of a wide-band GaAs IC amplifier. The amplifier consists of two cascaded stages. It features a high-voltage gain (>20 dB), wide bandwidth, and very low input VSWR. This amplifier is useful for many signal processing and instrument/ measurement applications. The examples folder contains four examples for characterizing the AC, DC and transient performance and measuring S-parameters of the circuit:
amp_ac
The amplifier schematic, containing commands for AC, noise, and small-signal parameter analysis. The amplifier schematic, containing commands for DC transfer analysis. Schematic of a circuit design appropriate for measurement of the amplifier s-parameters. The amplifier schematic, containing commands for transient analysis.
amp_dc amp_sparam amp_tran
Each of the schematics amp_ac, amp_dc, and amp_tran contains components to generate T-Spice analysis functions that were explored in previous examples. The transient analysis example, amp_tran, contains a polynomial voltage controlled voltage source. This provides a ramp-up sinusoidal wave as an input source. The circuit shown in the schematic amp_sparam is wired in the same way that s-parameters are measured. The components labeled GAASAMP are instances of the basic GaAs IC Amplifier schematic, amp. AC analysis on nodes S11, S21, S12, and S22 provides the corresponding s-parameters: S11, S21, S12, and S22. T-Spice reads the contents of model file gaas.md to obtain parameter values used in the evaluation of MESFET and diode model equations. The model file is located in the main project directory.
38
Design Examples
Voltage Controlled Ring Oscillator

This example describes the design and performance of a voltage-controlled ring oscillator. The ring VCO consists of a control stage that provides bias and tuning voltage and seven differential cells that form a ring oscillator. The tuning voltage from the control stage controls the frequency of the ring oscillator. The applications of VCO include frequency modulators, tone generators, A/D converters, and digital voltmeters.
ringvco
The ring oscillator schematic, containing commands for transient analysis. Subcircuit schematic for the bias control stage in the ring VCO. Subcircuit schematic for a differential amplifier.
control diffcell
Additional files located in the ringvco directory include:

mosis2u.md
MOSIS MOSFET 2um model parameters. This is the model that is used in simulating the design. An external T-Spice macromodel of a voltage-controlled oscillator. A DLL which contains the VCO macromodel described above. This DLL is used by T-Spice during simulation. A Spice file showing the performance of the VCO macro-model. This file has macromodel parameters tuned to match the performance of the actual circuit in ringvco.
vco.c vco.dll vcomacro.sp
This example provides the option to model the ring VCO using the user-defined external model feature in T-Spice. The file vco.c is the ring VCO model written in the C programming language. This C file is compiled and built into a dynamically linked library, vco.dll, before simulating the circuit. The file vco.dll can then be included in the SPICE input file for simulation in T-Spice.
Note:
For more information on the external model feature in T-Spice, see User-Defined External Models in the T-Spice User Guide and Reference.
39
Index
A
abstol keyword, 34
AC analysis, 15
.ac command, 16
accuracy, 4, 34 Advanced Model Package, 3, 4 amplifiers GaAs IC, 38 transconductance, 36 analysis AC, 15 DC operating point, 69 DC transfer, 10 noise, 30 transient, 13, 24, 27 attributes defined, 6 PARNAM, 18 axes formatting, 23 logarithmic, 34
B
binary notation, 28 bit keyword, 22 bitwise input, 22 bus keyword, 28
C
C, key letter, 8
capacitor, 8 charts expand/collapse operations, 11 new, 22 collapsing charts, 11
40
Index
convergence, 3, 25 current tolerance, 34
D
.dc command, 11
DC operating point analysis, 8

dec keyword, 16
decimal notation, 28
deftables keyword, 32
dialogs Simulation Manager, 9 Trace Properties, 11 digital circuit example, 21 DLL, 39 DxDesigner attributes, 6 subcircuits, 18
E
.ends command, 19
evaluation methods compared, 32 direct model, 32 table-based, 32 examples AC Analysis, 1517 DC Operating Point Analysis, 69 DC Transfer Analysis, 1012 Direct Model Evaluation, 32 MOS Transconductance Amplifier, 3637 Noise Analysis, 3031 Subcircuits, 1820 Transient Analysis, 1314, 2123 Transient Analysis, Powerup Mode, 2426 Transient Analysis, Preview Mode, 2729 Transistor Subthreshold Behavior, 3334 Voltage Controlled Ring Oscillator, 39 Wide-Band GaAs IC Amplifier, 38 expanding charts, 11 export netlist, 7 external models, 39
41
Index
F
frequency sweeping, 16
G
GaAs amplifier, 38 .gridsize command, 34
H
hexadecimal notation, 28
I
.ic command, 20 .include command, 8
initial conditions, 20, 24 input, previewing, 27 instance subcircuit, 1920
K
key letter, 8 C, 8 M, 8 X, 19
L
lin keyword, 11
logarithmic sweep, 16
42
Index
low-current simulation, 34, 37
M
M, key letter, 8
macromodels, 4, 39
.model command, 8
model evaluation direct, 32 model files, 8 models, external, 39 MOSFET regions of operation, 33 subthreshold simulation, 33 T-Spice definition, 8
N
netlist, exporting, 7 noise analysis, 30 .noise command, 30
O
octal notation, 28 .op command, 8 .options command, 32, 34, 37 oscillator, voltage-controlled, 39 output files opening, 9
P
parameters passing through hierarchy, 18 subcircuit, 19 sweeping, 1011 PARNAM, 18 piecewise linear, 14
43
Index
powerup keyword, 24, 25 preview keyword, 27 .print command, 10, 16 .print noise command, 30 PWL keyword, 14
R
resolution, 34 ring VCO, 39 run simulation, 9
S
semiconductor device simulation, 33 simulation commands .ac, 16 .dc, 11 .ends, 19 .gridsize, 34 .ic, 20 .include, 8 .model, 8 .noise, 30 .op, 8 .options, 32, 34, 37 .print, 10, 16 .print noise, 30 .subckt, 1920 .tran, 14 .tran/powerup, 2425 .tran/preview, 27, 28 .vector, 28 simulation, running, 9 sin keyword, 28 s-parameters, 38 speed, 3 stability, problems with, 25 subcircuit, 1820 definition, 1920 described, 18 DxDesigner, 18 instance, 1920 parameters, 19 .subckt command, 1920 subthreshold behavior
44
Index
transconductance amplifier, 36 transistor, 33 modeling, 36 region, 33 sweeps, 10 frequency, 16 linear, 11 logarithmic, 16 symbols attributes, 6, 18
T
tables, 3, 8 tolerance, current, 34 traces loading, 22 order of, 22 properties, 11 .tran command, 14 .tran/powerup command, 2425 .tran/preview command, 27, 28 transconductance amplifier, 36 transfer analysis, 10 transient analysis, 21 default mode, 13 op mode, 13 powerup mode, 24, 25 preview mode, 27 transition region, 33 T-Spice accuracy, 4 advantages, 34 convergence, 3 speed, 3
U
unstable circuits, 25
V
variables
45
Index
sweeping, 1011
.vector command, 28
voltage source bit, 22, 28 bus, 28 DC, 8 piecewise linear, 14, 27 polynomial, 38 repeating bit, 28 sinusoidal, 28 voltage-controlled, 38
W
W-Edit add chart, 22 axes, formatting, 22, 34 traces, 11, 22
X
X key letter, 19
46
Credits
Software Development
Ken Van de Houten
Quality Assurance
Luba Gromova Ken Van de Houten Lena Neo
Documentation
Judy Bergstresser Ken Van de Houten
T-Spice Pro 12 Examples Guide
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T-Spice12 Examples Guide 1

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T-Spice Examples GuideContents

1 2 Introduction Circuit Analysis Examples 3 5

T-Spice12 Examples Guide

T-Spice Examples GuideContents

T-Spice12 Examples Guide

The T-Spice Pro Circuit Simulation System

T-Spice 12 Examples Guide

The T-Spice Pro Circuit Simulation System

T-Spice 12 Examples Guide

Circuit Analysis Examples

T-Spice 12 Examples Guide

Chapter 2: Circuit Analysis Examples

Example 1: DC Operating Point Analysis

Example 1: DC Operating Point Analysis

SPICE Simulation Setup

T-Spice 12 Examples Guide

Chapter 2: Circuit Analysis Examples

Example 1: DC Operating Point Analysis

Export the Netlist to T-Spice

T-Spice 12 Examples Guide

Chapter 2: Circuit Analysis Examples

Example 1: DC Operating Point Analysis

Ld=0.0u Vto=0.622490 Phi=0.31 Ucrit=174667 Xj=.9u Neff=4.68830 Rsh=60 Cj=3.27E-04 Mjsw=0.195

Tox=225.00E-10 Kp=6.326640E-05 Uo=1215.74 Delta=0.0 Lambda=0.0 Nss=3.00E+10 Cgso=2.89E-10 Mj=1.067

Ld=.03000u Vto=-0.63025 Phi=.541111 Ucrit=637449 Xj=0.112799u Neff=0.64354 Rsh=150 Cj=4.75E-04 Mjsw=.307

Tox=225.000E-10 Kp=2.635440E-05 Uo=361.941 Delta=0.0 Lambda=0.0 Nss=3.00E+10 Cgso=3.35E-10 Mj=.341

T-Spice 12 Examples Guide

Chapter 2: Circuit Analysis Examples

Example 1: DC Operating Point Analysis

Run the Simulation In T-Spice

Open the Output File

T-Spice 12 Examples Guide

Chapter 2: Circuit Analysis Examples

Example 2: DC Transfer Analysis

Example 2: DC Transfer Analysis

T-Spice 12 Examples Guide

Chapter 2: Circuit Analysis Examples

Example 2: DC Transfer Analysis

T-Spice 12 Examples Guide

Chapter 2: Circuit Analysis Examples

Example 2: DC Transfer Analysis

T-Spice 12 Examples Guide

Chapter 2: Circuit Analysis Examples

Example 3: Transient Analysis: Inverter

Example 3: Transient Analysis: Inverter

T-Spice 12 Examples Guide

Chapter 2: Circuit Analysis Examples

Example 3: Transient Analysis: Inverter

.tran 1n 600n .end

T-Spice 12 Examples Guide

Chapter 2: Circuit Analysis Examples

T-Spice 12 Examples Guide

Chapter 2: Circuit Analysis Examples

Three voltage sources (in addition to VDD) are defined.

T-Spice 12 Examples Guide

Chapter 2: Circuit Analysis Examples

T-Spice 12 Examples Guide

Chapter 2: Circuit Analysis Examples

T-Spice 12 Examples Guide

Chapter 2: Circuit Analysis Examples

T-Spice 12 Examples Guide

Chapter 2: Circuit Analysis Examples

T-Spice 12 Examples Guide