IC (Inter-Integrated Circuit) (pronounced /a skwrd si/ or /a tu si/) (generically referred to as "two-wire interface") is a multi-master serial single-ended computer bus

invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, or cellphone. Since the mid 1990s several competitors (e.g. Siemens AG (later Infineon Technologies AG), NEC, Texas Instruments, STMicroelectronics (formerly SGS-Thomson), Motorola (later Freescale), Intersil, etc.) brought IC products on the market, which are fully compatible with the NXP (formerly Philips' semiconductor division) IC-system. As of October 10, 2006, no licensing fees are required to implement the IC protocol. However, fees are still required to obtain IC slave addresses allocated by NXP.[1] SMBus, defined by Intel in 1995, is a subset of IC that defines stricter electrical and protocol conventions. One purpose of SMBus is to promote robustness and interoperability. Accordingly, modern IC systems incorporate policies and rules from SMBus, sometimes supporting both IC and SMBus with minimal re-configuration required.

Contents
[hide]

1 Design o 1.1 Reference design o 1.2 Message protocols o 1.3 Messaging example: 24c32 EEPROM o 1.4 Physical layer 1.4.1 Clock stretching using SCL 1.4.2 Arbitration using SDA o 1.5 Timing diagram o 1.6 Example of bit-banging the I2C Master protocol 2 Applications 3 Operating system support 4 Development tools o 4.1 IC host adapters o 4.2 IC protocol analyzers o 4.3 Logic analyzers 5 Revisions 6 Limitations 7 Derivative technologies 8 See also 9 References 10 External links

[edit] Design

A sample schematic with one master (a microcontroller), three slave nodes (an ADC, a DAC, and a microcontroller), and pull-up resistors Rp IC uses only two bidirectional open-drain lines, Serial Data Line(SDA) and Serial Clock (SCL), pulled up with resistors. Typical voltages used are +5 V or +3.3 V although systems with other voltages are permitted. The IC reference design has a 7-bit address space with 16 reserved addresses, so a maximum of 112 nodes can communicate on the same bus. Common IC bus speeds are the 100 kbit/s standard mode and the 10 kbit/s low-speed mode, but arbitrarily low clock frequencies are also allowed. Recent revisions of IC can host more nodes and run faster (400 kbit/s Fast mode, 1 Mbit/s Fast mode plus or Fm+, and 3.4 Mbit/s High Speed mode); those speeds are more widely used on embedded systems than on PCs. There are other features, such as 16-bit addressing. Note that the bit rates quoted are for the transactions between master and slave without clock stretching or other hardware overhead. Protocol overheads include a slave address and perhaps a register address within the slave device as well as per-byte ACK/NACK bits. So the actual transfer rate of user data is lower than those peak bit rates alone would imply. For example, if each interaction with a slave inefficiently allows only 1 byte of data to be transferred, the data rate will be less than half the peak bit rate. The maximum number of nodes is limited by the address space, and also by the total bus capacitance of 400 pF, which restricts practical communication distances to a few meters.

[edit] Reference design

The reference design, as mentioned above, is a bus with a clock (SCL) and data (SDA) lines with 7-bit addressing. The bus has two roles for nodes: master and slave:

Master node node that issues the clock and addresses slaves Slave node node that receives the clock line and address.

The bus is a multi-master bus which means any number of master nodes can be present. Additionally, master and slave roles may be changed between messages (after a STOP is sent). There are four potential modes of operation for a given bus device, although most devices only use a single role and its two modes:

master transmit master node is sending data to a slave master receive master node is receiving data from a slave slave transmit slave node is sending data to a master slave receive slave node is receiving data from the master

The master is initially in master transmit mode by sending a start bit followed by the 7-bit address of the slave it wishes to communicate with, which is finally followed by a single bit representing whether it wishes to write(0) to or read(1) from the slave. If the slave exists on the bus then it will respond with an ACK bit (active low for acknowledged) for that address. The master then continues in either transmit or receive mode (according to the read/write bit it sent), and the slave continues in its complementary mode (receive or transmit, respectively). The address and the data bytes are sent most significant bit first. The start bit is indicated by a high-to-low transition of SDA with SCL high; the stop bit is indicated by a low-to-high transition of SDA with SCL high. If the master wishes to write to the slave then it repeatedly sends a byte with the slave sending an ACK bit. (In this situation, the master is in master transmit mode and the slave is in slave receive mode.) If the master wishes to read from the slave then it repeatedly receives a byte from the slave, the master sending an ACK bit after every byte but the last one. (In this situation, the master is in master receive mode and the slave is in slave transmit mode.) The master then ends transmission with a stop bit, or it may send another START bit if it wishes to retain control of the bus for another transfer (a "combined message").

[edit] Message protocols

IC defines three basic types of messages, each of which begins with a START and ends with a STOP:

Single message where a master writes data to a slave; Single message where a master reads data from a slave; Combined messages, where a master issues at least two reads and/or writes to one or more slaves.

In a combined message, each read or write begins with a START and the slave address. After the first START, these are also called repeated START bits; repeated START bits are not preceded by STOP bits, which is how slaves know the next transfer is part of the same message. Any given slave will only respond to particular messages, as defined by its product documentation.

Pure IC systems support arbitrary message structures. SMBus is restricted to nine of those structures, such as read word N and write word N, involving a single slave. PMBus extends SMBus with a Group protocol, allowing multiple such SMBus transactions to be sent in one combined message. The terminating STOP indicates when those grouped actions should take effect. For example, one PMBus operation might reconfigure three power supplies (using three different I2C slave addresses), and their new configurations would take effect at the same time: when they receive that STOP. With only a few exceptions, neither IC nor SMBus define message semantics, such as the meaning of data bytes in messages. Message semantics are otherwise product-specific. Those exceptions include messages addressed to the IC general call address (0x00) or to the SMBus Alert Response Address; and messages involved in the SMBus Address Resolution Protocol (ARP) for dynamic address allocation and management. In practice, most slaves adopt request/response control models, where one or more bytes following a write command are treated as a command or address. Those bytes determine how subsequent written bytes are treated and/or how the slave responds on subsequent reads. Most SMBus operations involve single byte commands.

[edit] Messaging example: 24c32 EEPROM

One specific example is the 24c32 type EEPROM, which uses two request bytes that are called Address High and Address Low. (Accordingly, these EEPROMs aren't usable by pure SMBus hosts, which only support single byte commands or addresses.) These bytes are used to address bytes within the 32 kbit (4 kB) supported by that EEPROM; the same two byte addressing is also used by larger EEPROMs, such as 24c512 ones storing 512 kbits (64 kB). Writing and reading data to these EEPROMs uses a simple protocol: the address is written, and then data is transferred until the end of the message. (That data transfer part of the protocol also makes trouble for SMBus, since the data bytes are not preceded by a count and more than 32 bytes can be transferred at once. I2C EEPROMs smaller than 32 kbits, such as 2 kbit 24c02 ones, are often used on SMBus with inefficient single byte data transfers.) To write to the EEPROM, a single message is used. After the START, the master sends the chip's bus address with the direction bit clear (write), then sends the two byte address of data within the EEPROM and then sends data bytes to be written starting at that address, followed by a STOP. When writing multiple bytes, all the bytes must be in the same 32 byte page. While it's busy saving those bytes to memory, the EEPROM won't respond to further I2C requests. (That's another incompatibility with SMBus: SMBus devices must always respond to their bus addresses.) To read starting at a particular address in the EEPROM, a combined message is used. After a START, the master first writes that chip's bus address with the direction bit clear (write) and then the two bytes of EEPROM data address. It then sends a (repeated) START and the EEPROM's bus address with the direction bit set (read). The EEPROM will then respond with the data bytes beginning at the specified EEPROM data addressa combined message, first a write then a read. The master issues a STOP after the first data byte it NACKs rather than ACKs (when it's

read all it wants). The EEPROM increments the address after each data byte transferred; multibyte reads can retrieve the entire contents of the EEPROM using one combined message.

[edit] Physical layer

At the physical layer, both SCL & SDA lines are of open-drain design, thus, pull-up resistors are needed. Pulling the line to ground is considered a logical zero while letting the line float is a logical one. This is used as a channel access method. High speed systems (and some others) also add a current source pull up, at least on SCL; this supports faster rise times and higher bus capacitance. Transitions for data bits are always performed while the clock is low, transitions while it is high indicate start and stop bits. When one node is transmitting a logical one (i.e., letting the line float to Vdd) and another transmits a logical zero then the first node can sense this because the line is not in a logical one state it is not pulled up to Vdd. When used on SCL, this is called "clock stretching" and gives slaves a flow control mechanism. When used on SDA, this is called arbitration and ensures there is only one transmitter at a time. [edit] Clock stretching using SCL One of the more significant features of the IC protocol is clock stretching. An addressed slave device may hold the clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The master that is communicating with the slave will attempt to raise the clock to transfer the next bit, but must verify that the clock line was actually raised. If the slave is clock stretching, the clock line will still be low (because the connections are opendrain). The same is true if a second, slower, master tries to drive the clock at the same time. (If there is more than one master, all but one of them will normally lose arbitration.) Clock stretching is not used by masters in single-master configurations. When a master wants to slow the rate of data transfer, it just delays issuing the next clock edge. Some masters, such as those found inside custom ASICs may not support clock stretching; often these devices will be labeled as a "two-wire interface" and not IC. To improve its robustness, SMBus places limits on how far clocks may be stretched. Hosts and slaves adhering to those limits can't block access to the bus for more than a short time, which is not a guarantee made by pure IC systems. [edit] Arbitration using SDA Every master monitors the bus for start and stop bits, and does not start a message while another master is keeping the bus busy. However, two masters may start transmission at about the same time; in this case, arbitration occurs. Slave transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. In contrast to protocols (such as Ethernet) that use random back-off delays before issuing a retry, IC has a deterministic arbitration policy. Each transmitter checks the level of the data line (SDA) and compares them with the levels it

expects; if they don't match, that transmitter has lost arbitration, and drops out of this protocol interaction. For example, if one transmitter sets SDA to 1 (not driving a signal) and a second transmitter sets it to 0 (pull to ground), the result is that the line is low. The first transmitter then observes that the level of the line is different than expected, and concludes that another node is transmitting. The first node to notice such a difference is the one that loses arbitration: it stops driving SDA. If it's a master, it also stops driving SCL and waits for a STOP; then it may try to reissue its entire message. In the meantime, the other node has not noticed any difference between the expected and actual levels on SDA, and therefore continues transmission. It can do so without problems because so far the signal has been exactly as it expected; no other transmitter has disturbed its message. If the two masters are sending a message to two different slaves, the one sending the lower slave address always "wins" arbitration in the address stage. Since the two masters may send messages to the same slave addressand addresses sometimes refer to multiple slavesarbitration must continue into the data stages. Arbitration occurs very rarely, but is necessary for proper multi-master support. As with clockstretching, not all devices support arbitration. Those that do generally label themselves as supporting "multi-master" communication. SMBus uses arbitration in two additional contexts, both of which are used to pass information asynchronously from slaves to the (single) host. The first context is that hosts must support the "host notify protocol". That is a restricted multi-master mode in which slaves write messages to the reserved "SMBus Host" address (0x08), passing their address and two bytes of data. When two slaves try to notify the host at the same time, one of them will lose arbitration and need to retry. The other context is that pure slave devices which issue the SMBALERT# interrupt need to arbitrate when they reply to requests issued to the reserved "SMBus Alert Response Address" (0x0c), which is a kind of broadcast address. When they successfully reply with their own address, winning an arbitration in "slave transmit" mode, they stop raising that interrupt. In both cases, arbitration applies when the slave address is transmitted.

[edit] Timing diagram

Data transfer is initiated with the START bit (S) when SDA is pulled low while SCL stays high. Then, SDA sets the transferred bit while SCL is low (blue) and the data is sampled (received) when SCL rises (green). When the transfer is complete, a STOP bit (P) is sent by releasing the data line to allow it to be pulled up while SCL is constantly high.

[edit] Example of bit-banging the I2C Master protocol

unsigned start = 0; unsigned read_bit(void) { unsigned bit; /* Let the slave drive data */ READSDA(); I2CDELAY(I2CSPEED/2); /* Clock stretching */ while (READSCL() == 0); /* SCL is high, now data is valid */ bit = READSDA(); I2CDELAY(I2CSPEED/2); CLRSCL(); return bit; } void write_bit(unsigned bit) { if (bit) { READSDA(); } else { CLRSDA(); } I2CDELAY(I2CSPEED/2); /* Clock stretching */ while (READSCL() == 0); /* SCL is high, now data is valid */ /* If SDA is high, check that nobody else is driving SDA */ if (bit) { if (READSDA() == 0) { ARBITRATION_LOST(); } } I2CDELAY(I2CSPEED/2); CLRSCL(); } void start_cond(void) { if (start) { /* set SDA to 1 */ READSDA(); I2CDELAY(I2CSPEED/2); /* Clock stretching */ while (READSCL() == 0); } if (READSDA() == 0) { ARBITRATION_LOST(); } /* SCL is high, set SDA from 1 to 0 */ CLRSDA(); I2CDELAY(I2CSPEED/2); CLRSCL();

start = 1; } void stop_cond(void) { /* set SDA to 0 */ CLRSDA(); I2CDELAY(I2CSPEED/2); /* Clock stretching */ while (READSCL() == 0); /* SCL is high, set SDA from 0 to 1 */ if (READSDA() == 0) { ARBITRATION_LOST(); } I2CDELAY(I2CSPEED/2); start = 0; } unsigned tx(int send_start, int send_stop, unsigned char byte) { unsigned bit; unsigned nack; if (send_start) { start_cond(); } for (bit = 0; bit < 8; bit++) { write_bit(byte & 0x80); byte <<= 1; } nack = read_bit(); if (send_stop) { stop_cond(); } return nack; } unsigned char rx (int nak, int send_stop) { unsigned char byte = 0; unsigned bit; for (bit = 0; bit < 8; bit++) { byte <<= 1; byte |= read_bit(); } write_bit(nak); if (send_stop) { stop_cond(); } return byte; }

[edit] Applications

IC is appropriate for peripherals where simplicity and low manufacturing cost are more important than speed. Common applications of the IC bus are:

Reading configuration data from SPD EEPROMs on SDRAM, DDR SDRAM, DDR2 SDRAM memory sticks (DIMM) and other stacked PC boards Supporting systems management for PCI cards, through an SMBus 2.0 connection. Accessing NVRAM chips that keep user settings. Accessing low speed DACs and ADCs. Changing contrast, hue, and color balance settings in monitors (Display Data Channel). Changing sound volume in intelligent speakers. Controlling OLED/LCD displays, like in a cellphone. Reading hardware monitors and diagnostic sensors, like a CPU thermostat and fan speed. Reading real time clocks. Turning on and turning off the power supply of system components.

A particular strength of IC is that a microcontroller can control a network of device chips with just two general-purpose I/O pins and software. Peripherals can also be added to or removed from the IC bus while the system is running, which makes it ideal for applications that require hot swapping of components.[citation needed] Buses like IC became popular when computer engineers realized that much of the manufacturing cost of an integrated circuit design results from its package size and pin count. A smaller package also usually weighs less and consumes less power[citation needed], which is especially important in cellphones and portable computing. Those concerns multiply at the board level, where routing lots of signals in parallel takes up scarce space.

[edit] Operating system support

In Microsoft Windows, IC is implemented by the respective device drivers of much of the industry's available hardware. In Mac OS X, there are about two dozen IC kernel extensions which communicate with sensors for reading voltage, current, temperature, motion, and other physical status. In Linux, IC is handled with a device driver for the specific device, and another for the IC (or SMBus) adapter to which it's connected. Several hundred such drivers are part of current releases. FreeBSD, NetBSD and OpenBSD also provide an IC framework, with support for a number of common master controllers and sensors. In Sinclair QDOS and Minerva QL operating systems IC is supported via a set of extensions provided by TF Services. In AmigaOS the shared library i2c.library by Wilhelm Noeker allows IC access. eCos supports IC for several hardware architectures.

[edit] Development tools

When developing or troubleshooting systems using I2C, visibility at the level of hardware signals can be important.

[edit] IC host adapters

There are a number of hardware solutions for host computers, running Linux, Mac or Windows, IC master and/or slave capabilities. Most of them are based on Universal Serial Bus (USB) to IC adaptors. Not all of them require proprietary drivers or APIs. IC Host Adapters The 25 IC Adapter Philips Parallel Printer Port Adaptor USB-I2C Adapter Connii MM 2.0 I2C USB 2.0 Host Adapter Aardvark I2C/SPI Host Adapter AnaGate I2C-Ethernet Gateway The Bus Pirate BusPro I2C CAS-1000 I2C/SMbus Analyzer/Exerciser CY3240-I2USB I2C2PC Host Adaptor I2C-Tiny-USB I2C Xpress iPort/USB I2C Bus Adapter Master Master, Multimaster, Slave Master Master, Multimaster Master, Multimaster, Slave Master, Multimaster Master Master, Multimaster Master, Multimaster, Slave Master Master, 3 Buses Master Master, Multimaster Master/Slave/Std/Fast I2C Modes Manufacturer Open Source Philips Semiconductors Byvac telos Total Phase Analytica Open source + Hardware Corelis Corelis Cypress Semiconductor I2CChip Open Source + Hardware Byte Paradigm MCC Jupiter Instruments National Instruments Host OS / Software Supported Mac, Linux (limited hardware support, see documentation) Linux Windows,Linux Windows, Labview Linux, Windows, Mac Linux, Windows, PLC All, USB serial terminal Windows Windows Windows All OS - simple ASCII commands Linux, Windows, Mac Windows GUI, TCL/tk and C/C++ interfaces Windows, Linux Windows Windows, maybe others

JI-300 I2C Bus Adapter Master/Multi-Master USB-8451 Master

(Multi)Master/Slave/Tracer SUB-20 Multi Interface Master, Multimaster, Adapter Slave U2C-12 I2C/SPI Master Adapter UCA93LV 400KHz I2C-Bus Comms Master/Slave/Multimaster Adapter Tracii XL 2.0 ELV USB-I2C-Interface Master USB-I2C USB I2C/IO Interface Board userial USB to I2C/SPI/GPIO bridge TIMS-0102 USB to I2C/SPI U401/U421 USB Interface USB2I2C Adapter ZIO Master Master, Multimaster Master Master Master Master Master

telos Dimax Xdimax Calibre UK Ltd ELV Elektronik AG Devantech DeVaSys Open Source + Hardware Jova Solutions USBmicro USBIO Tech Zilogic Systems

Windows, Labview Linux, Windows, Mac, DOS, MATLAB Linux, Windows, Mac Windows Linux, Windows, Mac, (simple ASCIICommands) Linux, Windows, Mac, OpenBSD Windows Linux, Windows, Mac Windows, Linux, and LabVIEW Drivers Linux, Windows, Mac Linux, Windows and LabVIEW Drivers Linux. Windows

Serial to IC bridges are also available, for systems with no USB ports.

[edit] IC protocol analyzers

IC Protocol Analyzers are tools which sample an IC bus and decode the electrical signals to provide a higher-level view of the data being transmitted on the bus. The following table is sorted by manufacturer. IC Protocol Analyzers IC Xpress : Analzyer and Host Adapter BusPro-I : Price Hos Manufactur / as- t Host OS, SW, API er of Bus Byte Paradigm Corelis IC Speeds

Bus List

Notes

EUR 450, US Windows,Tcl/Tk,C/C IC 2010/ B ++ 9 USD US Windows IC

Host up to Adapter 1 MHz (see above) up to .

IC Analyzer, Monitor, Debugger, Programm er CAS1000I2C/E : IC Analyzer, Corelis Exerciser, Emulator, Programm er JI-216 : I2C Bus Monitor IC/SMBu s Monitor Beagle : IC/SPI Protocol Analyzer EasyI2C : Low Cost Protocol Analyzer

1250, B 2010/ HS 9

5 MHz

USD US 7950, B Windows 2010, HS 9

IC,JTAG

up to Script,Sco 5 MHz pe

USD Jupiter 339, Instruments 2010/ 9 USD 895, MCC 2010/ 9 USD 300, Total Phase 2010/ 9 USD Xtreme 99, Engineering 2010/ LLC 9

US Windows B

IC

up to 3.7 MH . z up to 100 KHz

RSWindows 232

IC,SMBus,

Handheld

US Windows,Linux,Mac IC,SPI B

up to . 4 MHz

US Windows B

up to IC,TWI,SMB 400 us KHz

[edit] Logic analyzers

When developing and/or troubleshooting the IC bus, examination of hardware signals can be very important. Logic analyzers are tools which collect, analyze, decode, store signals so people can view the high-speed waveforms at their leisure. Logic analzyers display time-stamps of each signal level change, which can help find protocol problems. Most logic analyzers have the capability to decode bus signals into high-level protocol data and show ASCII data.

[edit] Revisions
The original IC system was created in the early 1980s as a simple internal bus system for building control electronics with various Philips chips.

In 1992 the first standardized version was released, which added a new fast mode at 400 kbit/s and a 10-bit addressing mode to increase capacity to 1008 nodes. Version 2.0 from 1998 added high-speed mode at 3.4 Mbit/s with reduced voltage and current requirements that saved power. Version 2.1[2] from 2000 is a minor cleanup of version 2.0. Version 3[3] from 2007 adds Fast mode plus (or Fm+) and a device ID mechanism, and is the latest standard.

[edit] Limitations
The assignment of slave addresses is one weakness of IC. Seven bits is too few to prevent address collisions between the many thousands of available devices, and manufacturers rarely dedicate enough pins to configure the full slave address used on a given board. Three pins is typical, giving only eight choices of slave address. While some devices can set multiple address bits per pin,[4][5] e.g. by using a spare internal ADC channel to sense one of eight ranges set by an external voltage divider, usually each pin controls one address bit. Manufacturers may provide pins to configure a few low order bits of the address and arbitrarily set the higher order bits to some value based on the model. This limits the number of devices of that model which may be present on the same bus to some low number, typically between two and eight. That partially addresses the issue of address collisions between different vendors. Ten-bit IC addresses are not yet widely used. [1], and many host operating systems don't support them. Neither is the complex SMBus "ARP" scheme for dynamically assigning addresses (other than for PCI cards with SMBus presence, for which it is required). Automatic bus configuration is a related issue. A given address may be used by a number of different protocol-incompatible devices in various systems, and hardly any device types can be detected at runtime. For example 0x51 may be used by a 24LC02 or 24C32 EEPROM, with incompatible addressing; or by a PCF8563 RTC, which can't reliably be distinguished from either (without changing device state, which might not be allowed). The only reliable configuration mechanisms available to hosts involve out-of-band mechanisms such as tables provided by system firmware which list the available devices. Again, this issue can partially be addressed by ARP in SMBus systems, especially when vendor and product identifiers are used; but that hasn't really caught on. The rev 03 version of the IC specification adds a device ID mechanism, which at this writing has not had time to catch on either. IC supports a limited range of speeds. Hosts supporting the multi-megabit speeds are rare. Support for the Fm+ one-megabit speed is more widespread, since its electronics are simple variants of what is used at lower speeds. Many devices don't support the 400 kbit/s speed (in part because SMBus doesn't yet support it). IC nodes implemented in software (instead of dedicated hardware) may not even support the 100 kbit/s speed; so the whole range defined in the specification is rarely usable. All devices must at least partially support the highest speed used or they may spuriously detect their device address. Devices are allowed to stretch clock cycles to suit their particular needs, which can starve bandwidth needed by faster devices and increase latencies when talking to other device addresses. Bus capacitance also places a limit on the transfer speed, especially when current sources aren't used to decrease signal rise times. Because of those limits (address management, bus configuration, speed), few IC bus segments have even a dozen devices. It's common for systems to have several such segments. One might

be dedicated to use with high speed devices, for low latency power management. Another might be used to control a few devices where latency and throughput aren't important issues; yet another segment might be used only to read EEPROM chips describing add-on cards (such as the SPD standard used with DRAM sticks).

[edit] Derivative technologies

IC is the basis for the ACCESS.bus, the VESA Display Data Channel (DDC) interface, the System Management Bus (SMBus), Power Management Bus (PMBus)and the Intelligent Platform Management Bus (IPMB, one of the protocols of IPMI). These implementations have differences in voltage and clock frequency ranges, and may have interrupt lines. TWI (Two Wire Interface) or TWSI (Two-Wire Serial Interface) is essentially the same bus implemented on various system-on-chip processors from Atmel and other vendors.[6] Vendors use the name TWI, even though IC is not a registered trademark. Trademark protection only exists for the respective logo (See upper right corner) and patents on IC have now lapsed.

[edit] See also

1-Wire Bus IS - Common for A/D and D/A converters Serial Peripheral Interface Bus (SPI) - Common in flash memories Serial Presence Detect (SPD) - Common in DRAM memories System Management Bus (SMB) - Common in PC motherboards UNI/O Bus List of network buses

[edit] References
1. 2. 3. 4. ^ IC Licensing Information ^ Revision 2.1 of the I2C specification. ^ Version 03 of the I2C specification. ^ Maxim's MAX7314 uses a common purely-digital low/high/SDA/SCL scheme to configure four addresses per address pin. 5. ^ TI's UCD9112 uses two ADC channels to select any valid 7-bit address. 6. ^ avr-libc: Example using the two-wire interface (TWI)

[edit] External links

Detailed Introduction, Primer Tackling I2C Development Complexities Using Innovative Tools Advanced IC Bus Analysis Webinar What exactly is IC? IC Background

IC Bus / Access Bus Using the IC Bus with Linux Proven Implementations of the IC Bus OpenBSD iic(4) manual page Lm-sensors, Linux package which supports sensors using the IC bus, among others. massmind IC page Source code, samples and technical information for using IC with PC, PIC and SX microcontrollers. Serial buses information page IC Bus Technical Overview and Frequently Asked Questions The Bus Buffer Resource. For 2-wire buses such as IC, SMBus, PMBus, IPMB & IPMI IC Protocol Texas Instruments' IC Logic Page A commercial hardware implementation of IC written in VHDL OpenCores open source hardware implementation, in Verilog and VHDL Howto program the IC protocol using the Z80 PIO Introduction to IC Bus Introduction to SPI and I2C protocols I2C Protocol Decode software Beginner's guide to using Arduino with IC devices, including worked examples

This I2C tutorial shows you how the I2C protocol works at the physical bit level. It only discusses single master mode (a single controlling device) as this is the most common use for I2C in a small system.

IC (pronounced I-squared-C) created by Philips Semiconductors and commonly written as 'I2C' stands for Inter-Integrated Circuit and allows communication of data between I2C devices over two wires. It sends information serially using one line for data (SDA) and one for clock (SCL). Note: You can find Master mode soft I2C routines in the RTC project.

Master and slave

The phillips I2C protocol defines the concept of master and slave devices. A master device is simply the device that is in charge of the bus at the present time and this device controls the

clock and generates START and STOP signals. Slaves simply listen to the bus and act on controls and data that they are sent. The master can send data to a slave or receive data from a slave - slaves do not transfer data between themselves.

Multi Master
Multi master operation is a more complex use of I2C that lets you have different controlling devices on the same bus. You only need to use this mode if you have more than one microcontroller on the bus (and you want either of them to be the bus master). Multi master operation involves arbitration of the bus (where a master has to fight to get control of the bus) and clock synchronisation (each may a use a different clock e.g. because of separate crystal clocks for each micro). Note: Multi master is not covered in this I2C tutorial as the more common use of I2C is to use a single bus master to control peripheral devices e.g. serial memory, ADC, RTC etc.

Data and Clock

The I2C interface uses two bi-directional lines meaning that any device could drive either line. In a single master system the master device drives the clock most of the time - the master is in charge of the clock but slaves can influence it to slow it down (See Slow Peripherals below). The two wires must be driven as open collector/drain outputs and must be pulled high using one resistor each - this implements a 'wired AND function' - any device pulling the wire low causes all devices to see a low logic value - for high logic value all devices must stop driving the wire. Note : If you use I2C you can not put any other (non I2C) devices on the bus as both lines are used as clock at some point (generation of START and STOP bits toggles the data line). So you can not do something clever such as keeping the clock line inactive and use the data line as a button press detector (to save pins). You will often will find devices that you realise are I2C compatible but they are labelled as using a '2 wire interface'. The manufacturer is avoiding paying royalties by not using the words 'I2C'! There are two wires (three if you include ground!) :
I2C Turorial: Signals definition SDA : Serial Data SCL : Serial Clock I2C Turorial: end of signal definition I2C Tutorial : Typical SDA and SCL signals

Speed
Standard clock speeds are 100kHz and 10kHz but the standard lets you use clock speeds from zero to 100kHz and a fast mode is also available (400kHz - Fast-mode). An even higher speed (3.4MHz - High-speed mode) for more demanding applications - The mid range PIC won't be up this mode yet! Note that the low-speed mode has been omitted (10kHz) as the standard now specifies the basic system operating from 0 to 100kHz.

Slow peripherals
A slow slave device may need to stop the bus while it gathers data or services an interrupt etc. It can do this while holding the clock line (SCL) low forcing the master into the wait state. The master must then wait until SCL is released before proceeding.

Data transfer sequence

A basic Master to slave read or write sequence for I2C follows the following order:
I2C Tutorial : I2C basic command sequence.

1. Send the START bit (S). 2. Send the slave address (ADDR). 3. Send the Read(R)-1 / Write(W)-0 bit. 4. Wait for/Send an acknowledge bit (A).

5. Send/Receive the data byte (8 bits) (DATA). 6. Expect/Send acknowledge bit (A). 7. Send the STOP bit (P).

I2C Tutorial : end of I2C basic command sequence.

Note: You can use 7 bit or 10 bit addresses. The sequence 5 and 6 can be repeated so that a multibyte block can be read or written. Data Transfer from master to slave
I2C Tutorial : Instruction sequence data from master to slave

A master device sends the sequence S ADDR W and then waits for an acknowledge bit (A) from the slave which the slave will only generate if its internal address matches the value sent by the master. If this happens then the master sends DATA and waits for acknowledge (A) from the slave. The master completes the byte transfer by generating a stop bit (P) (or repeated start). Data transfer from slave to master
I2C Tutorial : Instruction sequence data from slave to master

A similar process happens when a master reads from the slave but in this case, instead of W, R is sent. After the data is transmitted from the slave to the master the master sends the acknowledge (A). If instead the master does not want any more data it must send a not-acknowledge which indicates to the slave that it should release the bus. This lets the master send the STOP or repeated START signal.

Device addresses
Each device you use on the I2C bus must have a unique address. For some devices e.g. serial memory you can set the lower address bits using input pins on the device others have a fixed

internal address setting e.g. a real time clock DS1307. You can put several memory devices on the same IC bus by using a different address for each. Note: The maximum number of devices is limited by the number of available addresses and by the total bus capacitance (maximum 400pF). General call The general call address is a reserved address which when output by the bus master should address all devices which should respond with an acknowledge.Its value is 0000000 (7 bits) and written by the master 0000000W. If a device does not need data from the general call it does not need to respond to it.
I2C Tutorial : Reserved addresses.
0000 0000 0000 0000 0000 1111 1111 000 001 010 011 1XX 1XX 0XX 1 X X X X X X START byte - for slow micros without I2C h/w CBUS address - a different bus protocol Reserved for different bus format Reserved for future purposes Hs-mode master code Reserved for future purposes 10-bit slave addressing

I2C Tutorial : End of reserved addresses.

Most of these are not that useful for PIC microcontrollers except perhaps the START byte and 10 bit addressing.

START (S) and STOP (P) bits

START (S) and STOP (P) bits are unique signals that can be generated on the bus but only by a bus master. Reception of a START bit by an I2C slave device resets its internal bus logic. This can be done at any time so you can force a restart if anything goes wrong even in the middle of communication. START and STOP bits are defined as rising or falling edges on the data line while the clock line is kept high.
I2C Tutorial : text definition of START and STOP signals
START condition (S) STOP condition (P) SCL = 1, SDA falling edge SCL = 1, SDA rising edge

I2C Tutorial : end of text definition of START and STOP signals

The following diagram shows the above information graphically - these are the signals you would see on the I2C bus.
I2C Tutorial : end of definition of START and STOP signals I2C Tutorial : START (S) and STOP (P) bits.

I2C Tutorial : end of definition of START and STOP signals

Note : In a single master system the only difference between a slave and a master is the master's ability to generate START and STOP bits. Both slave and master can control SDA and SCL.

Repeated START (Sr)

This seems like a confusing term at first as you ask yourself why bother with it as it is functionally identical to the sequence : S ADDR (R/W) DATA A P The only difference is that for a repeated start you can repeat the sequence starting from the stop bit (replacing the stop bit with another start bit). S ADDR (R/W) DATA A Sr ADDR (R/W) DATA A P and you can do this indefinitely. Note: Reception of both S or Sr force any I2C device reset its internal bus logic so sending S or Sr is really resetting all the bus devices. This can be done at any time - it is a forced reset. The main reason that the Sr bit exists is in a multi master configuration where the current bus master does not want to release its mastership. Using the repeated start keeps the bus busy so that no other master can grab the bus. Because of this when used in a Single master configuration it is just a curiosity.

Data
All data blocks are composed of 8 bits. The initial block has 7 address bits followed by a direction bit (Read or Write). Following blocks have 8 data bits. Acknowledge bits are squeezed in between each block. Each data byte is transmitted MSB first including the address byte. To allow START and STOP bit generation by the master the data line (SDA) must not be changed while the clock (SCL) is high - it can only be changed when the clock is low.

Acknowledge
The acknowledge bit (generated by the receiving device) indicates to the transmitter that the the data transfer was ok. Note that the clock pulse for the acknowledge bit is always created by the bus master. The acknowledge data bit is generated by either the master or slave depending on the data direction. For the master writing to a slave (W) the acknowledge is generated by the slave. For the master receiving (R) data from a slave the master generates the acknowledge bit.
I2C Tutorial : Definition of ACK bits
Acknowledge Not acknowledge 0 volts High volts

I2C Tutorial : End of definition of ACK bits

ACK data master --> slave In this case the slave generates the acknowledge signal. When a not-acknowledge is received by the bus master the transfer has failed and the master must generate a STOP or repeated START to abort the sequence. ACK data slave --> master In this case the master generates the acknowledge signal. Normally the master will generate an acknowledge after it has received data but to indicate to the slave that no more data is required on the last byte transfer the master must generate a 'notacknowledge'. This indicates to the slave that it should stop sending data. The master can then generate the STOP bit (or repeated START).

I2C Tutorial : Specifics for the 16F88

Pin configuration To use the I2C mode in the 16F88 the SDA and SCL pins must be initialised as inputs (TRIS bit = 1) so that an open drain effect is created. By setting them as inputs they are not driving the wires and an external pull up resistor will pull the signals high. Slave mode The 16F88 fully implements all slave functions except general call. The general call function does not really matter as it is quite specialised commanding all devices on the bus to use some data. A low output is generated by driving the signal line low and changing the pin direction to an output. A high output is generated by changing the pin direction to an input so that the external resistor pulls the signal high. In slave mode this action is done for you by the SSP module (the outputs of the register at SDA and SCL are driven low automatically - regardless of the state of the register value). Master mode Basically there is very limited master mode functionality. There are two elements that are provided:

Interrupts Pin control

16F88 Interrupts

There are two interrupts that activate on reception of either a START or STOP condition. These two interrupts are only useful in a multi master mode system where it is necessary for the nonmaster device to detect the start and stop conditions. So for a single master system they are of no use at all!
16F88 Pin control

Note When the SSP module is active SDA and SCL output are always set at zero regardless of the state of the register values. So all you have to do is control the port direction. In master mode (16F88) SDA and SCL must be controlled using software.

I2C Tutorial : Specifics for 16F877A

It does it all for you!

Full master mode. Full slave mode. Full general call.

Note if you want a chip with full master and slave mode operation look for the MSSP module in a PIC chip e.g. 16F877A - then you won't need more software - just enough to drive the module.