Embedded Programmable Web-based ECG Monitoring & etection System Using a Fast Algorithm

http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4435068

Design of a High-Speed Differential Frequency-toVoltage Converter and Its Application

This paper appears in: Circuits and Systems I: Regular Papers, IEEE Transactions on Issue Date: April 2008 Volume: 55 Issue:3 On page(s): 766 - 774 ISSN: 1549-8328 References Cited: 22 INSPEC Accession Number: 9944377 Digital Object Identifier: 10.1109/TCSI.2008.916397 Date of Current Version: 02 May 2008 Sponsored by: IEEE Circuits and Systems Society

ABSTRACT This paper presents a new algorithm and circuit implementation for high-speed frequency-to-voltage converters (FVC). The proposed system overcomes the deficiencies of a previously reported converter and can operate about 20 times faster. To validate this FVC and show its usefulness, it was used in the design of a frequency locked loop. For the design of this loop, it was found that existing analytical models were incomplete in that they neglect the delay associated to frequency measurements. We proposed a new model which, unlike previous work, shows that frequency locked loops can potentially be unstable. Simulations confirm this fact and also show that the proposed implementation can operate at 5 KHz. To validate the results, a prototype circuit has been fabricated in a 0.18mum CMOS technology. Tests performed on the prototype show that it runs reliably at 3.84 GHz and consumes 77.4 mW with a 1.8-V power supply when biasing circuitry is included.

This paper appears in: Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on Issue Date: May 30 2010-June 2 2010 On page(s): 3088 - 3091 Location: Paris Print ISBN: 978-1-4244-5308-5 INSPEC Accession Number: 11463305 Digital Object Identifier: 10.1109/ISCAS.2010.5537986 Date of Current Version: 03 August 2010

ABSTRACT

This paper presents a low-cost CMOS voltage-to-frequency converter (VFC) with almost full-scale input operating range for front-end smart sensor interfaces in wireless sensor networks (WSN) applications. The proposed VFC, designed in a 0.35m CMOS technology supplied at 3 V, is a cost-effective circuit, exhibiting at the same time high performance characteristics: it operates with a power consumption below 0.8 mW at output frequencies ranging from 0.1 MHz to 2.7 MHz with an error below 4 % given a 0.1-2.7 V input (1 MHz/V sensitivity).
This paper appears in: Computing, Communication, Control, and Management, 2008. CCCM '08. ISECS International Colloquium on Issue Date: 3-4 Aug. 2008 On page(s): 123 - 126 Location: Guangzhou Print ISBN: 978-0-7695-3290-5 INSPEC Accession Number: 10202757 Digital Object Identifier: 10.1109/CCCM.2008.106 Date of Current Version: 29 August 2008

ABSTRACT This paper designed a DC motor speed control system. The controller is ARM S3C2410, and the operating system is muC/OS-II, a real time operating system. Designed a closed loop system of motor speed control, adopted the algorithm of PWM to control the armature voltage, and motor speed is controlled by regulating, of armature voltage. The system has a good respondence.