Low voltage, low power, high performance current

mirror for portable analogue and mixed mode

appIications
S.S.Rajput and S.S.Jamuar

Abstract: A novel current mirror (CM), suitable for operation at low voltage levels is presented. The
mirror has high input and high output voftage swings. Adaptive current biasing is introduced for
minimising the effects of offset current. A compensation technique has been used to increase the
bandwidth. This makes the CM structure attractive for portable, high frequency circuit applications.
P-SPICE simulations, based on models for 1 . 2 technology,
~ validate the operation of the proposed
current mirror for currents from 1 to 500@ with 1.2GHz bandwidth.

1 Introduction and less than 1.7V for input current ranging from 200 to
500pA with output impedance of approximately 1MQ.
The demand for portability has made low power usage a
key factor in integrated circuit design. Low power circuits 2 LVCM topology
normally find use in both digital and analogue mobile
systems. Non-mobile applications also prefer to have low The simple CM topology shown in Fig. l a requires input
voltage (LV) operation to eliminate instrument-cooling voltage (VJ of at least one Vt, and is unsuitable for any
requirements. LV applications. The modified CM (Fig. Ih), which oper-
A CM is a common building block both in analogue and ates at low voltage. incorporates a level shifter PMOS tran-
mixed mode VLSI circuits. Almost all high impedance sistor M4 (biased through a current at input port.
CMs reported so far [I-31 need high input voltages, which For this structure, we have
give them the capability of high output voltage signal Vd51 = V,l - vis4 (1)
swing. The input voltagc requirement for these CMs
depends solely on the threshold voltage (V,) of the input where Vds,andVg5, are the drain to source and gate to
MOSFET, thus making them unsuitable for low voltage source voltages for MI. L'T,4 is the gate to source voltage
opcration. New low voltage CM (LVCM) circuits. there- for M4.
fore, need to be investigated for getting high signal swings
at input and output terminals. A few CM topologies with
reduced input voltage requirements have becn rcported in
[4, 51, where either a level shifter or a bulk-driven approach
[1] has been used. The CM proposed in [4] is capable of
operating at a low supply of 1.3V, but it has limited cur-

11~
rent range (< 150pA) with a bandwidth of l00MHz. The
CM proposed in [I] has limited current range (< lOOpA), I I

while that proposed in [5] is not suitable for high frequency "ss
applications.
A novel LVCM with adaptive biasing and high input
and high output voltage swings is presented in this paper.
A&aptive biasing enhances the input signal swing capability
M4, ~-
a

'bias1 , ~ 'out

and reduces the undesirable offset current. The use of

capacitive and resistive compensation gives a bandwidth of
1.2GHz. The proposed LVCM can operate at a bias volt- Mi M2
age less than 1.2V for an input current less than 200p-4;
r-' '7
0E,2001 I "ss
IEE Pr0Creding.s onlinc no. 20010441
DOI: IO. Io49iipcds:200 10441 b
Fig. 1 chf structurm
Paper f i t received 20th September 2000 and in revised foiin 2Ylh March 2001 a Conventional CM structure
h Conventional 1c\.cl shiftcd CM struclurc
S.S. Rajput was with the Indian Institute of Technology and is now with the
Thin Film Teclinology Group, National Physical Laboratory. Dr K.S.
Krishnan Road. New Delhi, 110012,India M4 is operated in sub-threshold region and Vg,T4is
S.S. Jamuar is with the Department of Electrical Engheerhg, Indian Institute approximately 0.6 V. It is required to have a minimum V,,,
of Technoloa, Haur mas,New Delhi. 110016. Tndia equal to at least one V, to operate M1 in either linear/
IEE Proc.-Cir.cuifr Dcviws Sysl.. Vu/. 148, Nu. 5, Uclober 2001 273
saturation region. If Vds,equals 0.2V, then M1 operates
in the saturation region. However, M4 operates in the
sub-threshold region for the entire input current (I,,,) range.
The operation of MI and M2 depends on I,, and their
aspect ratios ( WIL).Hence, when I , < 1 .OpA, MI operates
in the sub-threshold region and when I, exceeds l.OpA,
M1 operates in the saturation region.
2. I Operation in sub-threshold region
At low input currents, M1 and M2 operate in the sub-
threshold regions and the input voltage present due to the
injection of I, is given by
where V, is the thermal voltage. IDOLand ION are process
parameters, (W/L)represents transistor aspect ratio, and
lies between 1.2 and 2.0.
As I, increases, both M1 and M2 enter into the satwa-
tion region and the circuit analysis carried out in the
following Sections assumes that M1 and M2 are in the
saturation regions.
2.2 Proposed LVCM struclure
The CM structures shown in Fig. I do not have high
output resistance. The LVCM structure shown in Fig. 2 is
based on the triode transconductor structure [6], and is
expected to increase the output resistance. The input
current Ijn is pumped into the drain of M1. The bias
current of M4 is kept small so that M4 operates in the sub-
threshold region and MI is in the saturation region. The
transconductance (gml)and channel conductance (gdl) of
M1 decide the input impedance (Rh). Here, M4 provides
the requisite gate bias for M1 and M2 while M5 provides
suitable bias for M3. V,, is given by
where AV, (= Kp V,) is the mismatch between the
~
threshold voltages of MI and M4 and PI represents the
transconductance parameter for M1.
Fig. 2
6
"SS
Prnpsed high output wedance L VCM
V,, and VgJ2 are equal, but V,, depends on the applied
bias voltage ( VB),output current (Iout)and the bias current
of M5 (Ibws2). We choose Ihrac2to be IO@, which ensures
that M5 operates in the linear region for entire range of V,
because the drain gate voltage of MS equals VgS7.
For a current flow through M3 and M2, lower V,
implies lower Vdy2.This causes higher Vgsj than that
required for Ihlar2
to flow. V,, depends on the gate bias of
M3 and is at least equal to V,,, + VIH.These conditions
214
ensure that MS operates in the linear region. Also, V,,,
increases as VB is increased and M3 has to pump IoUtbut
drain source voltage of M3 is small and inadequate for the
purpose. Hence, it requires higher gate source bias, which
equals the difference of applied voltage at source of MS
(VC) and the drain voltage of M2 (= V, - Vdsj).V, is
normally taken as VDD itself. Now, V, divides between Vds2
and Vds3as:
When V, is small, the above ratio is high and VdY2 equals
V,. With the increase in V,, Vds,rises as M5 enters into the
saturation from the linear region. When Vds2increases
further, Vgv3decreases to a minimum value where further
decrease in VEJ3will not allow I,,( to flow. Now the
increase in VdJ2 stops and remains fairly independent and
Vds3starts rising. M3 enters into saturation, resulting M5 to
be always in the linear region.
The input impedance (R,) and the output impedance
(4?,t) are given by
where gd and gcnrepresent the output conductances of M2
and M3, while gwL,and gnz3represent transconductances for
M1 and M3, respectively. Similarly, the minimum output
voltagc necessary for CM operation is equal to:
= Vd,a(min)
Voul(niin) + Vdta(min) (7)
3 Adaptive biasing technique
For the LVCM of Fig. 2, a minimum Ibras, is required and
V, is dependent of both I,, and IbiaJ1.If J n is increased,
then V,, also increases. But this increasc can be reduced to
a smaller value by increasing Ibmsl.It is possible to increase
Il,larlproportional to 6, by using the CMs obtained using
M6, M7 and M8 (Fig. 3). The current through M8 is pro-
portional to I,, and is Ibrasl.
"dd
I I
M7
-,
mi^
Fig. 3 Proposed ABLP'CM structure
vss
'bias2
The gate source voltage for M2 (VgJ is given by
where Vcp4is the threshold voltage of M4.
IEE Proc-Circuit,s Devices Syst., Vol. 148, hro. 5. October 2001
 We find that Vg,s2depends on V,,, and I,,,. For low
input current (41i5 1pA), Vds2is nearly equal to zero volts
and IhjrrSl solcly decides VKsz. ZbjlrSldrives Vgs2to bc near V,,
even Tor zero / j , l . V,, will also be zero, but Vds2increases
independently with VB. Under this condition, a current
flows through M2 (even though f j v is zero), because
decides the gate bias for M2 and Vd5,increases independ-
ently with V,. This condition drives M2 into the sub-
threshold region and a small current, known as the offset
current (IofJTez), flows through M2. As f,,jo,ylincreases, the
gate source bias of M2 increases, although q,zis still negli-
gible (= 0.0V for Zi,L < 1U). This causes fo,fsel to increase.
Thus, I,,, restricts the increase in ZbjNgl.
Thus two contradictory requircments emerge (i.e. that
f,,, should be increased to keep V, low and at the same
time should be decreased to keep lorreflow). In the
design of an adaptively biased LVCM (ABLVCM), Jl,jil,sIis
kept low, when , Z is low and is increascd for higher I,.
Higher IOilr,sl imparts low V, at higher Gn and lower Ihjrrslis
necessary at low 1, to have low Zoffi,,. Fig. 4 gives the
values of offset current under different operating condi-
tions.
We find that Ifs,, can also bc minimised by matching.
the threshold voltages of the PMOS and NMOS transis-
tors, but cannot be made zero. As shown in Fig. 4, opera-
tion of thc PMOS transistor in the sub-threshold region
reduces by a factor of 3. We have used this concept in
the proposed ABLVCM structure.
4 Circuit modelling
The goal of circuit modelling is to obtain the functional
relationship among the input and output variables, which
depends upon some physical and bias parameters. Hybrid
(h) parameters to model the small-signal behaviour for the
LVCM are given in Fig. 5, where
c
p cgbl+cgs2 +cg54 +Cgdl (11)
c,= cp+ c,, (12)
and g is the conductance connected between gates of M1
and M2.
5 Frequency enhancement
The high frequency response of the LVCM is described by
the parameter h2, (Fig. 5). The addition of an external
capacitor C,, between the gate and source of M4 decreases
the input capacitance C,, (cqn. 9) and increases C ,
(eqn. 12). This results m shifting the pole-location away
from the imaginary axis in the complex planc and the
bandwidth decreases. But addition of g, as proposed in [7],

Parameter Operating conditions

M1, M2, and M4 M1 and M 2 (& sub-threshold) and

(in sub-threshold) M4 (in saturation)

Fig. 4 under dtfiwit opemting conditions

Fig.5 Hybrid (h)parunwtrrs

I h B Proc.-Circuits D t v i r e , ~Sysl., Vol. 148, hro. 5 , Octoher 2001 215
increases g!. This compensates for increase in C,. When gl -1.5
>> g?,,, reduces to following: T c f ( ~ o ? L=
t ) __ (19)
T
This gives quite low TC, (Iout),equal to -5OOppmI"C at
room temperature.
We find that C,, primarily decides the bandwidth of
ABLVCM if gCnis constant. Reducing C,, can increase the 8 Simulation results
bandwidth of ABLVCM. This is achieved by addition of
the external capacitance Ce,. The parameters such as R,,,, R,,,l, bandwidth and
which should be bias insensitive, decide the performance of
6 Sensitivity analysis the ABLVCM. The CM should also have high input and
output voltage swing capabilities. The circuits have been
Sensitivity analysis of the CM is carried out to find the var- simulated using level 3 SPICE parameters for 1 . 2 tech-
~
iation of thc output current (Iou,)for the variations in vari- nology with supply voltage of f l V . The (WIL) ratios for
ous critical device parameters. I,,,, is given by various MOSFETS are given in Table 1.
PCO x Table 1: Aspect ratios
IOzLi
=
2L
~

Device Aspect ratio Figure

number Type (W Fm/l pm) numbeds)

M1,MZ NMOS 8412.4 2,3

M3 NMOS 60/1.2 2,3
M4, M5 PMOS 18/1.2 2.3
The sensitivity of I,,, was evaluated with respect to various
parameters. The following observations are made from the M6 NMOS 8.412.4 3
sensitivity calculations. Ml PMOS 120/1.2 3
For Vds2less than 2.0V, the sensitivity of the output M8 PMOS 2.414.8 3
current to VdA2change is almost negligible. Any variations
occurring in the transistor dimensions (W and L) have 8.1 LVCM
immediate reflection on I,,,. The sensitivity of I,,, to I,,zncl P-SPICE simulations were carried out for Ihlarl and lbmS2 of
change is almost negligible and the sensitivity of lour to the l0OpA and 10p.4 respectively, for 4, between lpA and
threshold voltage change is quite high, as is expected from SOOp.4. Input voltage (V,)is plotted in Fig. 6 for various
any CM structure. values of I,,,. V,, required is 0.8V as against 1.36V for
To calculate sensitivity of I,,, to I,,, we assume Kl = conventional CM for S00pA of IOU,.This voltage is still
K -AK,K2 = K + AK, VI,= V, -AV, and V,, = V, + AV,. higher for low voltage CM applications. For I,,, < 200p.4,
The current I,,, is given by the circuit operates with V,, < 0.SV. The variation of V,, as
- 1

2
Iout = 7 (/2 - 2 w ) - (15)

For = p2 we get

and the sensitivity of I,,,, to I, is dependent on variation in

K.

7 Temperature dependence ~ ~ ~ " 0.1

" " ' " 0.2
" ' " ' '0.3' - 0.4
" " " 0.5
input current lin, mA
Several of MOSFET parameters such as mobility (p) and Fig. 6 K,,uguinst I .
the threshold voltage ( VJ are temperature dependent and (i) Convcnlional CM;
(ivjpuoposrd ARLVCM
6)ciu?vcrcteuisiics
simple CM structure; (iii) proposed LVCM stIucture;
their effects on CM performance need to be evaluated. For
the ABLVCM under consideration, I,,,,, is given by -0

- -5

(17)
Assuming the temperature changes in A V , to be zero, the
fractional tcmperature coefficicnt (TCh is givcn as
21i2ab
TCj(I0ut) = -1 5
T
~ + Q a
111

97722
(it&)
(18)
input bias current lbias,,nA
where K2 = pCOx for M2. ABLVCM can be made temper-
Fig.7 ,Vb,clevelopdtrt the input port for 1, = 1WpA ~ i n d I ~ c, fhi ~
" i~s -
ature insensitive by selecting various parameters. If (L4/W,)
is small and IDo4>> IbIurl, we have
t u 5 as CI junction oj r,,
(i) lnpul voliage (V;,J:(13 ofkel cuirenf

216 IEE Prw-Circuio Devices S.ys1.. Vol. 148. Nu. 5. October 2001
a function of &cTri is shown in Fig. 7 for 4,]oT 1OOpA (trace 1.8kQ and 1M a , respectively, at a supply voltage of ?1 V.
(i)). Variation of lo,,fTe,
as a function of Ibknlis also shown The sensitivity analysis of I,,,, with respect to the changes in
(trace (ii)). There is an I(fl;v,, of 5 pA for Ioj~l,yl
of 1nA and the bias currents and bias voltages indicates that the varia-
needs a higher V,,, with reduced Iq8scl.
any decrease in I,,i,iu,sl tions in Ioutare negligible.
Zout as a function of Vo for different values of I,, is given in Thc T, against V, characteristics for ABLVCM is also
Fig. 8, where Ioflseris visible, when I, is less than l O p . 4 shown in Fig. 6. We find that V, is 0.65V for I,, of
(inset of Fig. 8). 500p.4, whereas it was 0.8V and 1.36V for the LVCM and
the conventional CM, respectively. Fig. 11 is the plot of
bias voltage against I,,,, for different values of hrl.Iuffset is
less than lpA (inset of Fig. 1 I). It requires an output volt-
age less than 0.4V for f, up to 200pA and approximately
0.65V for I,, up to 500pA.
~ -_

bias voltage VB, V

Fig.8 Cwre~~r~wltage
churucterivic.7,for IJI'OpOStd LVCM
Figure in inset shows I-V chai-aclerislicsat low currents

o0r ' ' ' ' 1 ' ' ' ' ' ' - A, . . . ,
1.o
I

0.5 1.5 2.0

applied voltage VB, V
Fig.11 Cuuvent-b'oltugeduiruc.teristus.furproposcd ABLVCM
Figui-c in thc insct shows I-V characteristics at low currents

Fig.9

I . . . . . . . . . ._ 1
.
1. ~ . "
l
_
.

3F I
0
-3
-6
-9 frequency, MHz
-1 2 Fig. 12
frequency respons~of proposed ABL VCM
.- (ij Without compensarion; (ii)with resistive compensation; (iii] with capacitive corn-
102
-20 "."""
1 ' """.'
I 03
--"."
.I 5

'
1o4
.,..' "-'I " '
! pensation; (iv) with resistive and capacitivc cr)mpcnsalion
Figure shown in the insel shows the expanded characteristics near cutoff fiququency
..-A
103 IO-* 10-1 i IO 102 io3 104
frequency, MHz
The frequency response of ABLVCM is similar to that of
Fig. 10 Fkequncy response. cfpr(ipo,sedLVCM
(i) Without compensation; (ij) with resistive compensation; (iiij wilh capdcitive con- the LVCM and the bandwidth is dependent on the type of
pensation; (ivj with resistive and capacitive compensation
Figure shown in the inset depicts the expanded characteristics ileal- cuton'lxquency
compensation used (Fig. 12). The bandwidth with and
without compensation is the same as in the LVCM. Simu-
We find that Iuurto Z
, ratio is almost equal to 1 (Fig. 9). lations shows that the bandwidth was 90MHz, ISOMHz,
The bandwidth is strongly dependent on the type of com- and 210MHz for ABLVCM; 95MHz, 150MHz, and
pensation used (as in Fig. 10 for of 500pA). The band- 200MHz for the CM o f Fig. la; and 2kHz, 115MHi, and
width is about 630MHz (trace (i)) with no compensation. 140MHz for the CM of Fig. lh, respectively, when I,,
With addition of gate resistance, bandwidth reduces to equals 1Op.4, 30p.4 and 50p.4, respectively.
approximately 5OOMHz (trace (ii)). There is a sag in the 0.5
frequency response around 10kHz due to the presence of a
zero around this frequency. Compensating capacitor 4: 0.4
increases the bandwidth to 790MHz (trace (iii)). With both
extemal capacitor and resistance, the bandwidth increases
E
-
;"
0.3
twofold to I.2GHz (trace (iv)) and the sag also disappears c
c 0.3 mA
due to cancellation of zero by the addition of polc. The
3 0.2
corresponding bandwidth for conventional CMs was found
to be 550MHz (Fig. lu), and 382MHz (Fig. Ih) and sag -
.,-
3
n
3
0.1
was also present. O

8.2 ABLVCM 0
0.75 1.oo 1.25 1.50 1.75 2.00
The ABLVCM uses adaptive biasing and frequency power supply voltage Vdd, V
enhancement techniques. R, and Rorrtare found to be Fig. 13 Biusrqukment for ABLVCM

IEE Pioc.-Circuirs Devices Sy.st., Vol 148, No. 5, October ZOO/ 271
 Simulations were also carried out under different supply
voltages to define the bias requirements (Fig. 13). For cur-
rents less than 400@, the circuit performs satisfactorily at
a single supply of 1.5V. However, bias voltage of more
than 1.6V is needed for I,, more than 400pA.
The bandwidth of the proposed circuit was evaluated by
simulating it at different voltage levels from M.625V to
k1.OV at I,,* of 200pA. The bandwidth of the ABLVCM
was independent of bias voltage when the latter is more
than +0.75V and was approximately 790 MHz. However
for voltages less than +0.75V, the bandwidth falls to
620MHz at M.625V. Worst-case analysis was carried out
to find variations in I,,, for 50% Gaussian deviations in thc
model parameters chosen for MOSFETs. The absolutc
error present in the DC current transfer is almost negligible
for changes in model parameters (3pA at 120pA). The
error in AC current transfer is also negligible. The band-
width of the ABLVCM decreases by 5”/0over a tempera-
ture change from 0 to 100°C.
8.3 Comparativeperformance
We observe that the ABLVCM has better performance
than other circuits. It operates satisfactorilywith input volt-
age as low as 0.65V for current up to SOOpA, whereas the
other LVCM require more than 0.SV (Figs. 6, S and 11).
It has quite low offset current. A supply voltage of 1.5V is
needed to ensure proper bias requirement for M4 and M5;
but other structures require higher voltage.
9 Conclusion
A novel high performance CMOS LVCM, which can oper-
ate with a supply voltage of ISV, is presented. The
ABLVCM has wide input current range 1pA to 400pA at
218
1.5V with rail-to-rail input and output voltage swing. At
2V, the ABLVCM can operate up to 500pA. It has high
bandwidth of approximately 1.2GHz. One immediate
application is in the design of handheld equipment, where
supply voltage and current are parameters of prime impor-
tance. This circuit can find wide-ranging applications in
portable equipment, where analogue and mixed mode cir-
cuits are used.
10 Acknowledgment
S.S. Rajput thanks Dr. R. Bhattacharyya, Head, Thin Film
Technology Group, NPL, New Delhi, for his kcen intcrest
in the work.
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IEE Pm.-Circuits Dei’iccs Sysr.. Vol. 148. hro. 5 . Ocrobrv 2001