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Challenges of Power Electronic Packaging and Modeling

Yong Liu and Dan Kinzer

Fairchild Semiconductor Corp 82 Running Hill Road, Mail Stop 35-2E, South Portland, ME 04106 Phone: (207)7613155, Fax: (207) 7616339, email: yong.liu@fairchildsemi.com

1. Introduction Abstract

Over the last two decades, power semiconductor Power electronic packaging is one of the fastest changing areas of technology in the power electronic industry due to the rapid advances in power integrated circuit (IC) fabrication and the demands of a growing market in almost such as all areas of power electronic consumer application portable electronics, technology has made impressive progress, particularly in increasingly high power density of monolithic copackaged,and hybrid designs [1-2], which are the driving forces towards a power system module, power system in package (SIP) and 3D power package with heterogeneous functional integration. The development of power packages depends on the development of power device integration. Current power devices have two major integration modes: Monolithic integration integration voltage discrete and includes hybrid power circuits integration. integrated (HYIC), and with Monolithic circuits, high intelligent functional power

electronics, home electronics, computing electronics, automotive, railway and high/strong power industry. However, due to the intrinsic high power dissipation, the performance requirement for power products are extremely high, especially in handling harsh thermal and electrical environments. The design rules and material and structure layout of power packaging are quite different from regular IC packaging. advances, recent challenges in and This talk will power is present a state-of-art and in-depth overview of recent opportunitiesin electronic electronic packaging design and modeling. A review of advances power packaging presented based on the development of power device integration. The talk will cover in more detail how challenges in both semiconductor content and advanced power package design and materials have co-enabled significant advances in power device capability during recent serves years. to Extrapolating where the further can same trends in in representative areas for the remainder of the decade highlight and improvement drive materials techniques continued

integrated power


combined the

integration and the integration of passive elements. Multichipintegration includes standard module and the intelligent power module (IPM). Figure 1 shows the power applications of the

different integration modes with different operation frequencies [\]. The complete power system integration may be monolithic or multichipaccording to the power range desired. Today the trends of monolithic integration are moving towards 3D heterogeneous integration and hybrid integration towards high switching frequency with reduced or eliminated bulky magnetics and capacitances as well as soft switching technologies for high efficiency and low harmonics [3]. Silicon carbide (SiC) and other wide bandgap

enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Along with new power packaging development, modeling is a key to assure successful package design. An overview of the power package modeling is presented. Challenges of power semiconductor packaging and modeling in both next generation design and assembly processes are presented and discussed.

(WBG) semiconductor

devices will ultimately be important elements for hybrid integration to advance system dynamic characteristics, overload capability, device ruggedness, and thermal and electrical performance [4-8].

978-1-4577-0106-1111/$26. 00 20111EEE


2011 12th. Int. Conf on Thermal, Mechanical and Multiphysics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2011

entertainment, industrial power conversion, automotive, and standard power electronics products. Consumer demand for increased mobility with advanced features

fi' I o

and for high efficiency energy solutions

has paved the has driven devices,

way for a variety of new products [9], and high power density design of

advances in power electronics technology towards the monolithic discrete components, 3D heterogeneous and multiple Figure 1 Various power applications chip module or power system in package (SlP)[10]. As compared to the development in general IC package [1119], the power package is far behind due to the extremely harsh operating environment. New modeling methodologies and tools are becoming necessary to support new power package development. This paper describes the challenges for today and the next few years in power package development that should be addressed by our industry.

This paper will introduce power package trends based on power device developments. A review of recent advances in power electronic packaging with both monolithic and multichippower integrations is presented. This paper will cover in more detail how advances in both semiconductor content and advanced package design and the materials have co-enabled the significant advances in power device capability during recent years. Extrapolating the same trends in representative areas to the remainder of the decade serves to highlight where further improvement in materials and techniques can drive continued enhancements in usability, efficiency, reliability and overall cost of power semiconductor solutions. Challenges of power semiconductor packaging in both next generation design and assembly process will be presented and discussed. In addition to the forward looking trends it is important to recognize that the methods for concurrent engineering of these solutions (both the semiconductor content and high performance package capability) are becoming increasingly dependent on rigorous use of proven multi-physicslFEA tools and techniques for both new power package development and its process. The challenges for modeling assembly of power

2.1 Impact of Power Die Shrinkage

The development of power ICs and devices has begun to aim at 130nm technology, while today 180 and 250nm technologies are beginning to drive significant die size shrinkage as compared to regular 350 or 500nm power technology. As the metal interconnect system inside the ICscontinues to (EM) issues have grown become thinner, and new current density has significantly increased. The electromigration interconnect alternatives will be considered. Current techniques such as gold ball bonding and aluminum wedge bondingare giving way to copper ball, clip, and wedge bonding, copper stud bumps and pedestals, flip chip and die embedding in PCBs. Development of fine copper wire (less than 1 mil) bonding technology becomes necessary due to more signal l/Os with smaller wire bond pitch. As the die shrinks, the pitch of power wafer level chip scale packages (CSP) will move from current 0.5mm towards OAmm. The heat dissipation on small die will become a very critical and significant challenge. Finding a high efficiency heat dissipation solution is necessary.

semiconductor package in new package and assembly process are investigated and discussed. Examples of new power semiconductor packaging in thermal management and assembly process are presented.

2. Challenges of power semiconductor packaging

2.2 Power System on Chip (SOC) vs. System in

Package (SIP)





various products is becoming increasingly important in our world due to limited energy resources and climate change. Especially significant is the fast growth of consumer electronics in both communications and

The monolithic integration of power devices allows state of art smart power ICs with technologies such as integration of bipolar, complementary metal oxide semiconductor (CMOS) and double diffused metal oxide semiconductor (DMOS)-BCDMOS. Intelligent discrete


2011 12th. Int. Conf on Thermal, Mechanical and Multiphysics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2011







2.3 Power Package Foot Print Pitch vs PCB Pad Pitch

vertical DMOS (VDMOS), and vertical trench MOS devices withower control and protection as well as other The integration of several heterogeneous technologies analog, digital, MOSFETs, etc. into a single silicon chip can be called Power System-on Chip (PSOC). However, such power SOC technology often is too expensive and complex. This leads to a wealth of opportunities for system in package (SIP), in which multiple chips with different functions are placed in one package or module [20] which has a similar function asSOC but with a lower cost.

As power die size shrinks, the package footprints shrink as well, and maintaining the thermal transfer capacity at the package level is difficult since the function/unit area of die is increasing with advanced BCDMOS processes. While the overall package footprint pad pitch is decreasing area, the customer's print circuit board (PCB) pitch will remain relatively larger. For example, the trend of peripheral pad pitch for a power IC chip will be reduced from about 400 -500um to 200-300um, while the pitch on the customer board can be much larger depending on voltage and current. How should the power wafer level chip scale package (WLCSP) with fine foot print pitch be designed that can be suitable for the larger pitch at the customer's PCB with excellent thermal performance? This is achallenge for the power package engineers because the thermal dissipation capabilities often rely more on the PCB as part of the system, while the smaller foot print pitch power chip cannot directly applied to the larger power PCB. An interposer can fill the interconnect gap between the fine print pitch and the larger PCB pitch, but ithave excellent electrical performance with lower Rds(on), smaller parasitic inductance and excellent heat transfer capabilities. Most importantly, the product should have robust reliability with lower lost. WLCSP

SIP has evolved as an alternative approach to SOC for electronics integration over because SOC in this technology market provides advantages many

segments. In particular SIP provides more integration flexibility, faster time-to-market, lower research and development (R&D) or non-recurring engineering (NRE) cost, and lower product cost than SOC for many applications, especially those with very high power or high currentHowever, SIP is not a replacement for silicon integration but should be viewed as complementary to SOC. For some very high volume applications SOC will be the preferred approach. Some complex SIP products will contain SOC components.

As the die shrinks, SOC can add more functions, and SIP can include more chips. In SOC, the thermal density will become very high. Determining how to insulate different functions in one chip and how to effectively dissipate the heat through the package will be a challenge [21]. Although the cost of SIP is low, there

directly bumping on leadframe or direct bond copper on ceramic, then apply the over molding is an effective packaging approach to connect the fine pitch on power chip to the larger pitch on PCB. This method is a trend that has very good thermal and electrical performances for fine pitch power device.

are challenges due to the assembly of multiple chips. The internal parasitic effects of SIP, like parasitic inductance [22], are higher than SOC. The impact of heat from the power components on the electrical performance of IC drivers will be a concern. To build an advanced SIP which has good thermal and electrical performance with low cost is the greatest challenge of power SIP, especially for high power module applications, where excellent efficiency, good thermal and electrical performances are critical for the product design and reliability.
2.4 New Materials for Power Device

Due to the limit of silicon power device at high voltage level (600-700 V), the technological advancement has pushed the development of new materials for power devices, such as silicon carbide (SiC), gallium nitride (GaN), and other wide band gap (WBG) semiconductor materials. SiC is one of the most promlsmg semiconductor materials that will be used to replace silicon in future power electronics. There are three great advantages of SiC [4,7] as shown in Figure 2: (1) The higher breakdown electric field strength of SiC allows a much thinner drift region and thus a much smaller specific on-resistance of SiC devices thansilicon devices.


2011 12th. Int. Conf on Thermal, Mechanical and Multiphysics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2011

(2) The low on-resistance of SiC devices allows the use of majority-carrier devices like MOSFET and Schottky diodes rather than minority-carrier devices such as insulated gate bipolar transistor (IGBT) and PiN diodes. This results in a much reduced switching loss absence of the charge storage effect. Lower switching losses will further allow higher switching frequency and subsequently smaller and less expensive passive components such as filter inductors and capacitors. (3) The larger band gap results in a lower intrinsic carrier concentration and higher operating junction temperature.

because they have negligible reverse recovery losses. SiC JFETs, MOSFETs, and bipolar transistors with exceptionally resistance were reported, which can potentially be used as the active power switches replacing Si-IGBTs. It is a great challenge to produce a high-quality interface between silicon carbide and a suitable gate dielectric material for SiC MOSFET structures. JFETs and bipolars avoid the gate reliability and poor channel mobility issues of MOSFETs, while bipolars offer normally-off operation with high noise margin for single supply input drives. The high defect density and cost of SiC has delayed wide-spread commercialization. The cost of SiC diodes historicallyranged from five to ten times that of silicon devices with the same voltage and current ratings, but is declining as materials improve and volume increases. Gallium Nitride devices have a theoretical limit for a vertical device even lower than SiC. Realizing that performance is not yet possible, due to the lack of a reasonable cost single crystal GaN substrate. GaN devices today are lateral, and so have limitations of high surface electric fields, susceptibility to voltage transients, on-state instability due to charge accumulation in the off-state, and usually normally-on operation. Normally-off devices are emerging, using hybrid GaN/silicon cascode arrangements or special gate structures that add to the device on-state resistance. Power terminals must be interdigitated and routed on the surface and space reserved for power wire bonds or other interconnects, which limits active area utilization. Nevertheless, GaN devices do show promise for future medium voltage and current applications. Much progress is happening to fully exploit these benefits of new semiconductor materials to achieve system-level improvement In the weight, size, efficiency, performance, and even possibly the overall cost of the power electronic products.
2.5 New Materials for Power Package

Figure 2. The Comparison of Si, SiC and GaN [7] In general, SiC devices could operate at a junction temperature as high as 500-550 c, as compared to a typical 150-200 c maximum junction temperature of silicon devices. The increased operating temperature can reduce the weight,volume, cost, and complexity of thermal management. Furthermore, the very high thermal conductivity of SiC reduces the thermal resistance of the device die. Significant progress has been made in research and development of SiC and other WBG device technologies in the past decade [4]. Various types of SiC switching devices and diodes have been developed and reported. The 600-1700-V SiC Schottky diodes are commercially available, which can replace Si freewheeling diodes in renewable energy (solar and wind), industrial motor drives, and hybridlfull electric electric vehicle (HEVlEV) inverters. SiC Schottky diodes have demonstrated superior performance to that of similar silicon PN diodes, especially with respect to their switching characteristics

Development of new package materials to support power package heat transfer and good electrical performance is critical and challenging. For example, and improvedthermal setting molding compound material with reasonable content of nano-silica fillers to rapidly dissipate heat from the power die while keeping the adhesion strength high is needed. At present, both Pb-free solder alloies and green epoxy mold compound


2011 12th. Int. Conf on Thermal, Mechanical and Multiphysics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2011












which the

include interface

electromigration of two metal

companies. However, thermal stability is a key issue [9], especially in the automotive environment, where current have difficulties meeting the requirement of exceeding 180 C continuous operation. The new green EMC will have to withstand such temperature from the power chip. Pb-free solder alloy must have high melting temperatures for power package. Currently the solder material for power package is PbSnAg based alloy which normally has the melting temperature above 300C with low cost. The challenge is to develop an equivalent Pb-free solder alloy for power devices that has the melting temperature about 300C with similar low cost. Also, the Green EMC should not burn during high temperature operation in the power device. As the chip shrinks, there are related trends in power packages. The first is for power ICs, where the volume of EMC is decreasing with the introduction of package technologies such as WL-CSP, power BGA, and flip chip BGA, which are gaining wider application. The second is in high power applications which currently apply VDMOS devices and IGBTs. We see a trend for increasing SiC, GaN, and other wide band gap semiconductor materials. [3, 7] The challenge is to epoxy mold compound materials




materials; contamination at the interface between leadframe, multiple chips and EMC; thermal resistance definition in SIP; 3D copper stud bumping and wire bonding simulation, etc.. The greatest challenges in modeling for power packages today are the multi-physics simulations, which couple the electrical, thermal and mechanical fields, and the assembly process simulation in a multi-scale SIP system. The development of highly efficient modeling algorithms for such a SIP system is very critical for the virtual prototyping of new products. In some cases, the SIP might have strong thermomechanical performance but is weak in the electrical area or the SIP has very good electrical performance but is weak in the thermomechanical design. Therefore it is necessary to determine the best solution using modeling. Package measurements are expensive, time consuming, and cannot provide all of the required information.

3.1 Co-design automation simulation

TTRS SIP 2009 white paper [26-27] describes a future vision of chip-package system co-design: (a) one tool for simultaneous design enabled by a multi-user, cross-functional EDA + system analysis + knowledge-based tool. (b) A wizard-like interface, automatically constructs baseline design for each component based on series of user questions, analysis and an expert system for technology selection and design rules. These ideas cover stress/mechanical modeling, thermal chip-package system and electrical chip-package system. This indicates a modeling trend of the industry is towards package system design automation. The advance of power package development needs the high efficiency, and short design cycles, in which the FEA use will accelerate the further miniaturization of power electronic components, and accelerate the incorporation of advanced materials and assembly structures [28]. However, most of the power package design engineers, material engineers, test engineers and the reliability analysis engineers are not familiar with FEA. If they can run designed experiments using FEA for their product optimization in co-designed power package efforts and for material selection, that will really accelerate the power package development. Therefore, to develop the

develop robust materials and methods that can easily transfer the heat from these devicesto ambient. Two such technologies are direct bond copper on ceramic (DBC) and insulated metal substrate with polymer insulation to dissipate the heat to heat sink [23-25]. The other is the built copper material based substrate at bottom and copper clips at package top for excellent heat transfer. For high power applicationmicro-channels built into the heatsink, substrate, or even the diein the future can effectively help the heat dissipation in power packages [26].

3. Modeling trends in power electronic packaging

The power package development today is becoming increasingly dependent on the rigorous use of proven multi physics/FEA tools and techniques. Correct use of the modeling tools can defmitely save design time and shorten the number of design cycles. The challenge is, can the modeling tool and methodology be ready to support the new trends in the development of new power package technologies? Examples of the challenges include various designs, reliability

modeling automation system is one trend of the power package modeling. This system allows people who might not know FEA but wish to do design optimization for their product to run FEA. Engineers just simply input some basic information and set the DOE set, the system will automatically do the meshing, apply boundary conditions and loads, solving and automatically output the results. References [29] and [30] have developed the initial modeling automation system for thermal, analysis. moisture and linear thermal-mechanical stress The results have shown great efficiency to save


2011 12th. Int. Conf on Thermal, Mechanical and Multiphysics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2011

modeling time. Developing the modeling methodology for SIP system needs further to be studied for how to define the thermal resistance for a SIP. A investigation of the thermal performance for various power packages has been presented in [31].

devices built in soft substrates, and ultrathin power switches have started to find use in industrial applications. One typical example of multi-physics is the electromigration issue which couples electrical, thermal and mechanical fields. Electromigration in power WL-CSP in both interconnect and solder balls will be a serious challenge as the pitch becomes small due to die shrinks. Modeling of electromigration will to improve the design of the WL-CSP. Simulation of 3D void generation has been developed in both interconnect and solder bumping level [40]. The further application of the migration simulation method to a package on package (POP) has been studied [41]. Typically, with multiphysics analysis, the exchange of data between the physics fields requires careful coordination, and the different mesh requirements for the various fields, loads, and boundary conditions must be correlated. For all these to function correctly requires a complex feedback loop between the various fields so that the coupled analysis converges to an accurate solution. The predictive FEA simulations more closely represent the real world than simplified assumptions that often neglect issues that turn out to be critical. Performing multiphysics analysis early in product development enables companies to easily and inexpensively spot and fix problems that can become costly and time consuming to resolve later. Factoring in the effect of more physics yields more accurate analysis, fewer physical prototypes, a shorter product-development cycle, lower development cost, and a faster time to market and response time to market changes.













applied to the new development of power package in design and assembly. Examples are, as the die size and thickness shrink, die pick up process will become very critical, simulating this pick process is helpful to reduce die cracking [32]. Passivation cracking modeling will help for the metal stacking and layout of passivation layer above the metal [33]. Moisture has a big impact on the power package during wet environmental condition, a systematic modeling and analysis methodology for moisture and vapor pressure have been introduced in [34]. Cu-wire bonding and Cu-stud bumping will induce the failure such as the silicon cratering and BPSG crack under the barrier layer. Development 2D-3D dynamic solution for the wire bonding process can optimize the cu wire bonding parameters [35-36]. Drop test is always of interest to and requested by the portable customers. There are a lot of studies towards the drop test modeling [37-39]. Power WL CSP will need fully simulation to pass the drop test requirement.

3.3. Multi-physics and multi-scale modeling

During the manufacturing and testing of microsystems, issues of multi-physics and multi-scale modeling are involved due to the intrinsic nature of nano-micro scales, and multi physics behaviors occurring in those processes. Despite the advances made in the current modeling of the structural, thermal, mechanical, and transport properties of materials at the macroscopic level (finite element analysis of complicated structures), there remains tremendous uncertainty about how to predict many properties of interest. For instance, exploiting the tremendous physical and mechanical properties of new nano-materials devices by understanding nanoscale materials and at atomic, In molecular, and supramolecular levels is useful for designing including materials structures. addition, optical, thermal, electrical, deformation/stress occur concurrently, which needs coupled-field analysis allowing to determine In the the combined effects of multiple such physical as power phenomena on a design. development of microsystems electronic packaging, multi-physics effects are inherent and must be addressed. Microsystems have components with micrometer dimensions. Extensive applications for these devices exist in both commercial and industrial systems. Well known components such as integrated silicon sensors, power

Multi-scale simulation can be defined as the enabling technology of science and engineering that links phenomena, models, and information between various scales of complex systems [28]. It is recognized that within the scope of materials and structures research, the breadth of length and time scales may range more than 12 orders of magnitude (Gates, T. S., et at., 2005 [42]). Different scientific and engineering disciplines for multi-scale modeling are involved at each level as shown in Figure 3. The idea of multi-scale modeling is straightforward: one computes information at a smaller (fmer) scale and passes it to a model at a larger (coarser) scale by leaving out, i.e., coarse-graining, degrees of freedom. From a "bottom-up" perspective, the multi-scale approach goal of should consider the intrinsic is then attributes to of the the constituent materials for the system of study. The ultimate multi-scale modeling predict macroscopic behavior of an engineering process from first principle, i.e., starting from the quantum scale and passing information into molecular scales and eventually to process scales. In addition, multi-scale modeling has the potential to significantly reduce development costs of new nanostructured materials for demanding structural applications by bringing physical and microstructural information into the realm of the


2011 12th. Int. Conf on Thermal, Mechanical and Multiphysics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2011

design engineer. There are several recent studies of the multi scale modeling that have paid attention to ionic polarization layers in polymer electrolytes [43] which could be potentially used for the polymer contamination. Molecular dynamics has been used for the multi-scale modeling for moisture, adhesion, delamination between molding compound and metal, and the material properties prediction [44-45].


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2011 12th. Int. Conf on Thermal, Mechanical and Multiphysics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2011

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2011 12th. Int. Conf on Thermal, Mechanical and Multiphysics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2011

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2011 12th. Int. Conf on Thermal, Mechanical and Multiphysics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2011