Proceedings of the International Conference on VLSI and Communication Engineering, April 16th18th 2009

Digital CMOS High-Speed Level Shifter Design

Abhijit Asati and Chandrashekhar

Abstract: The design of level shifter circuit using CMOS inverter requires an accurate adjustment of the inverter threshold (switching threshold) voltage Vth, which is dependent on the PMOS/NMOS width ratio (-ratio) of the inverter. An accurate selection of NMOS and PMOS device W/L ratio is essential for achieving the highest speed of level shifting operation based on amount of capacitive load to be driven by level shifter circuit. In this paper we propose a simulation-based method for accurate estimation of NMOS and PMOS device W/L ratios for high-speed level shifter design. Since the level shifter circuit is designed using digital CMOS inverter, the level shifting operation produces the output as inverted logic. Index Terms: level shifter circuit, beta ratio, CMOS, VLSI, digital circuit design, mobility, technology etc.

I. INTRODUCTION

In this paper we present a simulation-based method to determine the accurate NMOS device W/L ratio (the PMOS device W/L ratio is taken as times the NMOS device W/L ratio) to achieve highest possible speed without much increase in area and power consumption. Section II describes the calculation inverter threshold voltage (vth) and for appropriate level shifting operation, Section III discusses about the determining the optimum - ratio to give minimum propagation delay for W/L of NMOS device and three different load conditions, Section IV describes determination of NMOS device W/L ratio for given -ratio and given load capacitance for high speed level shifter design and section V concludes the paper.
II. CALCULATION OF INVERTER THRESHOLD VOLTAGE (Vth) AND FOR APPROPRIATE LEVEL SHIFTING OPERATION

The level shifting is very useful operation needed in CMOS digital circuit design. In sub-micron technologies the supply voltages of CMOS device are decreasing due to scaling [1]. The CMOS devices operating at lower supply voltages can be made compatible with the CMOS/TTL devices operating at higher supply voltages using a level shifter arrangement [2], [3], [4], [5]. The digital CMOS circuits prefers the dual supply voltage technique in order to reduce the dynamic energy consumption, in which low voltage gates are kept on non-critical path and high voltage gates are kept on critical path and the level shifting operation is performed whenever the low voltage gates drives the high voltage gates [4]. The use of conventional CMOS logic for level shifting provides robustness against voltage and transistor scaling and it provides reliable operation at low voltages and consumes low power as compared to other logic styles. CMOS logic devices have high noise margins due to the presence of a static path that restores the correct logic state in the presence of noise. Further, the sharper voltage transfer characteristic of CMOS inverter makes it suitable for level shifting operation. The design level shifter requires the appropriate selection of PMOS/NMOS width ratio () since -ratio decides the inverter threshold (switching threshold) voltage Vth of inverter [2]. This can be satisfied for any W/L of NMOS device but it will affect the speed of operation. For the case when large CMOS loads have to be driven the optimal selection of W/L ratio of NMOS device and PMOS device is a tedious process.
Abhijit Asati is with the Birla Institute of Technology and Science, Pilani Rajasthan, 333031, India, E-mail: abhijitmicro@gmail.com Chandrashekhar, Diector CEERI, Pilani, Rajasthan, 333031, India, E-mail: chandra@ceeri.ernet.in

Suppose a level shifting operation in which logic of VOH1= 2V and VOL1= 0.8 V has to be translated to VOH2= 3.3V and VOL2= 0 V. Such level shifting operation can be performed using a CMOS inverter by adjusting its inverter threshold voltage (vth) equal to [VOL1+ (VOH1VOL1)/2] =1.4V. Since digital CMOS inverter is used for level shifting the shifted logics will be inverted. Adjusting the inverter threshold requires the accurate selection of - ratio. We assume that a level shifter circuit produces inverted logic together with level shifting operation and drives the high voltage MOS capacitive load CL as shown in figure 1.
VDD P1

Cdp1 Vout Vin CL N1 Cdn1

GND

Figure 1: Level Shifter Circuit (CMOS Inverter Driving Capacitive Load CL)

Proceedings of the International Conference on VLSI and Communication Engineering

Since the level shifting operation requires the accurate adjustment of an inverter threshold (switching threshold) voltage Vth, therefore it is considered as an important design parameter characterizing the DC performance of the inverter. The calculation of vth are described in Equation (1) [2], [6].
Vtn + Vth = 1 (VDD + Vtp ) KR 1+ 1 KR

III. DETERMINING THE OPTIMUM - RATIO TO GIVE MINIMUM PROPAGATION DELAY FOR W/L OF NMOS DEVICE AND THREE DIFFERENT LOAD CONDITIONS

(1)

W n Cox K n n Cox ( L) n = where : K R = K = W ) p Cox p Cox ( p L p

The -ratio can be obtained in order to satisfy the required DC performance characteristic of inverter using equation (1). Although this -ratio can be satisfied for any W/L ratio of NMOS device but it may degrade the speed of operation, power consumption and area. The load capacitance seen by the inverter is given by equation (2) & (3). CL(total) = Cdp1 + Cdn1 + CL (2) Where, Cdp1 and Cdn1 are equivalent drain diffusion capacitance of PMOS and NMOS transistors of the inverter and CL represents the load capacitance to be driven by level shifter. For Cj0n = Cj0p and Cj0swn = Cj0swp, if PMOS devices are times larger than NMOS device then CL(total) is given by equation (3). The CL(total) includes the parasitic capacitances of both the devices.
Cdp1 = Cdn1 CL (total ) = (1 + ) Cdn1 + CL where : Cdn1 = K eqn AD n1 CJ + K eqswn PDn1 CJSW where : K eqn = 2 o V2 V1 ( o V2 o V1 ),

The widening of the PMOS device beyond certain point improves the tPLH (time delay between the 50% transition of the falling input voltage and the 50% transition of the rising output voltage) of the inverter but it also degrades the tPHL (time delay between the 50% transition of the rising input voltage and the 50% transition of the falling output voltage) due to effect of increased self parasitic capacitance [3]. For maximum speed tP = (tPLH + tPHL)/2 should be minimum for given load condition. In this study we have find out the optimum value of - ratio which produces minimum tP for given capacitive load and a fixed W/L ratio of NMOS device. It has been observed that for a particular -ratio the tP is minimum and for other -ratio tP increases. Table I shows the optimum - ratio for which tP is minimum for two fixed W/L ratios of NMOS device and for three different load conditions. The technology selected for study is 0.5m N-well CMOS process (SCN_SUBM, lambda = 0.3) of MOSIS. The technology parameters for both NMOS and PMOS devices are read from the model file of the 0.5mm technology. The simulations were performed using T-spice of M/s Tanner Research Inc. The VDD was kept at 3.3V level for all simulations because VOH2=3.3V and VOL2= 0 V. From Table I it can be observed that in the absence of capacitive load the level shifter circuit produces a almost fixed optimum - ratio to give minimum propagation delay tp, for all W/L ratio of NMOS device, which suggests that at no load condition increasing the W/L ratio of NMOS device does not yield any speed improvement but on the contrary consumes more average power and area.
Table I Optimum -ratio for which tP is Minimum for two Fixed W/L Ratios of NMOS Device and for three Different Load Conditions CL(pF) 0 0.1 0.5 (W/L)n=1 Beta () tp (min) 1.2 15 30 17.125ps 420ps 1775ps (W/L)n=10 Beta( ) tp (min) 1.1 5 13 17.2ps 75ps 233ps

(For Grading Coefficient = MJ = MJSW = 0.5) K eqn = K eqswn = voltage equivalent factor (0 < K eqn < 1) o = PB = Built in potential of PN junction

(3) While, in the level shifter circuit, if capacitive load is present then for smaller W/L ratio of NMOS device the minimum propagation delay tp is obtained at much larger -ratio but the value of tp is larger; to decrease this tp value we increase the W/L of NMOS device which gives now the minimum tp at much decreased -ratio. The increase in W/L of NMOS device beyond certain value increases area and power without contributing to speed improvement. In a level shifter circuit finding the optimal W/L ratio of NMOS device for given CL and -ratio is a

Using above -ratio and given load capacitance CL the appropriate selection of transistor device size can be carried out as described later in section IV.

Digital CMOS High-Speed Level Shifter Design

! of both the MOSFETS on the contrary it consumes more silicon area and power. Similar techniques can be used for determining W/L of NMOS device in high-speed logic gate design and mixed signal comparator design, for a given bratio and a given load capacitance CL.
V. CONCLUSION

challenging task since it affects speed, area and power. Section IV discusses the accurate estimation of NMOS device for given CL and - ratio.
IV. DETERMINING NMOS DEVICE W/L RATIO FOR GIVEN B- RATIO AND GIVEN LOAD CAPACITANCE FOR HIGH SPEED LEVEL SHIFTER DESIGN

Using the simulation results obtained in table 1, the graph can be plotted between optimum - ratio and capacitive load CL for each W/L ratio of NMOS device. Figure 2 shows the variation of optimum b- ratio with different load condition to produce minimum propagation delay for different W/L ratio of NMOS device.

The random selection of W/L ratio of NMOS device may degrade the performance of level shifter design. This paper presents simulation-based curve fitting method for the optimal selection of W/L ratio of NMOS device for achieving highest speed of level shifter design for a given -ratio and capacitive load CL. Since W/L ratio of NMOS device is optimally chosen to achieve high speed the area and power consumption of circuit will be optimal. The method includes the relevant technology parameters and associated parasitic capacitances in determination of the W/L ratio of NMOS device.
REFERENCES
[1] Mohab Anis, Mohamed Allam and Mohamed Elmasry , Impact of Technology Scaling on CMOS Logic Styles, IEEE Transaction on Circuits and Systems-II, Analog and Digital Signal Processing, 49(8), 577-587, 2002. [2] S. M. kang and Yusuf Leblebici , CMOS Digital Integrated Circuits, Analysis and Design, Third edition McGrawhill Publishing Company Limited, 2003. [3] MichelMichel J. Declercq, Martin Schubert and FranGois Clement, High Speed Communication and Interfaces IEEE International Solid-State Circuits Conference, pp. 162-163, 1993. [4] Abdulkadir Utku Dril, Yuvraj Singh Dhillon, Abhijit Chatterjee and Adi D. Singh, Level-shifter free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages IEEE Transactions on Very Lage Scale Integration (VLSI) Systems, 13(9), 1103-1107, 2005. [5] Maziyar Khorasani, Leendert van den Berg, Philip Marshall, Meysam Zargham,Vincent Gaudet, Duncan Elliott and Stephane Martel, Low-Power Static and Dynamic High-Voltage CMOS Level-Shifter Circuits IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1946-194, 2008. [6] Jan M. Rabaey, Anantha Chandrakasan, Borivose Nikolic , Digital Integrated Circuits, Second Edition PrenticeHall of India Private Limited, 2004.

Figure 2: Variation of Ratio with Different Load Condition to Produce Minimum Propagation Delay as Shown in Table 1

Note that when the load is present and as W/L ratio of NMOS device increases then the optimum - ratio to give minimum propagation delay drops down further and related propagation delay also decreases. Hence for the given ratio and given load condition the W/L of NMOS device in increased till it satisfy the both conditions. Draw the intersection of - ratio and load CL; increase the W/L of NMOS device till is touches this point. The increase in W/L of NMOS device beyond this point does not yield any further improvement in speed due to increased parasitic capacitance