Chapter 5: CMOS Logic Gate Design

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Chapter 5. CMOS Circuit and Logic Design 5.1 Introduction

To study the following two areas of CMOS design: Circuit (structural) design Layout (physical) design The goal to achieve: Functional correctness Smallest area, highest speed, lowest power consumption

5.2 CMOS Logic Gate Design

To achieve correct operation of any integrated logic gate, the following two constraints must be satisfied: Functional constraint Temporal(timing) constraint For COMS logic the following effects can result in incorrect functioning of a gate: Insufficient power supply (may due to noise on power/ground bus) Noise on gate inputs Faulty transistors

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Incorrect connections to transistors Incorrect ratios in ratioed logic Charge sharing or incorrect clocking in dynamic gates Functional correctness versus logic design styles Complementary CMOS gate (circuit) will always function correctly The function of ratioed or dynamic gates (circuits) may be compromised by poor design, sloppy layout, and unforeseen noise. Temporal aspects of a CMOS gate:
k The rise/fall time may be approximated by (EQ. 5.1), where eff ( rise / fall )V DD k is a constant (2~4), eff(rise/ fall) is the effective gain of the pull-up or pull-down chain in a gate affected by the number of transistors in series (or parallel) in the pull-down (fall time) or pull-up (rise time). C load

Cload is the load capacitance seen by the gate, which is dependent on

the size of the transistors in the gate (self-loading due to source/drain capacitance) the size and number of transistors to which the gate is driving the routing capacitance.

VDD is the power supply Note that the above formula does not consider the influence of the input rise/fall time.

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The timing of a circuit is determined by the delay time of the slowest (longest ) paths in the circuit. These paths are called critical paths. A path is defined as an alternating sequence of logic gates and signal nets from source to sink. The following objects can be served as a source: primary input memory element (latch or flip-flop) The following object can serve as a sink: primary output memory element (latch or flip-flop) The critical paths can be affected at four main levels: The architectural level The RTL/logic level The circuit level the layout level

5.2.1 Fan-in and Fan-out

Fan-in of a logic gate: the number of inputs to the gate. Fan-out of a logic gate (or a net): the total number of gate inputs that are driven by the gate. (see Figure 5.1)

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The stage ratio is the increase in transistor size in successive logic stages. Correct selection of the ratio can markedly affect timing in cascaded logic stages. However the ratio is greatly influenced by the fan-out of the gate. The fan-in of a gate implies the number of series transistor used to realize the gate and thus affects the speed of the gate. In general the fan-in ranges from 2 to 5. For example, the worst-case delay time tdr for an m-input NAND gate
t dr = Rp (mnC d + Cr + k C g ) = R p (mnr C g + q(k )C g + k C g ) = R p C g (mnr + q(k ) + k ) n n n R pCg Rp Cg = R p C g mr + q(k ) + k (EQ. 5.2) n n

where Rp = the effective resistance of p-device in a minimum-sized inverter n = width multiplier for p-device in this gate k = the fan-out (in units of minimum-sized inverters) m = fan-in of the gate Cg = gate capacitance of a minimum-sized inverter Cd = source/drain capacitance of a minimum-sized inverte Cr = routing capacitance r = C d/Cg q(k) = a function of the fan-out representing the routing capacitance as a multiplier times the gate capacitance

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If q(k) is equal to k, the above equation is of the form,

t dr = t internalr + k t output r , where t internalr = R p C g mr and t outputr = q(k ) R pCg (1 + ). n k

Similarly, the fall delay time

Rn 2 t df = m (mnrC g + q(k )C g + k C g ) = R p C g m r + mk n q( k ) Rp Cg (1 + ) = t internal f + t output f n k (EQ. 5.4)

where Rn = the effective resistance of n-device in a minimum-sized inverter. In general, for equal rise and fall time, i.e. tdf=tdr, we obtain Rp=mRn. Thus
pW p = nW n m

5.2.2 Typical CMOS NAND and NOR Delays

Figure 5.2 shows the delay for a family (Wn=6.4u, Ln=1u, Wp=12.8u, Lp=1u, tinput-rise/fall=0.1ns, CL = 0 to 1pF) of NAND and NOR gates measured by SPICE at the worst-speed corner. Table 5.1 summarizes the data shown in Figure 5.2 in terms of EQ. (5.1).

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Table 5.1

From the graph in Figure 5.2 and the equations 5.2 and 5.4, the effective resistance for the transistors can be calculated. For n=4, kCg=CL, q(k)=0, rCg(=Cd)=0.005pF (Cg= 0.003pF, r=1.7); Wp=2Wn, then
t df nand = m 4 t df nand Rnnand ( m 4 0.005 + ) CL Rnnand = 4 m(0.02 m + C g)

Table 5.2 show the effective resistance for m=1 to 4 Table 5.2

Example with Figure 5.3 on page. 270

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Table 5.3 shows the delays calculated for a rising output by using the values in Table 5.1 and EQ. 4.53 (which adds 0.44t f/r to the delay time.) Table 5.4 shows the areas for the implementations in Figure 5.3. Table 5.3 and 5.4

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5.2.3 Transistor Sizing

Sizing an inverter chain to drive a large load.

Sizing the transistors in a logic gate to obtain a smallest delay time, and balanced rise and fall time. For example, for the 8-input NAND gate used as a row decoder for memory array, transistor sizes are tuned to improve the rise time and to save the area by satisfying the fall time. The transistor sizing result is shown in Table 5.4. In general, for transistor sizing it is a good starting point to use minimum-sized devices throughout and then optimize paths from a critical-path-timing analysis. Table 5.5 .

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5.2.4 Summary
Basic guidelines for CMOS complementary logic design with speed as a concern: Use NAND where possible Place high-drive inverters at high fan-out nodes Avoid use NOR for high speed designs Use a fan-out below 5 to 10 Use minimum-sized gates which are driven by a high fan-out node Keep rising/falling edge sharp When designing with power or area as a constraint, large fan-in CMOS gate will always work when given enough time.

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5.3 Basic Physical Design of Simple Logic Gates

Perform physical layout to realize the behavior of a circuit. To simplify layout, unit-sized n-transistors are generally shown and p-transistors are often shown with doubling the unit size.

Symbolic layout is used.

5.3.1 The Inverter

Figure 5.4 shows the schematic and symbolic layout of an inverter. The connection between n-diffusion and p-diffusion must be made by one metal wire and two contacts (assuming there are no local interconnect or buried contacts.) The connection between sources and power/ground must be also be made with metal wire and contacts. Power and ground buses are run in metal. The common gate connection may be a simple polysilicon wire. Substrate (well) contacts must be added. Non-planar situation is dealt with by simply crossing two lines. Figure 5.4

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Figure 5.5(a) shows the final symbolic layout. The rest of Figure 5.5 shows the various symbolic layout the the same inverter. Figure 5.6 shows the symbolic layouts of same inverter by using Metal2/Metal3 layers. Figure 5.7 shows various methods for laying out large inverter.

5.3.2 NAND and NOR Gates

Figures 5.8 and 5.9 show respectively the typical symbolic layouts for NAND and NOR gates.

5.3.3 Complex Logic Gates Layout

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5.3.4 CMSO Standard Cell Design

With the same cell height and varying cell width. (Fig. 5-14, 5-15) Semi-custom Design. Use of standard cell.

5.3.5 Gate Array Layout

With prefabricated transistors. (Fig. 5-16) The user must customize the wire connection and the fab must manufacture the wire connection.

5.3.6 Sea-of-Gates Layout

Fig. 5-17 and Fig. 5-18.

5.3.7 General CMOS Logic-Gate Layout Guidelines

Page. 287-288

5.3.8 Layout Optimization for Performance

Fig. 5-19

5.3.9 Tramission-Gate Layout Consideration

Fig. 5.20, 5-21, and 5.22.

5.3.10 2-input Multiplexer Fig. 5.23

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5.4 CMOS Logic Structure 5.4.1 CMOS Complementary Logic

Ratioless design (does not have a fixed ratio in size between pull-up and pull-down structures). Varying ratio of P/N transistors will not influence the functional correctness of a circuit, but will influence the noise margin.

5.4.3 Pseudo-nMOS
Fig. 5.27 The design of this style of gate involves ratioed transistor sizes to ensure correct operation. The gain ratio of n-driver transistors to p-transistor load, yield sufficient high and low logic levels. Problems
Static power consumption Low output low noise margin.
driver load

, has to be selected to

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5.4.4 Dynamic COMS Logic

Fig. 5.30 Prechage Phase Evaluate phase Problems Input can change during precharge phase and must stable during evaluate phase. Subceptible to noise Simple single-phase dynamic CMOS gates can not be cascaded. (Fig. 5.31)

5.4.5 Clocked CMOS Logic

Fig. 5.32 For low power applications. Slower than fully complementary CMOS gates.

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5.4.6 Pass-Transistor Logic

Model for pass transistor logic, Fig. 5.33 Two-input XNOR gate, Fig. 5.34. Boolean function unit, Fig. 5.35. Some functions implemented by the Boolean function unit, Table 5.9

5.4.7 CMOS Domino Logic

Basic gate (Fig. 5.36) Static gate (avoid floating for output logic 1) Latched version (avoid floating for output logic 0) Poorly designed precharge circuit, Fig. 5.37

5.4.8 NP Domino Logic

Fig. 5.38.