ISA Bus Timing Diagrams

SBS ISA bus timing diagrams are derived from diagrams in the IEEE s P996 draft specification which were, in turn, derived from the timing of the original IBM AT computer. Please note that the IEEE P996 draft specification was never completed by the IEEE and is not an IEEE approved spec. Also, the latest IEEE draft is known to contain errors. In the absence of an approved IEEE specification, manufacturers of PC chip sets attempt to meet a consensus ISA bus standard. This has resulted in minor variations in signal interpretation and timing among the various PC chipset vendors. For this reason, SBS recommends that designers of interfaces to the ISA bus use the minimum number of bus signals needed to perform a required function (e.g. chip selection or signal synchronization). For example, at least one popular chipset does not drive AEN high during REFRESH. In certain instances, SBS has added logic to improve bus timing and/or signal relationships on CPU and peripheral boards. SBS ISA bus timing diagrams include several corrections relative to s the IEEE P996 draft specification. However, since these diagrams are derived from an uncompleted and unapproved IEEE specification, they may contain other errors. For comprehensive technical details on the ISA architecture and bus, SBS recommends the following book: ISA & EISA Theory and Operation, by Edward Solari; published by Annabooks (www.annabooks.com). This book contains a detailed technical exposition of the ISA and EISA buses and is written by the principal author of the IEEE P996 draft specification.

ISA Bus Timing Diagrams

REF
1 2 3 4a 4b 5 6 7a 7b 7c 8a 8b 8c 8d 10a 10b 10c 10d 11a 11b 11c 11d 12 13a 13b 13c 15a 15b 16 17 18 19 20a 20b 21 22 23 24 25a 25b 26a 26b 28 29 36 37

TYPE
M,IO M,IO M,IO M M M M M IO M,IO M IO M M,IO M IO M,IO M,IO M IO M,IO M,IO M,IO M M IO M,IO M,IO M,IO M IO IO M,IO M,IO M,IO M,IO M,IO M,IO M,IO M,IO M M M M M M

SIZE
8/16 8/16 8/16 16 8 8/16 8/16 16 16 8 16 16 16 8 16 16 16 8 16 16 8 8 8/16 16 8 8/16 8/16 8/16 8/16 16 8/16 8/16 8/16 8 8/16 8/16 8/16 8/16 8/16 8 16 8 16 16 16 16

DESCRIPTION
LA setup to BALE deasserted BALE pulse width LA hold from BALE deasserted LA setup to MEMx* asserted LA setup to MEMx* asserted MEMCS16* valid from LA MEMCS16* hold from LA SA, SBHE* setup to MEMx* SA, SBHE* setup to IOx* SA, SBHE* setup to IOx* or MEMx* Command width Command width Command width with ENDXFR* asserted Command width Read data access Read data access Read data access with ENDXFR* asserted Read data access Write data setup Write data setup Write data setup (even) Write data setup (odd) SA, SBHE* hold Command deasserted Command deasserted Command deasserted Read data hold Write data hold Read command to SD disabled ENDXFR* asserted from command IOCS16* asserted from SA IOCS16* hold from SA IOCHRDY valid from command asserted IOCHRDY valid from command asserted IOCHRDY deasserted pulse width Command hold from IOCHRDY BALE asserted from command deasserted Clock period (Tclk) Data setup to IOCHRDY deasserted (8-bit even) Data setup to IOCHRDY deasserted (8-bit odd) LA hold to MEMx* active LA hold to MEMx* active ENDXFR* setup to SYSCLK falling edge ENDXFR* hold from SYSCLK falling edge LA setup to ENDXFR* asserted SA setup to ENDXFR* asserted

DRIVER
MIN
111 61 26 120 183 66 0 39 102 102 240 165 103 541 173 110 48 482 -34 33 7 -45 53 108 170 170 0 25 30 10 74 0 70 373 15600

RECEIVER
MIN
100 50 15 109 172 102 0 28 91 91 219 154 92 530 195 132 70 504 -45 22 -4 -56 42 97 159 159 0 25 30 32 122 0 159 462 15611

MAX

MAX

125 125 46 120

125 35 120

167 85 75

167 74 64

41 -21 22 22 180 83

30 -32

158 61

Table 1. Memory and I/O Timing

24 SYSCLK 8 MEMR* MEMW* 11 10 16 15 SD<15..0> 7 SA<16..0> SBHE* 4 1 BALE 2 26 3 23 12 13

LA<23..17>

5 MEMCS16*

IOCHRDY

Note 1

Note 1: IOCHRDY timings apply if deasserted. See Figure 4.

Figure 1. 16-bit Memory Timing

ISA Bus Timing Diagrams

8 IOR*, IOW*

13

11

10 16 15

SD<15..0> 7 SA<15..0> SBHE* 18 IOCS16* 23 BALE 19 12

IOCHRDY

Note 1

Note 1: IOCHRDY timings apply if deasserted. See Figure 4.

Figure 2.

16-bit I/O Timing

8 MEMR* MEMW* IOR* IOW* 11 10 16 15 SD<7..0> 7 SA<19..0> 4 1 BALE 2 26 3 23 12

13

LA<23..17> 5 6

MEMCS16*

IOCHRDY

Note 1

Note 1: IOCHRDY timings apply if deasserted. See Figure 4.

Figure 3.

8-bit Memory and I/O Timing

ISA Bus Timing Diagrams

SMEMR* SMEMW* IOR* IOW*

20

21

22

IOCHRDY

25

SD<15..0>

Figure 4.

IOCHRDY Timing

SYSCLK 29 28 ENDXFR* 36 27

LA<23..17>

37 SA<19..0> 17 8c MEMW* MEMR* 10c SD<15..0>

IOCHRDY

Note 1: Assertion of ENDXFR* within the maximum time from command is only required for a 16-bit cycle with zero wait states. Otherwise, ENDXFR* may be asserted at any time during the cycle while command is asserted.

Figure 5.

ENDXFR* Timing

ISA Bus Timing Diagrams

REF

DESCRIPTION

DRIVER
MIN MAX

RECEIVER
MIN MAX

1a 1b 2 3a 3b 4a 4b 4c 5 6 7 8 9a 9b 10 11a 11b 12 13a 13b 13c 14 15 16

DACKn*, AEN setup to IOR* DACKn*, AEN setup to IORW* Address setup to MEMW*, IOW* IOR* setup to MEMW* MEMR* setup to IOW* Data access from IOR* 8/16bit Data access from MEMR* 16bit Data access from MEMR* 8bit Data setup to IOW* unasserted Read command hold from write command SBHE*, address hold Data hold from read command IOCHRDY deasserted from 16bit memory command IOCHRDY deasserted from 8bit memory command TC hold from command unasserted IOR* pulse width MEMR* pulse width IOW*, MEMW* width DACKn* hold from IOW* DACKn* hold from IOW* AEN hold from command DREQ inactive from IOx* IOCHRDY low width TC setup to command unasserted

76 321 102 246 0 220 173 332 164 50 53 11 81 384

65 310 91 234 0 242 195 337 142 39 42 0 103 406

60 797 547 500 114 173 41 119 Tclk 511 15600

49 786 536 489 103 162 30 141 Tclk 500 15611

Table 2. DMA Timing

Notes 1 and 4 DRQn

14

13

DACKn* 2 SA<16..0> SBHE LA <23...17> 1a 11 7

IOR*, MEMR* 1b 3 IOW*, MEMW* 4 5 8 12 6

SD<15..0>

16

10

TC

Note 2 IOCHRDY

15

AEN

Note 1: DRQn may be deasserted any time after DACKn* during a block mode DMA transfer. Note 2: IOCHRDY may be deasserted to insert additional wait states. Additional bus wait states are added in units of two bus clocks. Note 3: The DMA controller activates TC during the last cycle of a DMA request. Note 4: DMA transfers may be broken up into multiple back-to-back cycles where the DMA controller removes DACKn* and optionally releases the bus to allow higher priority cycles to occur. In this case, DACKn* will be temporarily deasserted even though DRQn is still asserted.

ISA Bus Timing Diagrams

Figure 6. DMA Timing

REF

DESCRIPTION

DRIVER
MIN MAX

RECEIVER
MIN MAX

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

MEMR* pulse width SA<0...7> setup to MEMR* SA<0...7> hold from MEMR* IOCHRDY deasserted from MEMR* MEMR* deasserted from IOCHRDY REFRESH* setup to MEMR* REFRESH* hold from MEMR* (Note 1) SA<11...0> tri-state from MEMR* high IOCHRDY width AM ownership delay (Note 2) AEN asserted to REFRESH* active AEN hold to REFRESH* inactive REFRESH* asserted to SA<0...7> valid REFRESH* hold from SA<0...7> valid Address and Control disabled to REFRESH* asserted Table 3. Refresh Timing

214 81 36 81 125 125 31 250 Tclk Tclk 2*Tclk 11 11 11 11 0

203 70 25 159 125 114 20 239

Tclk 2*Tclk 0 0 0 0 0

10

6 REFRESH* 15 13 SA<7..0>

14

2 MEMR* 4 IOCHRDY

10

11 AEN

12

Note 1: The temporary master may exceed the maximum REFRESH* hold time in order to conduct another refresh operation. Note 2: The temporary master, if the current master, must tri-state the address and command signals prior to driving REFRESH* high (1).

Figure 7. REFRESH Timing

11