PROJECT REPORT ON METRO TRAIN PROTOTYPE

BY CETPA INFOTECH PRIVATE LIMITED

CONTENTS 1. 8051 Microcontroller Architechture 2. Variant in Atmel 8051 Microcontrollers 3. Features of AT89c51, AT89c52 and AT89s51 4. Features of LCD Used 5. Features of Stepper Motor and its Driver IC 6. PCB Layout 7. Source Code in Assemby 8. Component List. 9. Appendix 10. Bibliography

8051 Microcontroller Architechture AT89C51:

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.

Pin Configurtion

The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.

Pin Description
VCC Supply voltage. GND 33333Ground. Port 0

Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89C51 as listed below: Port 3 also receives some control signals for Flash programming and verification.
RST

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
ALE/PROG

Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE

pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has noeffect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to V CC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Oscillator Characters: XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

Idle Mode
In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabledinterrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

Programming the Flash

The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside the users system, while the high-voltage programming mode is compatible with conventional thirdparty Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table. To program the AT89C51, take the following steps. 1. Input the desired memory location on the address lines.

2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all 1s. The chip erase operation must be executed before the code memory can be re-programmed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. (030H) = 1EH indicates manufactured by Atmel (031H) = 51H indicates 89C51 (032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming

Programming The AT89C51

AT89C52:
Features Compatible with MCS-51 Products 8K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-level Program Memory Lock 256 x 8-bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Counters Eight Interrupt Sources Programmable Serial Channel Low-power Idle and Power-down Modes

Description
The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industrystandard 80C51 and 80C52 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.

Pin Diagram

The AT89C52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector twolevel interrupt architecture, a full-duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89C52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset. Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke.

Data Memory
The AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. new features. In that case, the reset or inactive values of the new bits will always be 0.
Timer 2 Registers

Control and status bits are contained in registers T2CON and for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16bit auto-reload mode.
Interrupt Registers

The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.r. specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.

Timer 0 and 1
Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in the AT89C51.

Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.

Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1- to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into CAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt.

Auto-reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD. Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.

Interrupts
The AT89C52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that bit position IE.6 is unimplemented. In the AT89C51, bit position IE.5 is also unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.

AT89S51:
The AT89LS51 is a low-voltage, high-performance CMOS 8-bit microcontroller with 4K bytes of in-system programmable Flash memory. The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industrystandard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89LS51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89LS51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89LS51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. Rest all function of this Atmel Series Microcontroller is same as its other members.

Architecture Features:
8-Bit CPU Optimized for Control Applications Extensive Boolean Processing Capabilities (Single-Bit Logic) On-Chip Flash Program Memory On-Chip Data RAM Bidirectional and Individually Addressable I/O Lines Multiple 16-Bit Timer/Counters Full Duplex UART Multiple Source/Vector/Priority Interrupt Structure On-Chip Clock Oscillator On-chip EEPROM (AT89S series) SPI Serial Bus Interface (AT89S Series) Watchdog Timer (AT89S Series)

Memory Organization
Logical Separation of Program Data Memory
All Atmel Flash microcontrollers have separate address spaces for program and data memory. The logical separation of program and data memory allows the data memory to be accessed by 8-bit addresses, which can be more quickly stored and manipulated by an 8- bit CPU. Nevertheless, 16-bit data memory addresses can also be generated through the DPTR register. Program memory can only be read. There can be up to 64K bytes of directly addressable program memory. The read strobe for external program memory is the Program Store Enable signal (PSEN). Data memory occupies a separate address space from program memory. Up to 64K bytes of external memory can be directly addressed in the external data memory space. The CPU generates read and write signals, RD and WR, during external data memory accesses. External program memory and external data memory can be combined by applying the RD and PSEN signals to the input of an AND gate and using the output of the gate as the read strobe to the external program/data memory.

Program Memory
After reset, the CPU begins execution from location 0000H. each interrupt is assigned a fixedlocation in program memory. The interrupt causes the CPU to jump to that location, where it executes the service routine. External Interrupt 0, for example, is assigned to location 0003H. If External Interrupt 0 is used, its service routine must begin at location 0003H. If the interrupt is not used, its service location is available as general purpose program memory. The interrupt service locations are spaced at 8-byte intervals:

0003H for External Interrupt 0, 000BH for Timer 0, 0013H for External Interrupt 1, 001BH for Timer 1, and so on. If an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use. The lowest addresses of program memory can be either in the on-chip Flash or in an external memory. To make this selection, strap the External Access (EA) pin to either VCC or GND. For example, in the AT89C51 with 4K bytes of on-chip Flash, if the EA pin is strapped to VCC, program fetches to addresses 0000H through 0FFFH are directed to the internal Flash. Program fetches to addresses 1000H through FFFFH are directed to external memory. In the AT89C52 (8K bytes Flash), EA = VCC selects addresses 0000H through 1FFFH to be internal and addresses 2000H through FFFFH to be external. If the EA pin is strapped to GND, all program fetches are directed to external memory. The read strobe to external memory, PSEN, is used for all external program fetches. Internal program fetches do not activate PSEN. The hardware configuration for external program execution. Note that 16 I/O lines (Ports 0 and 2) are dedicated to bus functions during external program memory fetches. Port 0 (P0 in Figure 5) serves as a multiplexed address/data bus. It emits the low byte of the Program Counter (PCL) as an address and then goes into a float state while waiting for the arrival of the code byte from the program memory. During the time that the low byte of the Program Counter is valid on P0, the signal ALE (Address Latch Enable) clocks this byte into an address latch. Meanwhile, Port 2 emits the high byte of the Program Counter (PCH). Then PSEN strobes the external memory, and the microcontroller reads the code byte.

Program Memory

Program memory addresses are always 16 bits wide, even though the actual amount of program memory used may be less than 64K bytes. External program execution sacrifices two of the 8-bit ports, P0 and P2, to the function of addressing the program memory.

Data Memory
The right half of the internal and external data memory spaces available on Atmels Flash microcontrollers. Hardware configuration for accessing up to 2K bytes of external RAM. In this case, the CPU executes from internal Flash. Port 0 serves as a multiplexed address/data bus to the RAM, and 3 lines of Port 2 are used to page the RAM. The CPU generates RD and WR signals as needed during external RAM accesses. You can assign up to 64K bytes of external data memory. External data memory addresses can be either 1 or 2 bytes wide. One-byte addresses are often used in conjunction with one or more other I/O lines to page the RAM. Twobyte addresses can also be used, in which case the high address byte is emitted at Port 2. Internal data memory addresses are always 1 byte wide, which implies an address space of only 256 bytes. However, the addressing modes for internal RAM can in fact accommodate 384 bytes. Direct addresses higher than 7FH access one memory space, and indirect addresses higher than 7FH access a different memory space. Thus, the Upper 128 and SFR space occupying the same

block of addresses, 80H through FFH, although they are physically separate entities. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers as R0 through R7. Two bits in the Program Status Word (PSW) select which register bank is in use. This architecture allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing.

Programming Status Word:

The Instruction Set

All members of the Atmel microcontroller family execute the same instruction set. This instruction set is optimized for 8- bit control applications and it provides a variety of fast addressing modes for accessing the internal RAM to facilitate byte operations on small data structures. The instruction set provides extensive support for 1-bit variables as a separate data type, allowing direct bit manipulation in control and logic systems that require Boolean processing. The following overview of the instruction set gives a brief description of how certain instructions can be used.

Program Status Word

The Program Status Word (PSW) contains status bits that reflect the current state of the CPU. The PSW, shown in Figure 11, resides in SFR space. The PSW contains the Carry bit, the Auxiliary Carry (for BCD operations), the tworegister bank select bits, the Overflow flag, a Parity bit, and two user-definable status flags. The Carry bit, in addition to serving as a Carry bit in arithmetic operations, also serves as the Accumulator for a number of Boolean operations. The bits RS0 and RS1 select one of the four register banks shown in Figure 8. A number of instructions refer to these RAM locations as R0 through R7. The status of the RS0 and RS1 bits at execution time determines which of the four banks is selected. The Parity bit reflects the number of 1s in the Accumulator: P=1 if the Accumulator contains an odd number of 1s, and P=0 if the Accumulator contains an even number of 1s. Thus, the number of 1s in the Accumulator plus P is always even. Two bits in the PSW are uncommitted and can be used as general purpose status flags.

Addressing Modes
The addressing modes in the Flash microcontroller instruction set are as follows.

Direct Addressing
In direct addressing, the operand is specified by an 8-bit address field in the instruction. Only internal data RAM and SFRs can be directly addressed.

Indirect Addressing
In indirect addressing, the instruction specifies a register that contains the address of the operand. Both internal and external RAM can be indirectly addressed. The address register for 8bit addresses can be either the Stack Pointer or R0 or R1 of the selected register bank. The address register for 16-bit addresses can be only the 16-bit data pointer register, DPTR.

Register Instructions
The register banks, which contain registers R0 through R7, can be accessed by instructions whose opcodes carry a 3- bit register specification. Instructions that access the registers this way make efficient use of code, since this mode eliminates an address byte. When the instruction is executed, one of the eight registers in the selected bank is accessed. One of four banks is selected at execution time by the two bank select bits in the PSW.

Register-Specific Instructions
Some instructions are specific to a certain register. For example, some instructions always operate on the Accumulator, so no address byte is needed to point to it. In these cases, the opcode itself points to the correct register. Instructions that refer to the Accumulator as A assemble as Accumulator-specific opcodes.

Indexed Addressing
Program memory can only be accessed via indexed addressing. This addressing mode is intended for reading look-up tables in program memory. A 16-bit base register (either DPTR or the Program Counter) points to the base of the table, and the Accumulator is set up with the table entry number. The address of the table entry in program memory is formed by adding the Accumulator data to the base pointer. Another type of indexed addressing is used in the case jump instruction. In this case the dest ination address of a jump instruction is computed as the sum of the base pointer and the Accumulator data.

Liquid Crystal Display Fundamentals

A general discussion of how liquid crystal displays work. A basic introduction to the chemistry, structure, and properties of liquid crystals used in displays. An overview of display structure, assembly, and related technology is summarized.

Liquid Crystal Displays (LCDs) are categorized as nonemissive display devices, in that respect, they do not produce any form of light like a Cathode Ray Tube (CRT). LCDs either pass or block light that is reflected from an external light source or provided by a back/side lighting system. There are two modes of operation for LCDs during the absence of an electric field (applied Power); a mode describes the transmittance state of the liquid crystal elements. Normal White mode: the display is white or clear and allows light to pass through and Normal Black Mode: the display is dark and all light is diffused. Virtually all displays in production for PC/Workstation use are normal white mode to optimize contrast and speed. A simplified description of how a dot matrix LCD display works is as follows: A twisted nematic (TN) LC display consists of two polarizers, two pieces of glass, some form of switching element or electrode to define pixels, and driver Integrated Circuits (ICs) to address the rows and columns of pixels. To define a pixel (or subpixel element for a color display), a rectangle is constructed out of Indium Tin Oxide -- a semi-transparent metal oxide (ITO) and charge is applied to this area in order to change the orientation of the LC material ( change from a white pixel to a dark pixel). The method utilized to form a pixel in passive and active matrix displays differs and will be described in later sections. Figure 1 illustrates a cross sectional view of a simple TN LC display. Figure 2 depicts a dot matrix display as viewed without its metal module/case exposing the IC drivers.

Looking directly at the display the gate or row drivers are located either on the left or the right side of the display while the data or column drivers are located on the top (and or bottom) of the display. New thin display module technology mounts the ICs on conductive tape that allows them to be folded behind the display further reducing the size of the finished module. An IC will address a number of rows or columns. Figure 1: Cross Section of a Simple LC Display
viewer ///////////////////////////////////// Polarizer _____________________________________ glass ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Liquid Crystal _____________________________________ glass \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ Polarizer Backlight

Figure 2: LCD panel and IC driver locations

________________________________________ | | | IC IC | Source/Column ICs

| | | | | | |IC---------------------Pixel | | | |IC <---- Gate Line/Row IC | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

* An IC driver will address a number of row/column lines and not just the single pixel in the diagram above Polarizers are an integral part of a LCD display, possessing the unique property of only passing light if it is oriented in a specific (oriented) direction. To utilize this phenomena in TN LC displays, the bottom polarizer orients incoming light in one direction. The oriented light passes through the LC material and is either unaltered or "bent" 90 degrees. Depending on the orientation of the top polarizer, this light will either pass through or be diffused. If the light is diffused, it will appear as a dark area. Figure 3 is a simple illustration of the sequence of events that occur when light passes through a simple twisted nematic LC display.

Liquid Crystal Material

The liquid crystals used for display technology are thermotropic liquid crystals; they exhibit desired characteristics over a specific temperature range. This is the primary reason why LCDs do not operate properly when they are too cold or too warm. If liquid crystals are too cold, they will not twist and the display will not form an image. If the display is too warm, the resistance of the liquid crystal material changes and this alters the properties of the display and performance suffers. Liquid crystal material for display use is normally referred to as TN (STN, DSTN, MSTN, and etc.) or Twisted Nematic--sometimes known as TNFE or Twisted Nematic Field Effect. It is called TWISTED since the crystals are twisted 90 degrees (or more for STN) from the top piece of glass to the bottom piece of glass. (TN usually refers only to a 90 degree twist.) Field Effect (a direct correlation is the semiconductor MOSFET), refers to the LC material's ability to align parallel or perpendicular to an applied electric field. As a result, using twisted or untwisted liquid crystal and two polarizers; an applied electric field can force the LC material into a particular alignment effectively diffusing or passing light through the top polarizer. As a note of interest, polarizers are also one of the major reasons that LC displays require bright back lighting. The polarizers and liquid crystal materials absorb more than 50% of the incident light. As a result, even though the actual display is a very low power device, the power hungry back lighting makes a LCD module one of the primary causes of short battery life in notebook computers. Due to the fact that the LC material has optical properties and effectively bends light, the problem of viewing angle effects occur. When the user is not directly in front of the display the image can disappear or seem to invert (dark images become light and light images become dark). However, LC material and polarizer technology is rapidly improving and that improvement is showing up in brighter displays with greater viewing angles.

Liquid Crystal Alignment

Liquid crystals must be aligned to the top and bottom pieces of glass in order to obtain the desired twist. In other words, the 90 degree twist is formed by anchoring the liquid crystal on one glass plate and forcing it to twist across the cell gap (the distance between the two glass plates) when contacting the second plate. Furthermore, The actual image quality of the display will be dependent on the surface alignment of the LC material. The method currently used for aligning liquid crystals was developed by the Dai-Nippon Screening (English= Big Japan Screening) Company. The process consists of coating the top and bottom sheets of glass with a Polyimide based film. The top piece of glass is coated and rubbed in a particular orientation; the bottom panel/polyimide is rubbed perpendicular (90 degrees for TN displays) with respect to the top panel. It was discovered that by rubbing the polyimide with a cloth, nanometer (1 X 10 - 9 meters) size grooves are formed and the liquid crystals align with the direction of the grooves. It is common that when assembling a TN LC cell, it will be necessary to eliminate patches of nonuniform areas. The two parameters required to eliminate the nonuniformities and complete the TN LC display are pretilt angle and cholesteric impurities. TN LC cells commonly have two problems that affect uniformity following assembly: reverse tilt and reverse twist. Reverse tilt is a function of the applied electrical field and reverse twist is common when no electrical field is applied. Reverse twist is eliminated by the introduction of cholesteric additives and reverse tilt is eliminated by introducing a pre-tilt angle to the LC material. The pre-tilt angle also determines what direction the LC molecules will rotate when an electrical field is applied. Pre-tilt angle can be visualized by considering the normal position of the LC molecule to be flat against the glass plate, by anchoring one edge and forcing the other upward by a specific number of degrees, a pretilt angle is established.

Stepper Motor Fundamentals and Details:

Introduction

Stepper motors are commonly used in accurate motion control. They allow to control any motion with high precision by counting the number of steps applied to the motor. Most of systems controlling stepper motors are embedded systems such as printer, scanner or floppy disk drive. This application note describes how to drive a unipolar stepper motor with the Programmable Counter Array of an Atmel C51/C251 microcontroller. There are two major types of stepper motors: Permanent magnet stepper motors (unipolar stepper motors and bipolar stepper motors) and variable reluctance stepper motors (hybrid stepper motors).

Identification of Stepper Motor

There are several types of stepper motors, these cannot be driven in the same way. In this application note, we have chosen to drive a unipolar stepper motor For more information you will find schemes to identify the other types of stepper motors. Unipolar Stepper Motor Unipolar stepper motors are characterised by their center-tapped windings. Unipolar Stepper Motor

Bipolar Stepper Motor Bipolar stepper motors are designed with separate coils. Bipolar Stepper Motor

Variable Reluctance Variable reluctance stepper motor (also called hybrid motors) are characterised by one common lead.

Variable Reluctance Stepper Motor

Driving Unipolar Stepper Motors

There are three ways to drive unipolar stepper motors (one phase on, two phase on or half step), each one has some advantages and disavantages.

There are two stages to sorting out which wire is which in a 5- or 6-wire unipolar stepper motor:

1. Isolate the Common Power wire(s) by using an ohmmeter to check the resistances
between pairs of wires. The Common Power wire will be the one with only half as much resistance between it and all the others. This is because the Common Power wire only has one coil between it and each other wire, whereas each of the other wires have two coils between them. Hence half the resistance. 2. Identify the wires to the coils by supplying a voltage on the Common Power wire(s) and keeping one of the other wires grounded while grounding each of the remaining three wires in turn and observing the results. Select one wire and ground it Assume it's connected to coil 4. Keeping it grounded, ground each of the other three wires one by one Grounding one wire should make the rotor turn a little clockwise. That'll be the wire connected to Coil 3. Grounding one wire should make the rotor turn a little anticlockwise. That'll be the wire connected to Coil 1. Grounding one wire should do nothing That'll be the wire connected to Coil 2.

Stepper Motor Driver IC ULN2003

Pin Connection:

Voltage Regulator IC (Electrical Characteristics of MC7805):

The MC78XX/LM78XX/MC78XXA series of three terminal positive regulators are available in the TO-220/D-PAK package and with several fixed output voltages, making them useful in a wide range of applications. Each type employs internal current limiting, thermal shut down and safe operating area protection, making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 1A output current. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltages and currents.

Features
Output Current up to 1A Output Voltages of 5, 6, 8, 9, 10, 12, 15, 18, 24V Thermal Overload Protection Short Circuit Protection Output Transistor Safe Operating Area Protection

Pin Diagram of the Power IC

Typical Applications

Notes:
(1) To specify an output voltage. substitute voltage value for "XX." A common ground is required between the input and the Output voltage. The input voltage must remain typically 2.0V above the output voltage even during the low point on the input ripple voltage. (2) CI is required if regulator is located an appreciable distance from power Supply filter. (3) CO improves stability and transient response.

SHCEMATIC DIAGRAM:

PCB Layout:

PROGRAM in Assembly:

$mod51 dat equ p1 busy equ p1.7 rs equ p3.5 rw equ p3.4 en equ p3.3 bzr equ p0.2 ledf equ p0.0 ledb equ p0.1

org 0000h ajmp main

org 0003h test: mov c,p3.2 jnc halt setb bzr reti halt:

clr bzr ajmp test

;till zero blow on the bzr

main: mov ie,#00h setb ea ;setb ex0 here: mov p2,#00h acall ini mov dptr,#show0 acall read clr ledf acall delay ;p1.0

mov a,#01h acall command; Now make memory clear cursor home mov dptr,#show1 acall read setb ex0 mov a,#0c0h acall command ;#############

mov dptr,#show3 acall read acall delay ;Stopage1 time 3 sec rookee acall delay clr bzr acall delay

mov a,#01h acall command mov dptr,#show2 acall read mov a,#0c0h acall command mov dptr,#show4 acall read setb bzr acall delay10 acall stepperf

mov a,#01h acall command mov dptr,#show1

acall read mov a,#0c0h acall command mov dptr,#show4 acall read acall delay ;Stopage2 time 3 sec shsar acall delay clr bzr acall delay

mov a,#01h acall command mov dptr,#show2 ;display ne acall read mov a,#0c0h acall command mov dptr,#show5 acall read setb bzr acall delay10 acall stepperf

mov a,#01h acall command mov dptr,#show1 acall read mov a,#0c0h acall command mov dptr,#show5 acall read acall delay ;Stopage2 time 3 sec Meerut acall delay clr bzr acall delay

setb ledf clr ledb ;

; p1.0 ;off led at p1.0 for forward journey p1.1 ; 0n Led for back ward journey

mov a,#01h acall command mov dptr,#show2 ;display ne acall read mov a,#0c0h acall command shar

mov dptr,#show4 acall read setb bzr acall delay10 acall stepperb

mov a,#01h acall command mov dptr,#show1 acall read mov a,#0c0h acall command mov dptr,#show4 acall read acall delay ;Stopage2 time 3 sec shsar acall delay clr bzr acall delay

mov a,#01h acall command mov dptr,#show2 ;display ne roor

acall read mov a,#0c0h acall command mov dptr,#show3 acall read setb bzr acall delay10 acall stepperb

mov a,#01h acall command mov dptr,#show1 acall read mov a,#0c0h acall command mov dptr,#show3 acall read setb ledb ljmp here ;p1.1

;routine for stepper motor

; Delay Routine ;one sec delay delay: push acc push 00h push 01h push p0 push p1 mov r0,#0eh loopr: mov a,#0ffh loopb: mov b,#0ffh loopa: djnz b,loopa djnz 0e0h,loopb djnz r0,loopr pop p1 pop p0 pop 01h pop 00h pop acc

ret

;dlay stepper delays: push acc push 00h push 01h push p0 push p1

mov a,#0ffh loopa1: mov b,#0fh loopb1: djnz b,loopb1 djnz 0e0h,loopa1

pop p1 pop p0

pop 01h pop 00h

pop acc ret

delay10: mov tmod,#01h mov tcon,#00h mov tl0,#0f0h mov th0,#0f8h setb tr0 no: jnb tf0,no clr tr0 clr tf0 ret ;=============== Routine to read data from prog mem

read: nex: clr a movc a,@a+dptr cjne a,#'0',aga sjmp down aga: acall display inc dptr

sjmp nex down: ret ;================ stepper routine

stepperf: push acc push p1 mov a,#88h mov r1,#04h loop1: mov r0,#0e0h loop: mov p2,a acall delays rr a djnz r0,loop djnz r1,loop1 pop p1 pop acc ret

stepperb:

push acc push p1 mov a,#88h mov r1,#04h loop12: mov r0,#0e0h loop0: mov p2,a acall delays rl a djnz r0,loop0 djnz r1,loop12

pop p1 pop acc

ret ;******************************************************* ;LCD strobe subroutines ini: mov a,#38h acall command mov a,#38h

acall command mov a,#38h acall command mov a,#38h acall command mov a,#0eh acall command mov a,#06h acall command mov a,#01h acall command mov a,#80h acall command ret

command: acall ready mov dat,a clr rs clr rw setb en clr en

ret

display: acall ready mov dat,a setb rs clr rw setb en clr en ret

ready: clr en mov dat,#0ffh clr rs setb rw wait: clr en setb en jb busy,wait clr en ret

show0: db 'Welcome To All','0' show1: db 'CURRENT STATION','0' show2: db 'NEXT STATION','0' show3: db 'ROORKEE','0' show4: db 'MEERUT','0' Show5: db 'DELHI','0' end

Components List for Project

AT89c51 ULN2003 Stepper Motor 2 Line LCD Buzzer LED 1 1 1 1 1 3

Resistances 4.7K 470 ohm

(10K)

5 5 5 2 1 2 1 4 1 each 1 each 2 1 1 1 1 1

33picofarad Ceramic Disk Capacitor Crystal Osci. (12 MHz) Mini Switch 10K Pot (Preset) Diode 1n4007 IC Base (16Pin, 40Pin, 8Pin) Relimate (5 pin and 2 pin) Relimate (16pin) Power chord Capacitor 100Microfarad/ 25v Capacitor 470 Microfarad / 25v Power IC 7805 Transformer (9-0-9)