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A New DC Offset Removal Algorithm Using an Iterative Method for Real-Time Simulation
Gilsung Byeon, Student Member, IEEE, Seaseung Oh, Member, IEEE, and Gilsoo Jang, Senior Member, IEEE
AbstractIn this paper, a new dc offset removal algorithm for real-time simulations is proposed. Physically transferred signals in a real-time simulation interface tend to contain a dc offset component for various reasons. This component decreases the accuracy and stability of real-time simulations. The dc offset tends to change according to circumstances which include changes in the system conguration and effects of the external environment which makes the static dc offset removal scheme inefcient. The proposed algorithm can estimate and remove a dc offset component dynamically from the input signal of the hardware under test. In the proposed algorithm, the optimal constant for the condition equation is calculated by using an iterative method and is used to estimate the frequency, time, magnitude, and dc offset component of the input signal. Four sampling points are used to calculate the optimal constant in each step. The proposed algorithm has relatively fast speed and good accuracy in comparison to conventional dc offset removal algorithms. In order to verify the performances of the proposed algorithm, ofine and real-time dc offset estimation simulation tests were performed. The results of the simulation tests showed that the proposed algorithm can estimate the dc offset component promptly and exactly and can be applied to real-time simulations. Index TermsCalibration, dc estimation, dc offset, dc removal, iterative method, real-time simulation.

Fig. 1. Basic diagram of hardware-in-the-loop simulation.

I. INTRODUCTION

EAL-TIME simulations, in which the technique of a simulation of a system is being performed in the same time scale as the corresponding behavior of the system itself, has been used for many years for testing hardware (hardware in the loop or open loop) and software (e.g., prototype car under new load conditions and training aircraft pilot) [1], [2]. In real-time simulations of physical devices and systems, the physical time and the simulation time are the same. This technique provides many advantages that other analysis and testing methods do not provide. An engineer can constitute a simulation test-bed system that has the same characteristics as the real system where the components can be conveniently changed in order to observe different effects, in order to achieve a more efcient analysis of

Manuscript received August 05, 2010; revised February 08, 2011; accepted April 06, 2011. This work was supported by the National Research Foundation of Korea (NRF) Grant funded by the Korea government (MEST) (No. 20100018462). Paper no. TPWRD-00589-2010. G. Byeon and G. Jang are with the School of Electrical Engineering, Korea University, Seoul 136-701, Korea (e-mail: bgsean@korea.ac.kr; gjang@korea.ac.kr). S. Oh is with the BK21 of the Department of Electrical Engineering, Myongji University, Myongi, Korea (e-mail: shung@mju.ac.kr). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPWRD.2011.2142405

those effects on a real power system [3][5]. Real-time simulations enable engineers to save money and time usually spent on the installation of real systems for the purposes of study, and to protect themselves from any hazardous conditions. Among the various applications of this technique, the hardware-in-the-loop (HIL) simulation has been recently introduced to various elds of power systems. The HIL simulation system is composed of a virtual simulation system (VSS) and the hardware under test (HUT). The HIL system is a closed loop, owing to the interconnection of the VSS and the HUT. The simple diagram of the HIL simulation system is shown in Fig. 1 [6], [7]. The most severe problem due to dc offset inclusion in the real-time signal is the decrease of accuracy. In order to evaluate and improve the performance of the HUT, the engineer wants to obtain accurate real-time simulation results. Since unwanted dc offset between VSS and HUT does not appear in ofine simulations, accurate simulation results can be obtained. However, in real-time simulations, it is possible for the engineer to obtain inaccurate simulation results caused by the absence of the calibration system, incorrect calibration, and external factors. According to the test system conguration and its control scheme, fatal errors, such as simulation termination caused by divergence of close-loop errors, can occur in some cases. Harmonics as well as dc offset component and noise, which are the main distortion effects that are caused, are included in physical signals by various external factors during the data transfer. Generally, harmonics and noise are easily removed using well-designed lters, but the dc offset component is not eliminated completely. Moreover, it is very difcult to remove a changing dc offset on the simulation using existing calibration methods in real-time simulators. Therefore, it is not the intentional/necessary dc offset that should be removed but the unwanted dc offset caused by calibration failure to improve the accuracy of the real-time simulation. Until now, several methods have been proposed for the removal of the dc offset component. The discrete Fourier transform suppresses the effect of an exponentially decaying dc

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offset component over a wide range of time constants. However, it has the best performance when the time constant (X/R) of the dc offset matches the one in the mimic lter [8]. A modied DFT that requires one cycle plus two samples to remove the dc offset component was proposed in [9]. The algorithm using a weighting least error square (LES) was proposed in [10]. The algorithm that eliminates the decaying dc offset from the phasor estimates using modied DFT lters is proposed in [11]. However, the calculation of the dc offset using this technique is complex and increases the computational burden. Therefore, this technique is unsuitable for real-time simulation. Sidhu et al. improves the algorithm using three lookup tables in order to reduce the computational burden [12] and half-cycle LES lters [13]. Reference [14] has implemented the global optimization technique in order to estimate the dc offset parameters. The modied DFT algorithm that uses the recursive relationship between the even and odd sample sets was proposed in [15] and [16]. In [17], the dc offset is estimated and eliminated by calculating the integral of the fault current signal for a cycle. Most of the aforenementioned algorithms are developed mainly for protection relay applications. The DFT, LES, and its modied algorithms, which are representative algorithms, mainly focus on the removal of the exponentially decaying dc offset component. The main drawback of all proposed algorithms is the slow response because most algorithms use one or half-cycle samples to estimate the dc offset parameters. Also, some of them are not suitable for real-time simulation, owing to the extensive amount of computation. For application to real-time simulations, the algorithm must be simple to avoid the computational burden and not be restricted to the exponentially decaying dc offset component. In this paper, we describe a new algorithm to estimate and eliminate the dc offset component in the transmitted input signal for real-time simulation. The mathematical derivation of the proposed algorithm is described. The optimal constant by iterative solution is calculated and used to estimate the required parameters. In order to verify the proposed algorithm, we performed ofine and real-time simulation tests to estimate the dc offset component. Also, other parameters, such as the optimal constant, frequency, and iteration number are shown and discussed. The proposed algorithm is a software type and it can be applicable to real-time simulators and devices which enable built-in programmable user-dened modules. Recently, most real-time devices or simulators, such as RTDS, OPAL-RT, LabVIEW, HyperSim, and so on have their own built-in UDC program. In some cases, the real-time device, which is to be located between the VSS and the HUT, does not support the application of the proposed algorithm. However, it is possible to remove all dc offset components if the device where the transferred signal nally is received can support UDCs. Since the proposed algorithm can be applied selectively, the engineer can decide where this algorithm is installed exibly according to the characteristics of the test system. The major applications of this proposed algorithm can be as follows: relay tests, which need to remove the decaying dc offset component [3], [8][17].

interconnection between VSS and HUT in PHIL simulation [6], [7], [19]; parameters (frequency, time, amplitude, and so on) estimation of the nput signal for other applications. This paper is organized as follows. Section II describes the calibration problem and its effects on real-time simulation in detail. Section III represents the mathematical derivation of the proposed algorithm for estimation of the dc offset component from the transmitted input signal. The results of the simulation tests are described and discussed in Section IV. Some comments about further work and conclusions are presented in Section V. II. CALIBRATION IN REAL-TIME SIMULATION Signals are transmitted through a physical interface between the VSS and the HUT in a real-time simulation system. For example, in Fig. 1, if the researcher wants to transmit the voltage measurement signals of the interface bus from the VSS to the HUT using input/output (I/O) devices, the digital signal of the VSS is rst converted to an analog signal in the output device, and it is then transmitted to the signal amplier through a cable or an optical ber. The signal amplier is the device that amplies signals in order to adapt to the HUTs rated input signal level. The signal amplied by the signal amplier reaches the input device in the HUT. This procedure is the most basic but also the most essential step required in a real-time simulation system for transmitting the signal from the VSS to the HUT. If the I/O devices and cables in a real-time simulation system do not ensure data integrity, it is possible that the transmitted signal is distorted in the nal destination. The calibration failure of the I/O device terminal in the signal amplier, the VSS and HUT, noise in cables and wires, and the effects of the external environment all distort the original signals and, thus, affect the accuracy of the nal simulation results. Among these errors, the high-frequency noise and harmonics can be eliminated efciently by well-tuned lters. However, the removal of the dc offset component has always been an issue to be tackled since pre-existing methods have not been able to eliminate the error completely or efciently. Especially, this issue is a very crucial factor to be considered in power systems and HIL simulations. A power system has inductive elements, and the relationship between the voltage and current is dened as the numerical integration in the power system simulation algorithm [18]. The error resulting from the dc offset component is accumulated by the numerical integration. Moreover, this error feeds back into the system and produces a continuative error owing to the characteristics of the closed loop in the case of the HIL simulation [19]. Accurate I/O adjustment of devices used in real-time simulation is the best alternative to improve simulation accuracy. The proposed algorithm can be used for ancillary methods to support cases where the calibration scheme is imperfect or absent. The major reasons why the calibration scheme is not perfect are the inaccuracy caused by manual calibration scheme, inaccurate calibration reference, and changing of the dc offset on simulation. Actually, the engineer has to strive for accurate calibration of each I/O device because many devices provide only a manual calibration scheme up to now and it takes much time and manual effort (the engineer adjusts calibration screws in I/O devices

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BYEON et al.: NEW DC OFFSET REMOVAL ALGORITHM 3

manually). Even though the engineer can perform manual calibration accurately, it is possible that there is a doubtful dc offset component caused by the external environmental components (e.g., electromagnetic eld, defects in cable and wire, etc.). If a new device is added, or other I/O terminals are used, extra manual calibration must be performed. Moreover, the changing dc offset on simulation cannot be removed unless the calibration scheme changes its reference in real time. For example, the ON-OFF operation of the photovoltaic (PV) inverter due to the variable output characteristic of the PV system can change the dc offset of the neighboring real-time simulation. In these cases, the proposed algorithm can be an appropriate alternative. Therefore, in this paper, an active and dynamic method is proposed for the estimation and removal of the dc offset component. If the input signal has an intentional/necessary dc offset and unwanted dc offset together, the intentional/necessary dc offset, which is an essential and meaningful component, must not be removed. In this case, the selective application of the dc removal algorithm is required to just remove the unwanted dc offset for accurate simulation. III. PROPOSED ALGORITHM On the assumption that the VSS, HUT, and other devices in a power system use ac voltage and current signals for a real-time simulation system, the proposed algorithm in this paper is based on a mathematical approach using sampling data from a sinusoidal input signal. The optimal constant for the condition equation is calculated by using an iterative method which is then used for estimating the frequency, time, amplitude, and the dc offset component values of the input signal. Four sampling points are used in order to calculate the optimal constant in each step. In most real-time simulators, there is a limitation in the size of the system to be analyzed and complexity of the user-dened model (or algorithm) to enable real-time simulation. For the practical application of the proposed algorithm, it must be designed to conduct all of the procedures in each simulation time-step. In the proposed algorithm, some threshold and limit values for convergence in the iterative method are adjustable according to the performance of the real-time simulator. The relationship between the iterative number and the computational burden are described in this section. A. Derivation of the Condition Function First, it is assumed that four sampling points of the original sinusoidal input signal are extracted. The time difference between each point is one calculation time step of the real-time simulator that the input signal is entering into. If it is assumed that the differences between each dc offset of the sampling points is small , each sampling point can be represented by the use of a cosine function which includes a dc offset as shown (1) (2) (3) (4)

are In (1)(4), A, B, C, D, and the simulation time step known values that are acquired by sampling and measurement. , frequency , time , and dc offset compoThe amplitude nent are unknown values. The rearrangement of the simultaneous (1)(4) using a yields the equatrigonometric function to remove and tions (5) (6) (7) where is a certain constant that satises these relationships. Subtraction of (5) and (6) from (7) gives (8) (9)

B. Determination of Beta Using an Iterative Method In order to obtain , searching for a certain value is required, where the condition equation, which is dened as the equation obtained from the difference between (8) from (9), is zero condition (10) Here, the iteration algorithm is applied to obtain . The variation of the condition variable by the change in is represented in Fig. 2. This gure is a trace graph of the condition variable 100, , 60 Hz, in the case of . While the graph shape is changed little by variation of the parameters, the general shape of the trace is similar. The condition variable traces the bold line when changes from to zero and the thin line when changes from zero to . According to , the condition variable value might be a complex value or a real value. In the enlarged graph of region K in Fig. 2, two points satisfy the condition variable value of zero. One is a point when is zero, and the other point 1.88. The condition value of exists in the range 0 is an imaginary root that does not satisfy (5)(7). According to (5)(7), is always negative; therefore, the condition value 1.88 is a real root in this example. Fig. 3 in section 1.88. is a graph of the condition value for the range The axis is the condition variable value (the condition value is a real value in this gure) and the axis is in Fig. 3. When is zero, the condition value is zero. When decreases, the condition value decreases also. However, the condition value increases continuously from a specic , and the condition value passes through zero. If drops below 1.88, the condition value has an imaginary part as shown in Fig. 2. So, in this paper, an is determined by initial is selected and an improved using an iteration and convergence algorithm. The initial can be selected from (5)(7). Since the minimum value of the sine function is minus one ( 1.0), the initial is obtained by (11).

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Fig. 4. Arcsine function characteristics for the estimation of time value. Fig. 2. Trace graph of the condition variable (V f 60 Hz, t : e t ).

= 2 5 0 3 sec(501 )

= 100, 1t = 50e 0 6 s,

Fig. 3. Enlarged graph of region K in Fig. 2, and binary search.

This initial Fig. 3

is always located to the right of the real root in

Initial

(11)

Since the initial can either be a complex value or a real value, the selection of the iteration and convergence algorithm should be chosen to consider this factor. Therefore, a binary search is used in this paper. It can be applied regardless of whether the initial is complex or not. According to the sign of the condition value, the upper and lower bound are updated until the absolute value of the condition value is lower than the convergence limit. C. Estimation of the Frequency, Time, and Amplitude is determined, the frequency can be estimated by When in (8) and (9). If is accurate, the the substitution of estimated frequency value is accurately close to the original frequency value. Then, the time can be estimated by substituting the frequency in (5)(7). However, an auxiliary algorithm that
Fig. 5. Flowchart of the proposed algorithm.

will be shown is required due to the characteristics of the arcsine function.

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BYEON et al.: NEW DC OFFSET REMOVAL ALGORITHM 5

TABLE I ESTIMATED PARAMETERS AS CHANGE OF CONVERGENCE LIMIT (1000 SAMPLES)

Equation (5) is rearranged as follows: (12) Although the time is calculated by using , the arcsine function only returns the axis value in the shaded area owing to the dened bounds in general programming languages. As a result, point 2, which is used for calculating the time T2, returns time T1. In the same manner, Points 3, 4, 5 return T6 instead of T3, T4, and T5, respectively. However, the period of the sine function in (12) is the same as the period of the sampled points A, B, C, D (if the frequency is calculated exactly). Therefore, the compensated time value that is considered above the arcsine characteristic can be calculated by using the relationship of the four points. Then, the amplitude and the dc offset component that is included in the distorted signal are estimated by using the estimated frequency and time in (1)(4). The owchart of the proposed calibration algorithm is represented in Fig. 5. When the sinusoidal input signal is entered, is rst checked. If does not exist, is calculated by using the . From the second binary search algorithm, and it is dened as already exists, so does the condition value calculated time and it is rst compared with the accuracy threshold. by using If the condition value using is smaller than the accuracy is used to estimate the frequency, time, magnitude, threshold, and dc offset component without any iterative process. When the input signal that has the same parameters is entered for a certain time (steady state), this process is very useful, owing to the reductionofthecomputationalburden.Iftheinputsignalparametersare is larger than the accuchanged or the condition value using racy threshold, is calculated by using the iteration method, and the condition value is compared again with the previous condicontinuously. This algorithm is tion value in order to update effective since it can respond quickly to a change in the input, and reduce the computational burden efciently. Using the nally cal, the frequency, time, magnitude, and dc offset comculated ponent are estimated easily. D. Computational Burden and Accuracy Estimating an accurate value of is the same problem as how to make the condition variable value close to zero. The smaller the convergence limit, the more accurate becomes.

However, the hardware burden is more severe owing to an increase in the number of iterations. Table I represents the maximum iteration number, frequency error, time error, amplitude error, and dc offset component error with respect to the convergence limit. In this experiment, the amplitude, frequency, and dc offset of the input signal are 100, 60, and 10 Hz, and the binary search algorithm is used for convergence. The total simulation time is 0.05 s (a thousand sample data, 3 cycle). If the convergence limit decreases, the maximum iteration number increases. Especially, the iteration number increases when the sign of the second derivative of the input signal changes. This maximum iteration number is related to the computational burden. Although since it is possible for a recent real-time simulator to calculate 30 iteration processes in a simulation timestep, the engineer can determine the convergence limit to adjust the computational burden. As seen in Fig. 5, the proposed algorithm uses . If the conthe stored and updated optimal constant value vergence limit is smaller, the optimal constant is more accurate. So the maximum iteration number and steps without iteration increases. Also, the other parameters are more accurate according to the decrease of the convergence limit. From Table I, the setting of an appropriate convergence limit can satisfy the need for an accurate result and reduction of the computational burden. If the variation of the input signal parameters is not large, for a certain time period, extraction of the optimum value obtained by comparison with the historical condition value and using this method continuously is more effective than calculating by the use of an iterative method in every timestep. IV. SIMULATION RESULT AND ANALYSIS In order to verify the performance of the proposed algorithm, ofine and real-time simulation tests were performed. The rst simulation test was a steady-state simulation performed in order to observe the parameters related to the proposed algorithm. The second simulation test was a transient state. The performance of the proposed algorithm was compared with the cases of a conventional full-cycle DFT (FCDFT). The last simulation test is real-time simulation to identify the execution time and observe the performance of the proposed algorithm. A. Steady-State Simulation In order to observe the performance of the case when the dc offset component is changed by an external environment in the steady state, the programmed input signal as shown in Fig. 6(a) is entered. The dc offset is changed from 10.0 to 20.0 between

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Fig. 6. Estimated parameters in the steady-state simulation test. (a) Input signal and calibrated signal. (b) Estimated dc offset component of the proposed algorithm and conventional DFT and deviation from the original DC offset. (c) Estimated optimal beta of the proposed algorithm. (d) Estimated frequency of the proposed algorithm. (e) Estimated time of the proposed algorithm. (f) Iteration number of the proposed algorithm.

Fig. 7. Simple diagram of a test system.

0.05 s and 0.10 s. Fig. 6(b) represents the estimated dc offset component using the proposed algorithm and the conventional DFT and the deviation from the original dc offset component. Whilethe DFT uses full-cycle samples, the proposed algorithm uses only four samples to estimate the dc offset. Therefore, the proposed algorithm is much faster and accurate than the DFT. The deviation

is almost close to zero. The spike in Fig. 6(b) is the calculation error caused by the change of the sign of the second derivative value of the input signal. However, this error caused by the spike is not large enough to make the simulation unstable. Fig. 6(c)(e) show the estimated optimal , frequency, and time of the proposed algorithm. If the parameters, except for the dc offset, have not changed greatly, the optimal is nearly constant. Although the optimal and frequency have small oscillations during the initial short time, these parameters settled very fast because the algorithm nds the optimal quickly. The estimated time is repeated every cycle by compensation of the arcsine characteristics mentioned in Section III-C. Fig. 6(f) shows the iteration number of the proposed algorithm when the convergence limit is 1.0e-07. In order to calculate the optimal , some initial iteration processes are performed. After nding the optimal , only two or three steps

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Fig. 8. Estimated parameters in the transient state simulation test. (a) Input signal and calibrated signal. (b) Estimated dc offset component of the proposed algorithm and conventional DFT and deviation from the original dc offset. (c) Estimated optimal beta of the proposed algorithm. (d) Iteration number of the proposed algorithm.

B. Transient Simulation
TABLE II PARAMETERS OF THE TEST SYSTEM

Fault resistance: 0.01

.

perform iteration when the sign of the second derivative changes; the other steps do not have any iteration process. The maximum number of iterations of this case is 27 as shown in Table I. As described in the former section, the maximum iteration number of the algorithm is dependent upon the choice of the convergence technique and the convergence limit. As shown in Fig. 6, the proposed algorithm can estimate and remove the dc offset component fast and accurately.

In order to conrm the robustness of the proposed algorithm, the simulation test under a more severe condition is performed. Fig. 8(a) shows the signal where the fault current of the simple power system is shown as Fig. 7 and its original dc offset. Parameters of the test system are described in Table II. At 0.0375 s, AB ground faults occur which last for 0.05 s. The phase A current in bus 1 is used for the input signal to verify the performance of the proposed algorithm. Fig. 8(b) represents the estimated dc offset component using the proposed algorithm and conventional DFT and the deviation from the original dc offset component. Along with the steady-state simulation test, the DFT requires at least one cycle. However, the proposed algorithm estimates the changeable dc offset component very quickly. The deviation is almost close to zero as a steady-state case. Since the dc offset is ckle, the estimated changes continuously in Fig. 8(c). Fig. 8(d) represents the number of iterations of the proposed algorithm during a transient state when the convergence limit is the same as the one of the steady-state simulation. During the transient state, the iteration process is performed in almost every step to estimate . For the derivative of the input signal close to 0, the interval between the four points is small, thereby resulting in a few iterations since the value is being chosen far away from the real root. However, if the derivative value is large, this results in the initial value being too close to the real root which leads to an increase in the number of iterations. Fig. 8(a) shows the input signal without the estimated dc offset by the proposed algorithm and DFT. The proposed algorithm can remove the dc offset better than the DFT can.

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Fig. 9. Modied CIGRE HVDC benchmark system.

All of the aforementioned results clearly indicate that the proposed algorithm can accurately estimate the dc offset component and quickly extract the fundamental frequency signal. Also, the proposed algorithm improves the better speed and accuracy compared with the conventional full-cycle DFT. C. Real-Time Simulation In order to verify the implementation possibilities of the proposed algorithm in the real-time simulation environment, the proposed algorithm is implemented in a real-time digital simulator (RTDS). The RTDS is a special-purpose simulator designed to study electromagnetic transient phenomena in real time. The RTDS is comprised of specially designed hardware and software. The RTDS hardware is digital signal processor (DSP) and reduced instruction set computer (RISC) based, and utilizes an advanced parallel-processing technique in order to achieve the computation speeds required to maintain continuous real-time operation. RSCAD, which is based on RTDS-based software, includes accurate power system component models required to represent many of the complex elements which make up the physical power systems. The giga-processor card (GPC) is the processor card used to solve the equations representing the power system and control system components modeled within the RTDS. An RTDS rack typically contains between 2 and 6 GPC cards. Each GPC card includes two IBM Power PC 750GX processors running at 1 GHz [20]. The GPC card is divided into two parts: 1) for performing individual calculations where the network solution for the network analysis and the communication between the cards is being automatically assigned to 1A whereas the control processor for the control blocks and user-dened components (UDCs) are assigned to 1B when the simulation starts as shown in Fig. 10(g). The power system components conguring the power system network are assigned to the remaining GPC cards (2A, 2B ) in sequence. The UDC in RTDS is divided into two categories. One is the power system component UDC and the other is the control component UDC. The control component UDC is assigned to a part of the control processer (1B). Since the proposed algorithm is a control component UDC, the computational burden of the proposed algorithm is unaffected by the complexity of the power system component but is related to the number of control blocks and other control component UDCs. If the total calculation time of

control blocks and the control processor that includes the control component UDCs exceeds the simulation time step (e.g., 50 s), efcient simulation is being enabled through parallel processing by assigning an extra GPC card. However, real-time simulation is impossible when the calculation time of a control block or a control component UDC exceeds the simulation time step. In order to investigate the computational burden and execution time of the proposed algorithm, the modied CIGRE HVDC Benchmark system is chosen as the test system. In order to apply more computational burden on the CIGRE HVDC Benchmark system, which already has power electronics and many control blocks, a frequency-dependent transmission line is added. The test system is being shown in Fig. 9. Parameters of the CIGRE HVDC Benchmark system are represented in [21]. For verifying the algorithm in real-time simulation, a simulation test is composed by using a rectier voltage that receives an input from an external source congured in Hypersim and by adding a 30-Hz sawtooth signal (dc offset) that has an amplitude which is 10% of the original signal. In the proposed algorithm, using the transferred signal which is acquired through the RTDS GTAI (GT-analog input) card, the dc offset is estimated and removed where the corrected signal is being sent to the RSCAD external source to be utilized as the new rectier voltage source. At 0.0751 s, the three-phase-ground fault is applied to the inverter-side bus of the test system and the three-phase fault lasted for 0.1 s. The simulation time step of the RTDS is 50 s. Here, in order to compare the real-time graphs, MultiPlot (plot comparison module in RSCAD) has been utilized. Fig. 10(a) shows the signal which is the input voltage signal of the rectier. The input signal includes a dc offset with variable amplitude, but the dc offset is removed completely by using the proposed algorithm. Fig. 10(b) represents the number of iterations of the proposed algorithm in real-time simulation when the convergence limit is 10e-7. Fig. 10(c) represents the estimated dc offset component using the proposed algorithm and the deviation from the original dc offset component. In this simulation test, the estimated optimal value is 0.2067. Fig. 10(d)(f) show the rectier, dc link, and inverter voltage (phase A) of the test system. The black line represents the simulation result of the system when the entire system (include rectier) is composed and simulated in RTDS. The blue and red lines represent the simulation results of the test system where the dc offset in the external input

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Fig. 10. Estimated parameters and transient simulation in the real-time simulation test. (a) Input signal and calibrated signal. (b) Iteration number of the proposed algorithm. (c) Estimated dc offset component of the proposed algorithm and deviation from the original dc offset. (d) Rectier voltage in the test system. (e) DC link voltage in the test system. (f) Inverter voltage in the test system. (g) GPC processors usage. (h) Controls processors usage (27 iterations).

signal is removed and not removed, respectively. As shown in Fig. 10(d)(f), the original simulation result (black line) and the simulation result using the proposed algorithm (blue line) are found to be almost identical. However, the input signal, which

includes the dc offset component, has different real-time simulation results when compared to the original simulation results. The proposed algorithm can estimate and remove the dc offset exactly, and increase the accuracy in real-time simulation.

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Since the proposed algorithm is made for the control component UDCs, it is unaffected by the number of power components, such as power-electronics devices and frequency-dependent transmission lines. So the calculation time of the proposed algorithm is the most important factor to consider for application in real-time simulations. The maximum iteration number of the proposed algorithm in this case study is 27 iterations [Fig. 10(b)] when the convergence limit is 10e-7. In Fig. 10(h), the calculation time in real-time simulation of the proposed algorithm (blue box) is about 1.1 s when the maximum iteration is 27. Assuming that the simulation time step is 50 s, since the total calculation time including the UDCs and other control blocks is 6.77 s, this result is very acceptable and it shows that the proposed algorithm is suited and conforms to the requirements for a real-time environment. For the application of this algorithm in a real-time simulator other than RTDS, the engineer can change the convergence limit, depending on the performance of the simulator, to adjust the computation time accordingly for more efcient real-time simulation. V. CONCLUSION In this paper, a new dc offset removal algorithm for real-time simulation has been proposed. This algorithm is based on an iterative method for the optimal constant that is used to estimate parameters of the input signal. The mathematical derivation of the proposed algorithm is described. Using the stored optimal , the iteration number analysis according to the convergence limit and the autonomy of convergence algorithm can reduce the computational burden. Also, other estimated parameters, such as frequency, amplitude, and time can be used for other applications. A comprehensive result through steady and transient state simulation tests has shown that the proposed algorithm has fast estimation speed and good accuracy in comparison with conventional DFT. Real-time simulation results have shown that the proposed algorithm can be implemented under real-time constraints. Since the proposed algorithm uses simple trigonometric functions and an iteration method, the engineer can implement it easily. In further work, a study of the elimination of the spike caused by the sign change of the second derivative value and other application studies using this algorithm are required and under progress. REFERENCES [1] S. Oh, Evaluation of motor characteristics for hybrid electric vehicles using the hardware-in-the-loop concept, IEEE Trans. Veh. Technol., vol. 54, no. 3, pp. 817824, May 2005. [2] H. J. Slater, D. J. Atkinson, and A. G. Jack, Real-time emulation for power equipment development. II. The virtual machine, Proc. Inst. Elect. Eng., Electr. Power Appl., vol. 145, no. 3, pp. 153158, May 1998. [3] P. G. McLaren, R. Kuffel, R. Wierckx, J. Giesbrecht, and L. Arendt, A real time digital simulator for testing relats, IEEE Trans. Power Del., vol. 7, no. 1, pp. 207213, Jan. 1992. [4] S. Acevedo, L. R. Linares, J. R. Marti, and Y. Fujimoto, Efcient HVDC converter model for real time transients simulation, IEEE Trans. Power Syst., vol. 14, no. 1, pp. 166171, Feb. 1999. [5] J. Jeon, S. Kim, C. Cho, J. Ahn, and E. Kim, Development of simulator system for microgrids with renewable energy sources, J. Elect. Eng. Technol., vol. 1, no. 4, pp. 409413, Dec. 2006. [6] W. Ren, M. Steurer, and T. L. Baldwin, Improve the stability and accuracy of power hardware-in-the-loop simulation by selecting appropriate interface algorithms, presented at the Ind. Commercial Power Syst. Tech. Conf., Edmonton, AB, Canada, May 610, 2007.

[7] S. Lentijo, S. DArco, and A. Monti, Comparing the dynamic performances of power hardware-in-the-loop interfaces, IEEE Trans. Ind. Electron., vol. 57, no. 4, pp. 11951207, Apr. 2010. [8] G. Benmouyal, Removal of dc-offset in current waveforms using digital mimic ltering, IEEE Trans. Power Del., vol. 10, no. 2, pp. 621630, Apr. 1995. [9] J. C. Gu and S. L. Yu, Removal of dc offset in current and voltage signals using a novel fourier lter algorithm, IEEE Trans. Power Del., vol. 15, no. 1, pp. 7379, Jan. 2000. [10] E. Rosolowski, J. Izykowski, and B. Kasztenny, Adaptive measuring algorithm suppressing a decaying dc offset removal for digital protective relays, Elect. Power Syst. Res., vol. 60, pp. 99105, Sep. 2001. [11] T. S. Sidhu, X. Zhang, F. Albasri, and M. S. Sachdev, Discrete fourier-transform-based technique for removal of decaying dc offset from phasor estimates, Proc. Inst. Elect. Eng., Gen., Transm. Distrib., vol. 150, pp. 745752, Nov. 2003. [12] V. Balamourougan and T. S. Sidhu, A new ltering technique to eliminate decaying dc and harmonics for power system phasor estimation, presented at the IEEE Power India Conf., New Delhi, India, Apr. 2006. [13] T. S. Sidhu, X. Zhang, and V. Balamourougan, A new half-cycle phasor estimation algorithm, IEEE Trans. Power Del., vol. 20, no. 2, pt. 2, pp. 12991305, Apr. 2005. [14] F. Duan and R. Zivanoic, Estimation of DC offset parameters using global optimization technique, in Proc. Austral. Univ. Power Eng. Conf., 2008, pp. 14. [15] D. Lee, S. Kang, and S. Nam, New modied fourier algorithm to eliminate the effect of the DC offset on phasor estimation using DFT, in Proc. IEEE Power Eng. Soc. Transm. Distrib. Conf., 2008, pp. 16. [16] S. Kang, D. Lee, S. Nam, P. A. Crossley, and Y. Kang, Fourier transform-based modied phasor estimation method immune to the effect of the DC offsets, IEEE Trans. Power Del., vol. 24, no. 3, pp. 11041111, Jul. 2009. [17] Y. Cho, C. Lee, and G. Jang, An innovative decaying DC component estimation algorithm for digital relaying, IEEE Trans. Power Del., vol. 24, no. 1, pp. 7378, Jan. 2009. [18] H. W. Dommel, Digital computer solution of electromagnetic transients in single- and multiphase networks, IEEE Trans. Power App. Syst., vol. PAS-88, no. 4, pp. 388399, Apr. 1969. [19] W. Ren, Accuracy evaluation of power hardware-in-the-loop (phil) simulation, Ph.D. dissertation, Dept. Elect. Comput. Eng., Univ. Florida, Gainesville, FL, 2007. [20] Real Time Digital Simulator Power System Users Manual, RTDS Technol., Jan. 2009. [21] M. Szechtman, T. Wess, and C. V. Thio, A benchmark model for HVDC system studies CIGRE Working Group, 14.02 Electra no. 135, pp. 5473, Apr. 1991.

Gilsung Byeon (S06) received the B.S. degree in electrical engineering from Korea University, Seoul, Korea, in 2006, where he is currently pursuing the Ph.D. degree in electrical engineering. His research interests are power system modeling as well as control and simulation algorithm analysis.

Seaseung Oh (S02M08) received the B.E., M.E., and Ph.D. degrees from Korea University, Seoul, Korea. He was a Postdoctoral Researcher with Seoul National University, Seoul. Currently, he is a Research Professor in BK21 Division, Department of Electrical Engineering, Myongji University, Myongji. His research interests include computer applications in power system analysis, operation, controls and visualization.

Gilsoo Jang (S95M97SM06) received the B.S. and M.S. degrees from Korea University, Seoul, Korea, and the Ph.D. degree from Iowa State University, Ames, in 1997. He was a Visiting Scientist in the Electrical and Computer Engineering Department, Iowa State University, for one year and a Researcher with the Korea Electric Power Research Institute, Daejeon, Korea, for two years. Currently, he is a Professor with the School of Electrical Engineering, Korea University. His research interests include power quality and power system control.