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Phase Locked Loop (PLL)

Aniruddha Chandra
ECE Department, NIT Durgapur, WB, India. <aniruddha.chandra@nitdgp.ac.in>

Jan 24, 2009

ECE Department, NIT Durgapur

Winter School on VLSI Systems Design

Outline

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Synchronization PLL Basics Analog PLL Digital PLL TDTL FPGA Implementation
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Synchronization ???
Concept
Synchronization Urban traffic

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Attribute
Frequency/ phase Vehicle speed

In heavy traffic we are forced to match our speed to that of the car in front of us and should also try to avoid sudden braking so as not to frighten the driver behind us.
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Synchronization ???
Concept
Synchronization Orchestra

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Attribute
Frequency/ phase Scale of note

In a symphony orchestra, the reference is the conductor, and all musicians attempt to reproduce the beat as set by the conductors baton.

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Synchronization We take it for granted

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Synchronization
What happens without it?

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Exchange

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Synchronization
What happens without it?

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Exchange

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Synchronization
What happens without it?

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Synchronization Hierarchy
Carrier Synchronization
Coherent demodulation Non-coherent demodulation Multi Carrier systems

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phase/ frequency frequency sub-carrier

Symbol Synchronization
Integrator, Decision device

Frame Synchronization
Multiple access (TDMA), FEC (Block coding)

Network Synchronization
Transmitter synchronization Satellite, GPS, CDMA
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Phase Locked Loop (PLL) Building block for all synchronization system

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PLL - Basics
What is PLL?

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PLL is a circuit synchronizing an output signal (generated by an oscillator) with a reference or input signal in the frequency as well as in phase.
This is the action of a PLL Oscillator output Reference input

These look like pointless operations! Track average phase (& frequency)/ period input
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PLL - Basics
PLL types
Phase and Frequency locked coherent demodulation
Oscillator output

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Reference input

Frequency locked, constant Phase difference non-coherent demodulation


Oscillator output Reference input

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PLL - Applications
Clock phase adjustment in P Time-to-Digital converters (TDC) Frequency synthesis Motor speed control Frequency modulation/ demodulation Jitter reduction, Skew suppression, Clock recovery
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Turning the pages of History


1922-27: Oscillator synchronization - Appleton, VanderPol 1932: Publication on the PLL concept - H. de Bellescise 1932: British scientists develop the homodyne/ synchrodyne detection (AFC) 1943: PLL applied in TV - vertical and horizontal scan 1965: Analog PLL devices appeared 1970: Digital PLL introduced - IC 565, CD 4046 1980-90: All-digital PLL (ADPLL) was invented. Software controlled PLL (SPLL) became relity.
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Analog Phase Locked Loop (APLL)

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Analog PLL (APLL)

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In synchronized or locked state, the phase error between the oscillators output and the reference signal is either zero or an arbitrary constant. When phase error builds up, the oscillator is tuned by a control mechanism to reduce the phase error.

The components of a PLL: VCO, PD, and LF.


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APLL - Analysis

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The reference (or input signal) The output signal of the VCO

v1 (t ) = V1 cos(1t )

v2 (t ) = V2 cos(2 t )

with 2 (t ) = 0 + K 0 v f (t ), where o is the centre frequency of the VCO, Ko is the VCO gain, and vf (t) is the output signal of loop filter
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APLL - Analysis

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The phase error at PD e (t ) = (1 2 ) t PD output signal vd (t ) = K d e (t ), where Kd is the PD gain


vd (t) consists of a dc component and a superimposed ac

component
vf (t) is delayed version of vd (t) with ac removed
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APLL Components
Phase Detector (PD)

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PD compares the phases of the input and output signals and generate an error signal proportional to the phase deviation.

A mixer (analog multiplier/ balanced modulator) generates the sums and differences of the frequencies at its input terminals.
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APLL Components
Phase Detector (PD)
Superior noise performance Operates on the entire amplitude of the input and VCO signals rather than quantizing them to 1 bit Best suited for PLL applications in the microwave frequency range as well as in low noise frequency synthesizers

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Loop gain depends on signal amplitude Non-linear response due to non-idealities in the circuit
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APLL Components
Voltage Controlled Oscillator (VCO)
VCO produces an oscillation whose frequency can be controlled through some external voltage.

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VCO types
Ring oscillator - Odd number of inverters connected in a feedback loop. Relaxation oscillator - Generates square wave using Schmitt trigger.
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APLL Components
VCO types (Contd.)
Resonant oscillator - Resonant circuit in the positive feedback path of a voltage to current amplifier. Crystal Oscillator YIG Oscillator - YIG (Yttrium, Iron and Garnet) spheres, due to the ferrite properties, resonate at wave frequencies when immersed in a magnetic field.
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A simple resonant circuit VCO, where the frequency is controlled by adjusting the reverse bias of the varactor diode C1
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APLL Components
Loop Filter

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PLLs are mostly second order and as the VCO is modeled as an integrator, loop filters are of the lead-lag type. More specifically, the loop filter contains an integrator which is able to track a phase ramp, and this corresponds to tracking a step in frequency.

Passive lead-lag filter


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Active lead-lag filter


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APLL Performance Metrics


Hold Range

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The hold range, is defined as the frequency range over which the PLL is able to statically maintain phase tracking

Lock Range
The lock range, is defined as the frequency range within which the PLL locks within one single-beat note between the reference frequency and output frequency.

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Digital Phase Locked Loop (DPLL)

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Why DPLL?
Superiority in performance

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APLLs cant operate at very low frequencies. The analog LPF struggles while extracting the lower frequency component, as it needs larger time for better frequency resolution.

Speed
Self-acquisition of APLLs is often slow, while DPLLs can achieve locking within few cycles.

Reliability
VCO is sensitive to temperature and power supply variations. Analog multipliers are sensitive to DC drifts.

Reduction in size and cost


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DPLL Development

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Sinusoidal Digital PLL (1970) Digital tan-lock loop (1982) Time-delay digital tan-lock loop

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DPLL Schematic

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Digital PD

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DPLL Components
Phase Error Detector (PED)
Classification based on PED type 1. Flip-flop DPLL 2. The Nyquist-rate DPLL 3. The lead-lag DPLL or, binary-quantized DPLL 4. Exclusive-OR DPLL 5. Zero-crossing DPLL

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Flip-flop DPLL

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Comparator - convert sinusoidal input into a square wave Q output - duration when Q = 1 is proportional to phase error
Phase detector

Counter clock - frequency 2M fo fo = DCO center frequency 2M = number of quantization levels of the phase error over period of 2
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Flip-flop DPLL

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Counter - starts counting on the positive-going edge of the flip-flop waveform. The content of the counter, No, which is proportional to the phase error, is applied to digital filter.
Phase detector

The output of the digital filter K controls the period of the DCO DCO - programmable divideby-K counter

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DPLL Components
Digital Controlled Oscillator (DCO)

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Digital Controlled Oscillator (DCO)


DCO Components Programmable counter Binary subtractor Zero detector
Binary Subtrator

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With each clock pulse counter decrements by one. When it reaches zero, the counter generates a pulse. This pulse is used to load the counter with M K where K is input.
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Digital Controlled Oscillator (DCO)


Binary Subtrator

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DCO free-running frequency fo = fc /M where fc is the frequency of the counter clock. The period between the (k1)th and the kth pulse T(k) = (M K) Tc where Tc = 1/ fc
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Sinusoidal DPLL Digital tan-lock loop (DTL) Time-delay digital tan-lock loop (TDTL)

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Digital tan-lock loop (DTL)


Why DTL?
Sinusoidal DPLL - sensitive to the variations in the input signal power and rather limited lock range

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Components
90o phase shifter, 2 samplers, PED, digital loop filter, DCO
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Digital tan-lock loop (DTL)


Sampler I and II takes in-phase (I) and quadrature (Q) samples simultaneously.

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Phase error at sampling instant is extracted by the tan1 function. This phase error, modified by the digital filter, controls the period of DCO.
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Time-delay DTL (TDTL)


Why TDTL?

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A digital Hilbert transformer introduces approximations and imposes limitations on the range of input frequencies, especially when implemented on a microprocessor.

A constant time-delay may be used to produce a phaseshifted version of the incoming signal to reduce complexity.
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Improved TDTL - I
Variable delay TDTL (VD-TDTL)

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The conflicting requirements of fast acquisition and wide locking range necessitate the inclusion of more than one time delay.
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Improved TDTL - II
Adaptive gain TDTL (AG-TDTL)

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If a sudden change in input frequency drives the system to go outside the locking range, the system senses this error through the FSM and updates the gain of the digital filter to bring the operating point within the locking region
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Improved TDTL - III


Adaptive gain variable delay (AG-VD) TDTL

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Combining the best of two - faster acquisition, wider locking range and more resilience to frequency drifts
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TDTL FPGA Implementation

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Platform
Xtreme DSP development board
Virtex-II XC2V3000 chip with three million gates Virtex-II XC2V80 for clocking and I/O management Spartan-II interface FPGA for communicating with PC using the PCI bus/ USB. Xilinx System Generator serves as the software development platform. It consists of a Simulink library called the Xilinx Blockset, and software to translate a Simulink model into a hardware realization of the model.
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Xtreme DSP Development Kit-II powered by a Virtex-II FPGA chip from Xilinx.
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TDTL FPGA Implementation

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CORDIC Arctangent Block

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The COordinate Rotational DIgital Computer (CORDIC) algorithm is an iterative method of calculating trigonometric and functions.

The CORDIC algorithm is used to implement the 4-quad tan1(x / y) function of the phase detector, converging to angles between within eleven system clock cycles.
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DCO Block
The disadvantage of using divide-by-k counter is poor frequency resolution.

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The DCO is implemented using a Direct Digital Synthesis (DDS) block


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References

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Read more about this


S. R. Al-Araji, Z. M. Hussain, and M. A. Al-Qutayri, Digital Phase Lock Loops: Architectures and Applications, Springer, Dordrecht, Netherlands, 2006. W. F. Egan, Phase-Lock Basics, Wiley InterScience, John Wiley & Sons, New York, 1998. R. E. Best, Phase-Locked Loops: Design, Simulation, and Applications, McGraw-Hill, New York, 2003, 5th edition.

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Read even more about this

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M. Kihara, S. Ono, and P. Eskelinenesign, Digital Clocks for Synchronization and Communications, Artech House, Boston, London, 2003. H. M. Berlin, Design of Phase-Locked Loop Circuits with Experiments, SAMS Publishers/ Longman Higher Education, 1978. A. Blanchard, Phase-Locked Loops: Application to Coherent Receiver Design, Krieger Publishers, 1992. F. M. Gardner, Phaselock Techniques, John Wiley & Sons, New York, 2005, 3rd edition.
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Thank You!
aniruddha.chandra@nitdgp.ac.in

Questions???
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