FLASH CONVERTORS Problem Question : Flash Convertors, tracking methods should be three or four and find out whether

they come as I.Cs and present on that. INTRODUCTION A Flash ADC (also known as a Direct conversion ADC OR parallel A/D converter) is a type of analog-to-digital converter that uses a linear voltage ladder with a comparator at each "rung" of the ladder to compare the input voltage to successive reference voltages. Often these reference ladders are constructed of many resistors; however modern implementations show that capacitive voltage division is also possible. The output of these comparators is generally fed into a digital encoder which converts the inputs into a binary value (the collected outputs from the comparators can be thought of as a unary Value). Architectural details Flash ADCs are made by cascading high-speed comparators. Figure 1 shows a typical flash ADC block diagram. For an N-bit converter, the circuit employs 2N-1 comparators. A resistive-divider with 2N resistors provides the reference voltage. The reference voltage for each comparator is one least significant bit (LSB) greater than the reference voltage for the comparator immediately below it. Each comparator produces a 1 when its analog input voltage is higher than the reference voltage applied to it. Otherwise, the comparator output is 0. Thus, if the analog input is between VX4 and VX5, comparators X1 through X4 produce 1s and the remaining comparators produce 0s. The point where the code changes from ones to zeros is the point at which the input signal becomes smaller than the respective comparator reference-voltage levels. This architecture is known as thermometer code encoding. This name is used because the design is similar to a mercury thermometer, in which the mercury column always rises to the appropriate temperature and no mercury is present above that temperature. The thermometer code is then decoded to the appropriate digital output code. Shown in Fig.1 is an N bit Flash ADC, which uses -1 comparators (Generally, -1 comparators are required for conversion to an n-bit binary code). A four-bit converter requires 15 comparators. A comparator is not needed for the all-zeros condition. The large number of comparators is the Flash converters main disadvantage.

Their main advantage is in the fast conversion time (nanoseconds).

Fig.1 Sparkle Codes Normally, the comparator outputs will be a thermometer code, such as 00011111. Errors can cause an output like 00010111, meaning that there is a spurious zero in the result. This out-of-sequence 0 is called a sparkle, which is caused by imperfect input settling or comparator timing mismatch. The magnitude of the error can be quite large. Modern converters like the MAX109/MAX104 employ an input track-and-hold in front of the ADC along with an encoding technique that suppresses sparkle codes. Metastability When the digital output from a comparator is ambiguous (neither a 1 nor a 0), the output is defined as metastable. Metastability can be reduced by allowing more time for regeneration. Gray-code encoding, which allows only 1 bit in the output to change at a time, can greatly improve metastability. . Thus, the comparator outputs are first converted to gray-code encoding and then later decoded to binary, if desired. Another problem occurs when a metastable output drives two distinct circuits. It is possible for one circuit to declare the input a 1, while the other circuit thinks that it is a 0. This can create major errors. To avoid this conflict, only one circuit should sense a potentially mestatable output.

Input Signal-Frequency Dependence When the input signal changes before all the comparators have completed their tasks, the ADC's performance is adversely impacted. The most serious impact is a drop-off in signalto-noise ratio (SNR) plus distortion (SINAD) as the frequency of the analog input frequency increases. Measuring spurious-free dynamic range (SFDR) is another good way to observe converter performance. The "effective bits" achieved by the ADC is a function of input frequency; it can be improved by adding a track-and-hold (T/H) circuit in front of the ADC. The T/H circuit allows dramatic improvement, especially when input frequencies approach the Nyquist frequency, as shown in Figure 2 (taken from the MAX104 data sheet). Parts without T/H show a significant drop-off in SFDR.

Fig2

Fig.VII.(1).2 Operation The reference voltage is set by a resistor voltage divider. The output of each comparator is connected to an input of the priority encoder. It is sampled by a pulse on the Enable Input and a three-bit binary code representing the value of the analogue input appears on the encoders output. The binary code is determined by the highest order input having a high level. The sampling rate determines the accuracy with which the sequence of the digital codes represents the analog input of the ADC. The more samples taken in a given period of time, the more accurately the analogue signal is represented in digital form. Fig.VII(1).2 shows sampling of values on an analog waveform for conversion to digital form. STAIR STEP-RAMP ANALOGUE-TO-DIGITAL CONVERTERS Such converter is shown is Fig.VII(1).3.

Assume that the counter begins in the reset state (all 0s) and the output of the Digital-toAnalogue Converter (DAC) is 0. Assume that an analog voltage is applied to the input. When it exceeds the reference voltage (the output of DAC), the comparator switches to a high level output state and enables the AND gate. The clock pulses begin advancing the counter through its binary states, producing a stairstep reference voltage from the DAC. The counter continues to advance from one binary state to the next producing higher steps in the reference voltage. When the stair-step reference voltage reaches the analogue input voltage, the comparator output goes to its low level and disables the AND gate, thus cutting off the clock pulses to stop the counter. The binary state of the counter at this point equals the number of steps in the reference voltage, required to make the reference equal or greater than the analog input. This binary number represents the value of the analog input. The control logic loads the binary counts into the latches and resets the counter, thus beginning another count sequence to sample the input value. The operation of a four-bit conversion is illustrated in Fig.VII(1).4.
Fig.VII(1).3

Fig.VII(1).4 This type of ADCs is much slower than the Flash type. In the worst case of maximum input, the counter must sequence through its maximum number of states before a conversion occurs. For an 8-bit conversion there are 256 states. The conversion time varies, depending on the analogue voltage. TRACKING ANALOGUE-TO-DIGITAL CONVERTERS The tracking method uses an UP/DOWN counter and is faster than the stair-step ramp method, because the counter is not reset after each sample, but tends to follow the analogue signal.

The circuit diagram and the sample and conversion methods are shown in Fig.VII(1).5 and Fig.VII(1).6.

Fig.VII(1).5

Fig.VII(1).6 As long as the DAC output reference voltage is less than the analog input, the comparator output level is high, putting the counter in the UP mode, which causes it to produce an up sequence of binary counts. This causes an increasing stair-step reference voltage out of the DAC, which continues until the stair-step reaches the value of the input voltage.

When the reference voltage equals the analogue input, the comparators output switches to its low level and puts the counter in Down mode, causing it to back up one count. If the analogue input is decreasing the counter will continue to back down in its sequence and effectively track the input. If the input is increasing, the counter will back down one count after the comparison occurs and then will begin counting up again. When the input is constant, the counter backs down one count when a comparison occurs. The reference output is now less than the analogue input. The comparator goes to its high level, causing the counter to count up. As soon as the counter increases one state, the reference voltage becomes greater than the input, switching the comparator to its low output state. This causes the counter to back down one count. This back and forth action continues as long as the analogue input is constant, causing an oscillation between two binary states in the ADC output.