CONTENTS 1. Introduction 2. Basic Concepts 3. Instructions 4. Symbols, literals, expressions, Constants and data areas, location counter 5.

Integer operations 6. Decimal operations 7. Data transfer and Logical operations 8. Bit manipulations 9. Branching 10. Assembler Directives 11. JCL aspects 12. Subroutines, linkage 24 bit mode 13. Mixed Mode Programming using COBOL and Assembler.

INTRODUCTION
What is Assembly Language Lowest-level of programming on a system Symbolic forms of representing machine language instructions Usually represents a single machine instruction Machine dependent

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Advantages over high-level language Very efficient and tight code can be developed Disadvantages Applications development time is more Applications are machine dependent Relatively more difficult to learn and understand than a high level Language Advantages over machine language Use of mnemonic operation codes helps remembering the instructions Symbols can be used to represent variables and constants Macros can be used to generate repeated codes Conditional assembly enables tailoring the code generated

BASIC CONCEPTS
IBM-370 MACHINE ARCHITECTURE

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Main storage Addressed by 24 bits or 31 bits One single address space contains code and data Byte is the least addressable unit Instruction categories Fixed point Arithmetic, Decimal Arithmetic, Floating point Arithmetic, Logical Operations, Branching, Status Switching, Input Output Programmer accessible Hardware Registers are Program Status Word (PSW) 64 bits wide General Purpose Registers (GPRs) Floating Point Registers (FPRs) Control Registers (CRs) 0-15 each 32 bits wide Access Registers (AR'S) 0-15 each 32 bits wide PSW 64 bits in length Contains the Condition Code (two bits) Address of the next instruction to be executed. PSW Key field GPR'S numbered 0-15 and 32 bits wide Used as accumulators in Fixed point arithmetic Used as base and index registers in computing the effective address Two consecutive registers can be used to hold 64bit operands addressed by even register AR'S Numbered 0-15 each 32 bits wide Used to point to address / data space FPR Used for floating point operations Numbered 0,2,4,6 each 64 bits wide 64 bits in length Can contain short or long operand Two adjacent registers can be used as 128 bit register for extended precision CR'S Control registers each of 32 bits are available Used by the IBM control program Instructions to access / modify them are privileged and can be issued only by the OS. INPUT/OUTPUT Data processing and I/O processing are concurrent Consists of Channel subsystem, Control Unit and I/O unit

ASSEMBLY STATEMENT FORMAT NAME FIELD 1 OPERATION FIELD 10 OPERAND FIELD 16 REMARK S SEQUENC 72 E *

Fixed Format. Can be changed only through ICTL Assembler Directive Fields in a statement are separated by one or more blanks Name / label field if present must start in column 1 and maximum 8 characters in length To continue a statement to next line, type a non blank character in column 72 and continue the next line from column 16 Comment lines start with character ('*') on column 1 PSW Format IE Prog 0R0 0 0TOX Key 1MWPA SC C Mask 0 0 0 0 0 0 0 0 0 5 8 12 16 18 20 24 31 A Instruction Address 32 63 PER Mask (R): Bit 1 controls whether the CPU is enabled for interruptions associated with program-event recording (PER). When the bit is zero, no PER event can cause an interruption. When the bit is one, interruptions are permitted, subject to the PER-event-mask bits in control register 9. DAT Mode (T): Bit 5 controls whether dynamic address translation takes place. When the bit is zero, DAT is off, and logical and instruction addresses are treated as real addresses. When the bit is one, DAT is on, and the dynamic-address-translation mechanism is invoked. I/O Mask (IO): Bit 6 controls whether the CPU is enabled for I/O interruptions. When the bit is zero, an I/O interruption cannot occur. When the bit is one, I/O interruptions are subject to the I/O-interruption subclass-mask bits in control register 6. External Mask (EX): Bit 7 controls whether the CPU is enabled for interruption by conditions included in the external class. When the bit is zero, an external interruption cannot occur. When the bit is one, an external interruption is subject to the corresponding external subclass-mask bits in control register 0; PSW Key: Bits 8-11 form the access key for storage references by the CPU. If the reference is subject to key-controlled protection, the PSW key is matched with a storage key when information is stored or when information is fetched from a location that is protected against fetching. Machine-Check Mask (M): Bit 13 controls whether the CPU is enabled for interruption by machine-check conditions. When the bit is zero, a machine-check interruption cannot occur. Wait State (W): When bit 14 is one, the CPU is waiting; that is, no instructions are processed by the CPU, but interruptions may take place. When bit 14 is zero, instruction fetching and execution occur in the normal manner. The wait indicator is on when the bit is one.

Problem State (P): When bit 15 is one, the CPU is in the problem state. When bit 15 is zero, the CPU is in the supervisor state. In the supervisor state, all instructions are valid. In the problem state, only those instructions that cannot affect system integrity are permitted; such instructions are called unprivileged instructions. The instructions that are never valid in the problem state are called privileged instructions. When a CPU in the problem state attempts to execute a privileged instruction, a privileged-operation exception occurs. Address-Space Control (AS): Bits 16 and 17, in conjunction with PSW bit 5, control the translation mode. Condition Code (CC): Bits 18 and 19 are the two bits of the condition code. The condition code is set to 0, 1, 2, or 3, depending on the result obtained in executing certain instructions. Program Mask: Bits 20-23 are the four program-mask bits. Each bit is associated with a program exception, as follows: Program- Mask Bit Program Exception 20 Fixed-point overflow 21 Decimal overflow 22 Exponent underflow 23 Significance When the mask bit is one, the exception results in an interruption. When the mask bit is zero, no interruption occurs. Addressing Mode (A): When the bit is zero, 24-bit addressing is specified (AMODE 24). When the bit is one, 31-bit addressing is specified (AMODE 31). Instruction Address: Bits 33-63 form the instruction address. This address designates the location of the leftmost byte of the next instruction to be executed. Bit positions 0, 2-4, and 24-31 are unassigned and must contain zeros. A specification exception is recognised when these bit positions do not contain zeros. When bit 32 of the PSW specifies the 24-bit addressing mode, bits 33-39 of the instruction address must be zeros; otherwise, a specification exception is recognised. A specification exception is also recognised when bit position 12 does not contain a one

INSTRUCTIONS
TYPES OF INSTRUCTIONS machine instructions Assembler instructions (directives) Macro instructions Example : PRINT NOGEN TEST1 CSECT STM BALR USING ST LA MVC PUTMSG WTO L LM SR BR DATA1 DS DATA2 DS SAVE DS END

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14,12,12(13) 12,0 *,12 13,SAVE+4 13,SAVE DATA1,DATA2 'MESSAGE' 13,SAVE+4 14,12,12(13) 15,15 14 CL100 CL100 18F

Assembler Directive Machine instruction Machine instruction Assembler Directive Machine instruction Machine instruction Machine Instruction Macro instruction Machine instruction Machine instruction Machine instruction Machine Instruction Data Definition Data Definition Data Definition Assembler Directive

INSTRUCTIONS FUNDAMENTALS Two, four, or six bytes in length Should begin on a half-word boundary First byte normally contains the operation code. In some instructions it is two bytes. Operation code specifies the function of the instruction Operand designation follows the operation code Operands Entities that are involved in operations defined by operation code Operands can be either implicit or explicit Four types of operands Register operand Example immediate operand Example Storage operand Example Implied operand, Example

AR 3,2 MVI DATA,X'F1' L 3,FIELD1 LM 14,12,SAVE

REGISTER OPERAND Identified by R field in the instruction Specifies either GPR or FPR Operand access is faster Example AR 1,2

IMMEDIATE OPERAND Contained with in the instruction itself Eight bit value Self defining term or an absolute symbol can be used Example : MVI DATA,B'10000000' STORAGE OPERAND Resides in memory Address is not specified explicitly Base and 12 bit offset with (in some instructions) index register is used Program can be relocated If Register 0 is used as a base or index register its contents are ignored 12 bit displacement BALR instruction is used to load base register If symbols are used assembler resolves it to base displacement form Effective address = (base register) + (Index Register) + 12 bit displacement (note that some instruction formats do not support index register) base register should be made to contain the base address at run time Size of storage operand is implied by the instruction for some instructions For some instructions Length field(s) is/are embedded in the instruction Storage operands can be specified in implicit form as a re-locatable expression Example L 3,DATA L 3,DATA+4 Storage operands can be specified in the Explicit form Example L 3,4(1,2) Explicit addresses are of the form D2(X2,B2) or D2(B2) or D2(L2,B2) or D1(L1,B1) or D1(B1) Absolute addresses are also assembled in base displacement form. However the value in the base register will not change on relocation Implicit addresses are those where a single re-locatable or absolute expression is specified Example L 4,DATA L 3,DATA+4 LA 2,1000 . . DATA DS F IMPLIED OPERAND The instruction implies the operand Example

TRT D1(L,B1),D2(B2) Registers 0,1 participate in this operation

INSTRUCTIONS CLASSIFICATION FIRST HALF WORD RR FORMAT OP CODE 0 8 R1 12 R2 15 SECOND HALF WORD THIRD HALF WORD

RRE FORMAT OP CODE 0 RX FORMAT OP CODE R1 0 8 12 16 24 R1 28 R2 31

X2 16

B2 20

D2 31

RS FORMAT OP CODE 0 8 R1 R3 B2 12 16 20 D2 31

SI FORMAT OP CODE 0 8 S FORMAT OP CODE 0 SS FORMATS OP CODE 0 8 OP CODE 0 8 L1 12 L 16 L2/I3 16 B1 20 B1 20 D1 32 D1 32 36 B2 36 B2 D2 47 D2 47 16 B2 20 D2 31 I2 16 B1 20 DI 31

EXAMPLES : RR type instruction AR 2,3 (reg 2) <== (reg 2) + (reg 3) RS type instruction BXLE 1,2,D2(B2) (reg 1) <== (reg 1) + (reg 2) If reg1>reg3 then branch RX type instruction L 1,D2(X2,B2) (reg 1) < == memory referenced by (D2 +X2 +B2) S type instruction LPSW D2(B2) SI type instruction

NI D1(B1),I2 SS type instruction MVC D1(L,B1),D2(B2) PACK D1(L1,B1),D2(L2,B2) Note that (Rn) denotes the contents of GPR n. It is known as Register Notation and is commonly used to supply values for a Macro operand.