Application Note

MSAN-198

Performing Clock Recovery for Circuit Emulation when using the MT90880
Contents
1.0 Circuit Emulation Services over a Packet Network 1.1 Leased Line Provision 1.2 Regenerating the Clock 2.0 Clock Recovery Techniques 2.1 Adaptive Clock Recovery 2.2 Differential Recovery 3.0 Implementation of Clock Recovery 3.1 Adaptive Clock Recovery 3.2 Differential Clock Recovery 3.3 Using the RTCP protocol 4.0Proof of Concept Evaluation Board using the MT90880
AN5789 Issue 1 August 2002

1.0 Circuit Emulation Services over a Packet Network

The MT90880 can be used to transport TDM links across the packet domain and transparently reconstruct the links at the far end. This is similar to the circuit emulation services defined by the ATM Forum, with the MT90880 providing the core of the circuit emulation inter-working function.

1.1

Leased Line Provision

Circuit emulation is typically used to support the provision of leased line services to customers using legacy TDM equipment. For example, Figure 1 below shows a leased line TDM service being carried across a packet network. The advantages are that a carrier can upgrade to a packet switched network, while still maintaining their existing TDM business.

Related Documents
"Unstructured Circuit Emulation Using the MT90880", Zarlink Semiconductor Application Note, MSAN-199, August 2002 "MT90880 Data Sheet", Zarlink Semiconductor, DS5568, Issue 1.3, June 2002

Customer Premises

Carrier Network TDM Leased Line Service

Customer Premises

Customer data

TDM

TDM to packet

Packet Network

queue

TDM fregen

fservice Provider Edge Interworking Function

~
fregen Provider Edge Interworking Function

Extract Clock

Figure 1 - Leased Line services over a Circuit Emulated link

Customer data

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1.2 Regenerating the Clock

Application Note

One of the main issues with this type of application is that the clock used to drive the TDM link is not linked into the central office clock, and hence may be any value within the tolerance defined for that service. The reverse link is also independently timed, and may be operating at a slightly different frequency. In the plesiochronous digital hierarchy the difference in clock frequencies between TDM links is compensated for using bit stuffing techniques, allowing the clock to be accurately regenerated at the remote end of the carrier network. With a packet network, that connection between the ingress and egress frequency is broken, since packets are discontinuous in time. From Figure 1, the TDM service frequency fservice at the customer premises must be exactly reproduced at the egress of the packet network (fregen). The consequence of a long-term mismatch in frequency is that the queue at the egress of the packet network will either fill up or empty, depending on whether the regenerated clock is slower or faster than the original. This will cause loss of data and degradation of the service. This application note describes a means to achieve clock recovery when performing circuit emulation with an MT90880. A related application note (reference1) describes how to use the MT90880 to perform circuit emulation using unstructured data transfer (UDT).

2.0
2.1

Clock Recovery Techniques

Adaptive Clock Recovery

For operation with a packet network, the clock rate can be inferred by averaging the arrival rate of the packets over a period. This averaging period has to be sufficiently long to remove jitter effects, caused by variation in the transit delay of packets across the network. The technique is known as adaptive clock recovery. It is not necessary to use the actual data packet arrival rate, since it could be equally well performed on out of band packets transmitted at a rate that is related to the same TDM service clock. This means that the first provider edge could transmit clock packets to the remote end at a regular rate, related to the TDM service frequency, fservice (see Figure 2 below). The remote provider edge averages the arrival rate of these packets, and compares it to the rate of a local oscillator. The frequency of the local oscillator, fregen is adjusted to match the TDM service frequency. The reverse link is independently timed, and has its own, separate adaptive timing control.

Customer Premises

Carrier Network TDM Leased Line Service

Customer Premises

Customer data

TDM

TDM to packet Clock Packet

Packet Network

queue

TDM fregen
Extract Clock

fservice Provider Edge Interworking Function

Compare

~
fregen

Provider Edge Interworking Function

Figure 2 - Adaptive Clock Recovery

Customer data
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MSAN-198

The disadvantage of this type of scheme is that, depending on the characteristics of the packet network, it may prove difficult to regenerate a clock that stays within the wander requirements of the plesiochronous digital hierarchy. The reason for this is that any variation in delay between clock packets will feed through as a variation in the frequency of the recovered clock, fregen. High frequency jitter can be filtered out, but any low frequency variation or wander is more difficult to remove without a very long time constant. This will in turn affect the ability of the system to lock to the original clock within an acceptable time. The extent of the wander is dependent on the characteristics of the carrier's packet network. If the loading on the network is kept small, such as might be expected if it was dedicated to this type of service, then the wander on the clock frequency may never exceed the specified limits. The performance can be further improved by giving the clock packets high priority, such that their delay through the network (and hence the delay variation) is reduced. This may not be an issue if the system is as drawn in Figure 2, with the regenerated circuit going direct to a customer site. However, if the regenerated circuit has to connect into the existing plesiochronous hierarchy, then excessive wander will cause interruptions in service. Therefore the PSTN operator may require that an alternative technique capable of meeting the wander requirements be used.

2.2

Differential Recovery

A second means of regenerating the service clock is to relate it to a known clock that is available at each end of the packet network (e.g. a primary reference clock, if one is available). For example, the difference between the TDM service frequency and the primary reference frequency could be measured and transmitted across the network. The service frequency can then be easily regenerated by adding back in the reference frequency (see Figure 3).

Customer Premises
Customer data

Carrier Network
TDM Leased Line Service
TDM Packet Network
queue

Customer Premises
Customer data

TDM to packet Difference

TDM fregen
Extract Clock

fservice Provider Edge Interworking Function

add

~
fregen

Provider Edge Interworking Function

~
Primary Reference Source, freference

Figure 3 - Primary Reference Clocking The advantage of this technique is that it is unaffected by the variation in transit time between clock packets. Therefore it is possible to meet the required jitter and wander specification for the regenerated clock regardless of the loading or congestion on the packet network. Differential techniques (such as the SRTS scheme defined in the ATM AAL1 specification) are acceptable for TDM links that need to be connected back into the PSTN.

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Application Note

The main disadvantage is that the technique requires a common clock at each end of the packet network. Where the packet network runs between central offices, it may be that there is a primary reference source available in each central office, traceable back to the same high quality reference. However, often one edge of the packet network is on a remote site, without an accessible reference clock. In these situations the adaptive clock recovery technique must be used. One possible alternative is to use a GPS (global positioning by satellite) unit at each end of the network. These units take reference time from a satellite, avoiding the need to distribute the clock by conventional means. GPS units are small and relatively inexpensive, but still capable of generating a reference clock with a highly stable and accurate frequency.

3.0
3.1

Implementation of Clock Recovery

Adaptive Clock Recovery

At the first provider edge, where the TDM service is originally turned into packets, a means of generating clock packets at regular intervals needs to be provided. This could be as simple as dividing down the TDM service clock frequency by a fixed amount, and using the result to generate a regular interrupt of the host processor. On interrupt, the host processor then needs to send a clock packet across the network to the packet egress node (Figure 4).

Host CPU
Clock packets

TDM in

LIU

Clock Data

MT90880

Figure 4 - Source Provider Edge Node On receiving the packets, the receiver host processes averages the arrival rate and uses the result to control a DCO. The output of the DCO is used to clock the TDM data out of the MT90880, and onto the TDM circuit. For adaptive control, a feedback loop is included to compare the recovered clock against the incoming packet arrival rate. The Host CPU implements the filtering algorithm required to reduce jitter and wander to acceptable levels.
feedback

Host CPU

DCO

~
Clock

Clock packets

MT90880

LIU

TDM out

Data

Figure 5 - Receiving Provider Edge Node

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Application Note
3.2 Differential Clock Recovery

MSAN-198

This method is similar to the first, except that the interrupt is generated from a division of the reference clock frequency. At regular intervals according to the reference clock, a counter driven by the TDM service clock is read, and the result used to generate a clock packet relating the service clock to the reference clock (Figure 6).
Reference clock

n counter
read

Host CPU
Clock packets

TDM in

LIU

Clock Data

MT90880

Figure 6 - Source Provider Edge Node On receiving the packets, the receiver host compares the relationship between the reference clock and the service clock, and adjusts a DCO to achieve the same relationship against its own reference clock. The output of the DCO is used to clock the TDM data out of the MT90880, and onto the TDM circuit.
Reference clock read

Host CPU

DCO

~
Clock

counter

Clock packets

MT90880

LIU

TDM out

Data

Figure 7 - Receiving Provider Edge Node

3.3

Using the RTCP protocol

RTCP is a standard protocol used for maintenance of real time links over a packet network. It is normally associated with RTP (Real Time Protocol), which is a protocol for the transport of real time data across a packet network. However, in this case, RTCP could be used as a standalone protocol for communicating the frequency of a clock. The RTCP protocol transmits packets at a rate of approximately one every few seconds across the packet network. These packets contain largely statistical information about the data packets received using RTP. However, each packet also contains two timestamps: Wall clock time, a standard reference clock; and the RTP timestamp, relative to the real time clock being used (in this case, the TDM service clock). Wallclock time is defined as the number of seconds since 00.00 hours UTC on the 1st January 1900. It contains two parts: a 32-bit integer and 32-bit fractional part. Provided the wallclock time at each end of the network is accurately aligned, this could be used to represent a primary reference clock. Usually wallclock time is maintained by using NTP, but this may not be accurate enough for the purpose. Alternatively, wallclock time could be related to a telecom clock or GPS clock at each provider edge.

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Application Note

The RTP timestamp is defined as the value of a service clock counter at the same instant that wall clock time was read. The counter increment can be defined in a profile; for example, it could be defined as a count of the number of bit periods since the last packet was sent. Hence, an RTCP packet can be used as a standards-based means of transporting timing information across the network for use with both adaptive and differential clock recovery methods. Where there is no common clock, the wallclock times can be ignored, and the RTP timestamp used to implement an adaptive clock recovery scheme. Where there is a sufficiently accurate clock at either end of the network, this can be used to drive wallclock time. The RTCP packet then can be used to indicate the relationship between the reference (wallclock time) and the service clock (RTP timestamp).

4.0

Proof of Concept using the MT90880 Evaluation Board

The evaluation board for the MT90880 contains some additional hardware to allow schemes based on the ideas outlined in this application note to be evaluated (see Figure 8). Using this hardware it is possible to implement both adaptive and differential clock recovery techniques, and assess the viability for use in a particular type of system. The hardware includes a stable, digitally controlled oscillator, a DPLL (Zarlink MT9045) to generate the TDM service clock and frame pulse from the variable oscillator, an external clock input and a divider to produce a low frequency interrupt from the service clock. The TDM service clock and frame pulses are used to control a TDM switch (Zarlink MT90869). This contains internal bit error rate test sequence logic, which can be used to generate test data for converting into packets in the MT90880 device.

MPC8260 CPU
External clock interrupt Timer interrupt

Setup and clock packets

MT90880 TDM-IP Processor

TDM Switch
MT90869

ST-bus

1024

Packet interface frame pulse

Frequency control

clock

~
DCO
16.384 MHz 100 ppm

DPLL
MT9045

Figure 8 - MT90880 Evaluation Board - Clock Recovery Hardware

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Application Note
4.1 Adaptive Clock Recovery with the MT90880 Evaluation Board

MSAN-198

The following diagram (Figure 9) shows how the evaluation board can be used to trial an adaptive clock recovery scheme.

External clock

interrupt Timer

MPC8260 CPU

Setup and clock packets ST-bus

MT90880 TDM-IP LAN

interrupt 1024 Frequency control

TDM Switch

frame pulse DPLL

clock

~
DCO

Source Board
Setup and clock packets ST-bus

External clock

interrupt Timer

MPC8260 CPU

MT90880 TDM-IP

interrupt 1024 Frequency control

TDM Switch

frame pulse DPLL

clock

~
DCO

Receiving Board

Figure 9 - Adaptive Clock Recovery with the MT90880 Evaluation Board On the source board, the TDM service clock is generated by the DCO. This allows the clock to be set to any given frequency within a range. Furthermore, the CPU is able to inject controlled jitter and wander into the DCO output, to test the ability of the receiving end to track the input. The clock and frame pulse output from the DPLL is used to clock a TDM stream out of the TDM switch and into the MT90880. The content of this stream is arbitrary, and it is used to simulate a real stream running at a given rate. For instance, the bit error rate capability of the MT90869 could be used to generate a pseudo-random bit-stream, allowing the integrity of the data stream to be checked at the receiver node. The frame pulse is divided down by up to 1024, and this is used to generate an interrupt to the CPU. On interrupt, the CPU generates a clock packet to be sent to across the network to the receiving node containing the timestamp. This can be either in RTCP format, or using a proprietary packet type. If the appropriate equipment is available, then the packets through the LAN could be delayed by varying amounts to simulate heavy traffic loading and congestion on the network. Alternatively, the board could be connected to a real LAN. At the receiver, the clock packets are routed to the CPU. The recovered clock is again generated using the DCO, and is periodically adjusted dependent on the arrival rate of the clock packets. The clock signal from the DPLL is routed to the CPU's timer/counter block to allow comparison of the recovered clock frequency against the timestamps received from the source. The recovered TDM clock is used to clock the data out of the MT90880 and into the TDM switch. If the bit error rate test capability of the MT90869 has been used to generate the data, the integrity of the received data can be checked. The internal queues can also be monitored to check for underflow and overflow. This can be an indication that the clock may not be as accurate as required.
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4.2 Differential Clock Recovery with the MT90880 Evaluation Board

Application Note

The next diagram (Figure 10) shows how the evaluation board can be used to trial a differential clock recovery scheme.

interrupt Timer

MPC8260 CPU

Setup and clock packets ST-bus

MT90880 TDM-IP LAN

interrupt 1024 Frequency control

TDM Switch

frame pulse DPLL

clock

~
DCO

Source Board
Setup and clock packets ST-bus

interrupt

MPC8260 CPU
Timer interrupt 1024

MT90880 TDM-IP

~
Primary Reference Clock

TDM Switch

Frequency control

frame pulse DPLL

clock

~
DCO

Receiving Board

Figure 10 - Differential Clock Recovery with the MT90880 Evaluation Board On the source board, the external clock input is used to bring in a low frequency primary reference clock of some type (e.g. GPS clock or a stable test clock). The TDM service clock is generated by the DCO, allowing the actual frequency to be controlled within a given range. The external reference clock is routed into the CPU's interrupt input, causing a periodic interrupt, while the TDM service clock is routed into a timer/counter channel on the CPU, allowing the number of clock periods between reference clock interrupts to be counted. A clock packet can then be constructed, relating the frequencies of the two either using RTCP, or a private protocol encoding the relationship. As with the adaptive scheme, the clock and frame pulse output from the DPLL is used to clock a TDM stream out of the TDM switch and into the MT90880. At the receiver, the clock packets are routed to the CPU. The TDM service clock is again generated using the DCO, and as with the source board, both the service and reference clocks are routed into channels on the CPU's timer/counter. The relationship between the service clock and the common reference is adjusted to match that specified in the incoming clock packets. The recovered TDM clock is used to clock the data out of the MT90880 and into the TDM switch. If the bit error rate test capability of the MT90869 has been used to generate the data, the integrity of the received data can be checked. The internal queues can also be monitored to check for underflow and overflow.

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