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APPENDIX A
Farmwald/Horowitz Patents No. 1. Claim Term, Phrase, Claims or Clause access time 937/4(1), 5(1) information 097/6(1) Rambuss Preliminary Proposed Construction information that indicates a time a device must wait from receiving a transaction request to responding to a transaction request an amount of time that must transpire before commencing an action an amount of time associated with a read as a result of nVidias Preliminary Proposed Construction information that specifies a predetermined non-zero amount of time that a device must wait from receiving a transaction request to responding to a transaction request a predetermined non-zero amount of time that must transpire before commencing an action. a predetermined non-zero amount of time that must transpire before data is read from a memory device. plain meaning.

2.

delay time

937/31(30) 696/27(26), 29(26)

3.

read delay

997/1, 19, 32, 35, 38 997/1, 19, 32, 38 696/26, 29(26), 30(26) 281/36, 42(36), 43(36) 097/1, 5(1), 26 937/1, 3(1), 4(1), 5(1), 18, 23(18), 24(18), 37(30) 020/2(1), 32(28), 34(28), 37(28), 38

4.

in response to

5.

information that represents an amount

937/32(30)

information that indicates an amount of time which lapses 1

information that indicates a predetermined non-zero amount of time

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No.

6. 7.

Claim Term, Phrase, Claims or Clause of time which lapses latch circuitry 937/19(18) latch 937/19(18)

Rambuss Preliminary Proposed Construction a circuit or circuit element to capture and maintain a signal value to capture and maintain a signal value

8.

memory controller / controller device / memory controller device

997/1, 3(1), 19, 26(19), 31(19), 32, 38 696/26 937/18, 19(18), 22(18), 23(18), 24(18), 26(18), 29(18), 30, 31(30) 020/1, 2(1), 10(1), 11(1), 12(1), 13(1), 14(1), 38, 47(38), 49(38)

an integrated circuit device that includes circuitry to direct the actions of one or more memory devices

nVidias Preliminary Proposed Construction that must lapse. circuitry for maintaining a particular state of a signal until being reset. maintaining a particular state of a signal until being reset as distinguished from sampling a device that includes circuitry to direct the actions of one or more memory devices

9.

integrated circuit controller device memory device

020/38

no separate construction required

10.

937/2(1), 4(1), 5(1), 8(1), 18, 23(18), 24(18), 30, 32(30), 36(30) 37(30), 38(30), 097/1, 5(1), 6(1), 26 281/36, 38(36),

an integrated circuit device in which information can be stored and retrieved electronically, not including a memory controller

a controller device constructed on a single monolithic substrate, commonly called a chip A device in which data can be stored and retrieved electronically.

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No.

Claim Term, Phrase, or Clause

Claims 39(36), 40(36), 42(36), 43(36), 44(36), 45(36), 46(36) 696/26, 27(26), 28(26), 29(26), 30(26), 31(26), 997/1, 19,26(19), 32, 38 020/1, 2(1), 28, 29(28), 32(28), 34(28), 35(28), 37(28), 38, 49(38)

Rambuss Preliminary Proposed Construction

nVidias Preliminary Proposed Construction

11.

operation code

937/1, 3(1), 4(1), 5(1), 14(1), 15(1), 17(1), 18, 23(18), 24(18), 29(18), 30, 37(30) 020/2(1), 32(28), 34(28), 37(28), 38 696/26, 29(26), 30(26), 35(26) 997/1, 2(1), 3(1), 19, 26(19), 31(19), 32(19), 38

one or more bits to specify a type of action

One or more control bits specifying a type of action to be performed by a memory device.

12.

precharge information 937/17(1) 696/35(26),

one or more bits indicating whether the sense amplifiers and/or bit lines(or a portion of the sense amplifiers and/or 3

Information denoting whether sense amplifiers and/or bit lines (or a portion of the sense amplifiers and/or bit lines)

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No.

Claim Term, Phrase, or Clause programmable register representative of a number of clock cycles of the external clock signal to transpire sample / samples / sampling

Claims 997/19, 32(30)

Rambuss Preliminary Proposed Construction bit lines) should be precharged a register whose contents can be modified based on information received from an external source indicates a number of clock cycles of the external clock to occur

nVidias Preliminary Proposed Construction should be precharged. A register within a memory device that is permanently or semi-permanently loaded with a fixed value. indicates a number of clock cycles of the external clock signal that must transpire before commencing an action.

13.

696/26

14.

696/28(26) 937/5(1)

15.

997/1, 19, 32, 38 696/27(26), 28(26) 097/1, 26 937/1, 18, 23(18), 26(18) 020/14(1), 17, 25(17), 29(28), 30(28), 34(28), 49(38)

to obtain at a discrete point in time / obtains at discrete points in time / obtaining at discrete points in time

obtain/ obtains/ obtaining at one or more discrete points in time, as distinguished from latch/ latches/ latching.

16.

value is representative 696/27(26), of a delay time to 29(26) transpire variable delay line 020/11(1), 12(1)

information that indicates a delay time to occur

17.

a circuit or circuit element to provide a variable amount of delay

information that indicates a predetermined non-zero amount of time that must transpire before commencing an action. a delay line that uses feedback to provide a varying amount of the delay.

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Barth II Patents No. 1. Claim Term, Phrase, or Clause after a second/third delay time has transpired memory device Claims 119/21 952/21 953/25 2. 050/29 119/21 952/21, 22(21) 953/25 3. integrated circuit memory device 050/29 119/21 952/21, 22(21) 4. sense command 050/29 119/21 952/21 953/25 5. the memory device initiates a write operation after a first delay time transpires 953/25 the writing of data is initiated after a first delay time The memory device begins to perform a write operation only after a first predetermined non-zero amount of time transpires. one or more bits that specify that a row of memory cells be activated Signals provided to a memory device for initiating a sense operation within the memory device. no separate construction required a memory device constructed on a single, monolithic substrate, commonly called a chip a integrated circuit device in which information can be stored and retrieved electronically, not including a memory controller A device in which data can be stored and retrieved electronically. Rambuss Preliminary Proposed Construction after a second/third amount of time has elapsed nVidias Preliminary Proposed Construction After an additional second/third predetermined non-zero amount of time has transpired.

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6.

7.

the write command is presented/posted internally to/within the memory device after a first/second delay [time] has transpired from when the write command is received write command

050/29 119/21 952/21

the write command is held and issued internally after a first/second delay [time] has transpired from when the write command is received

The write command is provided to a memory core of a memory device only after a first/second predetermined nonzero amount of time has transpired from when the write command is received by the memory device.

050/29 119/21 952/21 953/25

one or more bits that specify that the memory device receive and store data

Signals provided to a memory device for initiating a write operation within a memory device.

8.

delay time

119/21 952/21 953/25

an amount of time that must transpire before commencing an action

a predetermined non-zero amount of time that must transpire before commencing an action.

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