Timing Diagrams Using Xilinx 10.

Timing Diagrams Using Xilinx 10.1

Instructor: Bea Jarupan

Introduction
In this tutorial you will use Xilinx 10.1 to analyze and simulate a clocked sequential circuit. The circuit to be simulated uses an edge triggered JK-type flip-flop and an edge triggered D-type flip-flop.

Analyzing the Circuit

Q1

Q0

Figure 1: Final design

Create a new Project

Invoke the Project Navigator, and create a new project by selecting File New Project with the name Newproj. In the New Project window, specify Schematic as the Top-level source type. After clicking Next, specify XC9500 CPLDs as the device Family, XST (VHDL/Verilog) as your Synthesis Tool from the pull-down menus, and VHDL as the Preferred Language. We will not create new sources for this project at this point. Continue clicking Next, Next, Next and then Finish to end the new project setup process. To create new source, click on Project New Source. In the window that opens up, select the entry Schematic and give the name top in the File Name field. Click Next and in the next window click Finish. Once you do that a blank schematic will open up in Xilinx ECS, the Schematic Editor window.

Timing Diagrams Using Xilinx 10.1

Inputs and Outputs

Start by adding four I/O Markers to the design. Click on Tools Create I/O Markers. A window will pop up, requesting you to specify the input and output port names. Specify inputs as DI, CLK, CLR and the output as DO. Separate the I/O Marker names by commas. This will add 3 inputs and an output with wires attached to them in your schematic.

Drawing the Circuit

Click on Add Symbol to bring up the Symbols library. Using the tools you have learned about in the previous projects, draw the circuit shown in Figure 1. You will need the following components from the Symbols Library. A JK-type flip-flop with a clear input (named fjkc), a D-type flip-flop with a clear input (named fdc). The flip-flops can be found under the Category: Flip_Flop; or you can type the component name in Symbol Name Filter. Place the symbols as per the final diagram. Now wire up the circuit to resemble Figure 1 the final circuit. Before you save your changes and start the simulator, you need to check the circuit. Click on Tools Check Schematic. If there are errors, they will be displayed in the Transcript window at the bottom of Project Navigator. If there are no errors, then the Console tab will display No error or warning is detected. When you are done drawing your circuit, check its integrity and save it. You should have no errors. When you have successfully checked and saved your circuit, you are finished with your schematic design.

Simulating the Circuit

Click on the Sources tab in your Sources window. In the Sources for: Implementation sub-window, click on your schematic file top (top.sch) to make it active. In the Processes sub-window, click on the (+) in front of the Design Utilities to expand the view. Select View HDL Functional Model and right click to select Properties. In the Process Properties window, select VHDL in the Value field and click OK. Follow the same procedure to select VHDL for the View HDL Instantiation Template. Now select Project New Source. In the window that opens up, select the option Test Bench Waveform. Specify wave as the name for the waveform in the File Name field and click on Next, Next and then in the following window click Finish. This will open the HDL Bencher. In the Initialize Timing window (Figure 2), set Clock High Time to 50, Clock Low Time to 50, Input Setup Time to 10, Output Valid Delay to 10, and Initial Length of Test Bench to 1200 ns. Make sure that the Single Clock option is selected and the Rising Edge option is also selected. Deselect the GSR (FPGA) option in Global Signals. Click Finish.

Timing Diagrams Using Xilinx 10.1

Figure 2: Initialize Timing window

When you power up a circuit containing flip-flops, the initial state of the flip-flops is unknown. You need to clear the flip-flops before you can begin the actual simulation. To do this, assert the CLR input (set it to 1) for 1 clock period at the beginning of the simulation. After the first clock cycle, set your CLR to 0. Note that the input sequence is applied only after the flip-flops have been reset or cleared. As long as the CLR input is 1, the outputs (Q1, Q0) will always be 0. So when CLR is 0, start applying your input sequence DI = 01011111.. in the second clock cycle. Your input stimulus is shown in Figure 3. Save the test bench waveform. To set the end of simulation to 1200 ns, click on wave (wave.tbw) in the Sources for: Behavioral Simulation sub-window. Now in the Processes sub-window, right click on the option Simulate Behavioral Model and select the Properties. In the Process Properties window, change the Simulation Run Time to 1200 ns. Save the waveform for the test bench setup. To simulate the circuit, double-click on Simulate Behavioral Model in the Processes sub-window under ModelSim Simulator.

Figure 3: Test Bench Waveform window