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Department of ECSE

TE 341

TE341: Analogue Electronics for Engineers II


Dr. KISSAKA Office: KIJITONYAMA

Course Assessment:
UE 60% end of Semester (According to UE Timetable) CA 40%
2 tests: (30% equal weight)
1 mid-semester (wk 8)
1 end of semester (wk 13)

4 Units Course Lecture: 3 Hrs/wk Tutorial: 1 Hr/wk Practical: 2 Hrs/wk


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Lab work: (10%)


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Lecture

Time Table:
Time

Labs Tutorial

Course Outline:
Amplifier design Power amplifiers Differential amplifiers Operational amplifiers Voltage comparators CAD
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10 11 12 13 14 15 16 17 18 19

Mon Tue Wed Thu Fri


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Lecture 1

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TE 341

Reference/Text Books:
Floyd, T., Electronic Devices, Maxwell Macmillan, 3rd Edition or Higher Boylestad, R. and Nashelsky, L., Electronics Devices and Circuit Theories, Prentice-Hall, 5th Ed. 1991 Floyd, T. Fundamentals of Linear Circuits. Prentice Hall Career & Technology, 1992 Sedra, A. and Smith, K. Microelectronic Circuits, Saunders College Publishing, 3rd Ed., 1991.
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Amplifier Design:
Amplifier for Symmetrical Operation (Class A)
Class A operation means that the transistor operates in the active linear region at all the times For class A amplifier the Q-point should be at the centre of the transfer characteristic to ensure symmetrical operation and maximum swing (Variation) at the output. Current flows for 3600 of the input ac signal The maximum variation should not cause the transistor(s) to exceed maximum ratings
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Amplifier Design
IC (mA)

Amplifier Design
IC (mA)
IB = 500A IB = 400A

IC(max)
Saturation Region

PD(max)
Distorted output
50 40 30

Q-point close to Saturation


IB = 500A

SOAR

IB = 300A IB = 200A IB = 100A

IB = 400A IB = 300A IB = 200A IB = 100A

ICQ
20 10

ICE0 0 VCE(sat)
Cut-off Region
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VCE(max)

VCE (V)

0
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VCEQ

VCE (V) DC load line


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Lecture 1

Department of ECSE

TE 341

Amplifier Design
DC load line IC (mA)
50 40 30 20 10

Amplifier Design
IC (mA)
Output Current 50 40 30

Q-point close to Cut-off


IB = 500A IB = 400A IB = 300A

Centred Q-point close


Input Current IB = 500A IB = 400A

Distorted output

ICQ
20 10

Q 0

IB = 200A IB = 100A

IB = 300A IB = 200A IB = 100A

ICQ VCEQ

VCE (V)
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VCEQ

VCE (V) DC load line


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Amplifier Design
Design of CE, RC coupled, Single stage, Class A Amplifier
VC C

Amplifier Design
Given Specifications: Maximum Voltage swing across R IC C2
L

2Uo

RS C 1

R1

RC

. RL u o

Maximum input voltage and source Resistance 2US and RS UO Lower and upper cutoff frequencies fL fU f
12

us

uin R2

IE

RE

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Lecture 1

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TE 341

Amplifier Design
Assumptions: RS Rin or Uin US

RS

Amplifier Design
uin Determination of VCC (DC supply voltage)
R2 R1 RE Without any ac signal at the input

us

i.e. negligible drop across RS Voltage gain is given by:

VCC = I C RC + I E RE + VCE
For IE IC , then

Au =
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Uo Uo Uin Us
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VCC = I C RC + I C RE + VCE
But the Vcc must supply both dc voltage and ac variation caused by ac input signal
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Amplifier Design
VC C

Amplifier Design
Therefore:

RS C 1

R1

RC

IC C 2 R uo
L

VCC I C RC + I C RE + VCE + iC ( RC RL ) + iC RE
dc component ac component

us

uin R2

IE

RE

ic
RC RL u o

For maximum ac collector current, VCE has to be minimum i.e. VCE(sat) (Saturation voltage)

VCC I C ( RC + RE ) + VCE ( sat ) + $C ( RC RL ) + $C RE i i


For small signal transistors, VCE(sat) 0.5V

RE
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Lecture 1

Department of ECSE

TE 341

Amplifier Design
To obtain symmetrical current signal without clipping, the Q-point current IC ic For design purposes,
Therefore: ICQ 0

Amplifier Design
ic ic
The output voltage shall develop across the parallel connection of RC and RL

U O = $C ( RC RL ) i

$C = I = I i CQ C
+ IC

Therefore

VCC = IC

(RC

+ RE

) + V C E ( sa t )

(R

RL ) + IC RE
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$c = I = U O i C RC RL
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Amplifier Design
Small signal equivalent circuit using r-parameters

Amplifier Design
ic
RC RL u o

ib us

re
R2 R1 R E

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TE 341

VCC = I C ( RC + RE ) + VCE ( sat ) + I C ( RC RL ) + I C RE

Amplifier Design
Therefore:

Amplifier Design
Therefore:

VCC
But

RC R R RE RE VCE ( sat ) + U O + + C L+ R R C L RC RL RC RL RC RL
Au = RC RL RE

RC and VCC are unknown, In this case we consider RC RL and RL is known Hence:

2 R + RL VCC VCE ( sat ) + U O + 1 + C RL Au

And

R ( R + RL ) RC + RL RC = C C = RC RL RC RL RL
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2 VCC VCE ( sat ) + U O 3 + Au

Choose Standard Value (3V, 4.5V, 6V, 9V, 12V, etc


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Amplifier Design
Determination of RC From equation 1:

Amplifier Design
Determination of RE From

2 R + RL VCC VCE ( sat ) + U O + 1 + C RL Au Then:


RC V C E ( sat ) V 2 R L CC 2 3 UO Au

Au =

RC RL RE

RE =

RC RL Au

RC and RE have been determined without knowing the type of transistor to be used This is possible because the overall voltage gain is determined by the external components only
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Check whether RC RL if not recalculate VCC


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Lecture 1