VHDL Assignment NO 2

1. Describe a 16-1 Mux in VHDL using Behavioral Modeling.. 2. Describe a 3-to-8-line decoder/demultiplexer in VHDL using Behavioral modeling... 3. Realize a J-K Master slave Flip-Flop using Behavioral Modeling in VHDL.

4. Realize a 3 Bit up/down synchronous Counter using Behavioral Modeling in VHDL. 5. Design a BCD to 7-Segment Decoder in VHDL using Behavioral Modeling. 6. Realize a Twisted ring or Johnson counter in VHDL using Behavioral Modeling. 7. Design a Counter of a microwave Owen which counts down the values from input time as HH:MM:SS to 00:00:00 in VHDL using Behavioral Modeling. 8. Realize an 8-bit barrel-shifter in VHDL using Behavioral Modeling. 9. Realize a Carry Look-Ahead generator in VHDL using Behavioral Modeling. 10. Realize a 4-bit adder/Subtractor (use mode control input to select b/w add and sub) in VHDL using Behavioral Modeling. 11. Realize a BCD up/down Counter in VHDL using Behavioral Modeling.. 12. Realize a BCD adder Circuit in VHDL using Behavioral Modeling.. 13. Design a Bidirectional shift register using MOD Control in VHDL using Behavioral Modeling. 14. Design a 4-bit Ring counter in VHDL using Behavioral Modeling. 15. Design a Circuit to find the factorial of a given number using Functions in VHDL.
16. Design a Universal Counter. It can count up or down, pause, be loaded with a specific value, or be synchronously cleared. Its functions are summarized in Table.

1 | DOEACC VLSI Design Group

Sreejeesh S.G

17. Design a Stop Watch, which displays the time in three decimal digits, and counts from

00.0 to 99.9 seconds and wraps around. It contains a synchronous clear signal, clr, which returns the count to 00.0, and an enable signal, go, which enables and suspends the counting. This design is basically a BCD (binary-coded decimal) counter, which counts in BCD format. Our Broad has a 100-MHz clock; we first need a mod-2500, 000 counter that generates a one-clock-cycle tick every 0.1 second. The tick is then used to enable counting of the three-digit BCD counter. 18. Design a Generic Multiplexer in VHDL using Behavioral Modeling.

19. Write a VHDL program for sorting in ascending/descending 10 integers with a mode control 20. Write a VHDL program to design a 16X8 dual port RAM in Behavioral Modeling.

21. Design a Dual Port Asynchronous Read/Write RAM using VHDL in Behavioral Modeling. 22. Design a Dual Port Synchronous Read/Write RAM using VHDL in Behavioral Modeling.

2 | DOEACC VLSI Design Group

Sreejeesh S.G