EE101B: Common-source amplier

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Lecture 7 EE101B: Common-source amplier

EE101B Department of Electrical Engineering Stanford University Prof. M. Hershenson Prof. K.V. Shenoy

Common-source amplier in ICs A simple common-source amplier Circuit analysis Equivalent amplier model Signal range Graphical analysis

Degenerated common-source amplier Discrete common-source amplier Coupling capacitors Analysis Loading eects Example

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Reading for this lecture

From Sedra & Smith Section 4.7.1 Section 4.7.2 Section 4.7.3 Section 4.7.4

Practice problems Example 4.11

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A simple common-source amplier

Consider the common-source amplier

VDD RD VO VI vin M

We call it common-source amplier because the source is connected to ground (the common terminal) The input AC signal is fed from the gate The output AC signal is measured at the drain

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Circuit analysis of the simple common-source amplier

To analyze this amplier we will do the following: 1. Perform DC analysis (nd bias point: drain DC current and check that the transistor is in the saturation region) 2. Find circuit small-signal AC model (based on the bias point obtained) 3. Perform AC analysis

So far we have seen how to perform the DC analysis of simple CMOS circuits (Lecture 5) and how to obtain their small-signal AC model (Lecture 6). In this lecture we focus on how to perform the small-signal AC analysis.

In the remainder of this lecture, we assume that the transistor operates in the saturation region at its bias point.

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AC small-signal analysis: model

Now we nd the AC (small-signal) model for the common-source amplier shown in the rst slide. For AC analysis: Kill the DC sources (i.e., short the DC voltage sources and open the DC current sources) Substitute the transistors by their AC (small-signal) model.

+ vin vgs gm vgs ro

vout RD

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AC small-signal analysis: voltage gain

1. Voltage gain= vout : vin The input source is directly connected to the gate so we have vin = vgs so the current through the dependent current source is gm vin Now it is easy to nd vout , vout gm vin R r
D o

We have ro in parallel with RD and all the current from the dependent source ows through the total drain resistance so vout = gm vin (RD and the gain is Av = vout vin = gm (RD ro ) ro )

Note that the gain is negative. (When vin increases, vgs also increases. This means that id increases so the drain voltage (vd ) decreases. Since when vin increases, vd decreases the gain is negative. Note that the absolute gain can still be greater than one !!)

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AC small-signal analysis: input and output resistances

The input and output resistances (Rin and Rout ) of an amplier are two important characteristics of the amplier. We will be interested in them when the amplier is connected to a source with non-zero impedance, when it is connected to a load or when it is connected to another amplier VDD RD Rin VO M vin Rout

The input resistance is the total resistance looking into the amplier (or in other words, is the resistance presented to the input signal source) The output resistance is the total resistance seen from the output of the amplier.

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AC analysis: input resistance

1. Input resistance: To compute the input resistance we connect a test voltage source at the input of the amplier and we compute how much current is owing through it. Rin imeas vtest vgs + gm vgs ro vout RD

Since the gate resistance is innite, we have imeas = 0 and the input resistance is just Rin =

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AC analysis: output resistance

2. Output resistance: To compute the output resistance we kill the input source, connect a test voltage source at the output of the amplier and we compute how much current is owing through it. Rout imeas + vgs gm vgs ro RD vtest

Since vgs = 0, we have that gm vgs = 0 so the dependent current source is like an open circuit. then we have vtest = imeas (RD and the output resistance is Rout = RD ro ro )

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Output resistance
Lets try to understand the expression we obtained for Rout . Looking into the output node we see RD in parallel with ro . For AC signals, RD is connected between the transistor drain and ground ro is the small-signal resistance looking into the drain of the transistor (since its source is connected to ground).

RD

id,2 id,1 M1

imeas vtest

In the gure id,1 = vtest /ro and id,2 = vtest /RD . Then we can write, vtest vtest + imeas = id,1 + id,2 = ro RD so vtest 1 = 1 = R D ro imeas + R1D ro

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Equivalent amplier AC model

An equivalent AC amplier model for the common-emitter amplier just seen is Rout vin vRin Av vRin

vout

where Av = gm (RD Rout = RD ro ro )

Note that Rin = . This is a quite useful high-level model. We will make use of it when we study multistage ampliers.

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Signal range: linear amplier

We rst take a look at the actual voltages at drain, source and gate for the common-source amplier: they have both a DC component and an AC component. Instantaneous voltages at transistor nodes Source voltage. The source is grounded so it has no AC (or small-signal) component, i.e., vS = VS = vs = 0. Gate voltage. Assuming the input AC signal is vin = vin sin(t) and the input DC signal is VI , vG = VI + vin sin(t) Sometimes (if gain is large) we can neglect the AC component at the gate because it is pretty small compared to the AC component in the drain. The maximum and minimum values of the gate voltage are: max. gate instantaneous voltage vG,max = VI + vin min. gate instantaneous voltage vG,min = VI vin Drain voltage. vD = VD +vin Av sin(t) = VDD ID RD +vin Av sin(t) We call VM = |vin Av | (amplitude of AC signal at the drain) and we have

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max. drain instantaneous voltage vD,max = VDD ID RD + VM min. drain instantaneous voltage vD,min = VDD ID RD VM

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Graphically, VDD RD vin vin VI vin VD M VM VM

VG

So far we have assumed that the transistor is biased in saturation. We also have assumed that the transistor remains in saturation for the entire range of the AC input signal. If the transistor enters another region of operation, the analysis we just did would not be valid (remember we derived the small-signal model for the transistor in saturation!) We now nd out for what values of the input signal the transistor remains in saturation

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Signal range: limits

If the drain voltage is too low (a threshold below the gate voltage), the transistor will enter the linear region. The transistor behaves like a resistor and the output voltage is no longer a linear amplication of the input voltage (it is clipped below). This is not a desirable behavior (in general we want to build linear ampliers).

VDD RD VG vin vin VI vin VD M

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In order to keep the transistor in saturation, we need vD vGS Vt . This has to be true at all times. The critical case is when the drain voltage is minimum and the gate voltage is maximum vD,min vGS,max Vt so a limit on the swing at the drain is given by VM VDD ID RD VI vin + Vt or equivalently, in terms of an upper limit on the input signal VDD ID RD VI + Vt vin 1 + |Av | The drain voltage cannot be above the supply voltage. Otherwise the transistor drain current would be owing out of the drain which is not possible. For very low values of the gate voltage, the signal at the drain clips at VDD . VDD RD VG vin vin VI vin To avoid this behavior and keep the transistor in saturation, we need vD,max VDD VD M

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so another limit on the signal swing at the drain is VM ID RD which in terms of a lower limit in the input signal can be written as ID RD |Av | There is also a limit on how large the input AC signal can be so that our linearity approximation holds. We saw in Lecture 6 that for the small-signal 2 (VGS Vt ). In model to be valid we need vgs this case, vin = vgs so the requirement for vin is vin vin 2 (VGS Vt )

Taking to mean at least a factor of 10, we have the condition vin 0.2 (VGS Vt ) in terms of VI , vin 0.2 (VI Vt ) Note that the condition above is more stringent that the condition imposed by making sure that the transistor is not turned o. To keep the transistor on, we need vGS Vt . The minimum value of vGS is VI vin . Thus, another limit on vin is vin VI Vt

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Designing for maximum signal range

Normally we want to bias the amplier at a point that allows maximum signal swing. If the DC drain voltage is too high (close to VDD ), we will be able to have large negative swings but we wont be able to have large positive swings Similarly if the DC drain voltage is too low (close to ground), we will be able to have large positive swings but we wont be able to have large negative swings Thus, it makes sense to pick a DC value for the drain voltage that is somewhere in the middle of VDD and ground. The point for maximum symmetrical swing (same amplitude of positive swing than negative swing) can be obtained by equating the rst two limits we derived above for the input signal vin . VDD ID RD VI + Vt ID RD = |Av | 1 + |Av | if |Av | 1 ID RD = VDD ID RD VI + Vt or in terms of VI VI = VDD 2ID RD + Vt

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Maximum voltage gain

Consider the common-source amplier with RD very large (so RD ro ro ) and VDD also very large (so we can allow a large voltage drop across RD ). Under these circumstances the amplier gain is vout Av,max = = gm (RD ro ) gm ro vin or 2VA Av,max = gm ro = (VGS Vt ) The ratio 2VA / (VGS Vt ) is an upper bound on the gain we can obtain from a common-source. In practice we have |Av,max | 10 100 (in sub 0.1m technologies, this value is more between 1 10). A resistively loaded common-source, has gains much smaller than Av,max . The reason is that RD cannot be made very large for output voltage swing considerations. There are other ampliers (ampliers loaded with transistors) in which one can get gains close to Av,max . We will see these ampliers in the next lecture.

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Design trade-os
How do we design an amplier for high gain? Lets RD . Then we can write, assume for now that ro vout 2VRD 2 kVR = gm RD = = D Av = vin VGS Vt ID where VRD = ID RD is the DC drop across RD . To have a large gain, we can: Increase k. For a given process and Cox are xed, so to increase k we must make the ratio W/L large. But we cannot make W/L arbitrarily large. A large W means large areas, large capacitances and slow circuits (more on this in later lectures). The smallest L is limited by the process technology. Also (in reality) a small L means small ro and worse behavior predictability. Increase VRD . Since we have a nite supply voltage, we cannot increase VRD arbitrarily. Typically the maximum VRD we can have is limited by the voltage swing requirements. Decrease ID (assuming constant VRD ). Small currents give raise to smaller values of gm and larger values of ro . This in turn, gives raise to larger time constants and thus slower ampliers (more on this in later lectures).

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Increase ID (assuming constant RD ). We cannot increase ID arbitrarily because of swing constraints and also power constraints.

As you can see, there are a lot of design trade-os, we must consider when designing a circuit.

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Graphical analysis
In Lecture 5, we saw how to plot the large signal V0 /VI characteristic of a grounded common-source amplier. We dont repeat the analysis here but show again the resulting transfer characteristic.

6 5 4

VO (V)

slope=Av
3 2 1 0 0

VI (V)

There is a range of VI for which the circuit behaves as a somewhat large gain amplier. This is the region where the slope V0 /VI is high. The gain is negative since as we increase VI , V0 decreases.

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The gain (gm (ro RD )) we found using the small-signal equivalent model is just the slope of this transfer characteristic in the region of high gain. Remember in Lecture 5 (page 5.4), we derived that for = 0, the relationship V0 /VI in the high gain region was, 1 W VO = VDD n Cox (VI Vt )2 RD 2 L Taking partial derivatives, we nd W VO = n Cox (VI Vt ) RD = gm RD VI L which is the same as we obtain with the small-signal analysis if we consider ro = (corresponding to = 0).

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Degenerated common-source amplier

A degenerated common-source has: The input AC signal is fed from the gate The output AC signal is measured at the drain The source connected to ground with a resistor RS

VDD RD VO VI M1 RS

This circuit is an example of shunt-series feedback which we will study at the end of the quarter.

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Degenerated common-source amplier: circuit analysis

For circuit analysis we follow the next steps: 1. Perform the DC-analysis as was covered in Lecture 5. 2. We nd the AC-model, which is similar to the previous common-source except that we have a source resistance and we need to add another transconductance to show the body eect.

vin

+ vgs

vout gm vgs ro RS gmb vbs RD

+ vsb

3. We perform the AC-analysis using the AC-model found in previous step.

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Degenerated common-source amplier: voltage gain

1. Voltage gain= vout : For this analysis we assume vin ro = . id vout + gm vgs vgs gmb vbs vin RD + is vsb R
S

We apply KVL, across the source resistor to compute the source voltage is v s = is R s We apply KVL, across the drain resistor to compute the output voltage is vout = id RD We apply KCL at the drain and source id = gm vgs + gmb vbs (3) Since vgs = vin vs and vbs = 0 vs , we can write equation (3) as id = gm (vin vs )gmb vs = gm vin (gm + gmb ) vs (4) (2) (1)

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Now we substitute equations (1) and (3) in (4) and have id = gm vin (gm + gmb ) id Rs which we can rewrite as gm id = vin 1 + (gm + gmb ) RS Now substituting (2) in (6), we nd the small-signal voltage gain, gm vout = RD vin 1 + (gm + gmb ) RS (6) (5)

Some comments, For RS = 0, Av = gm RD (same as we derived before for ro = ). We have, vout gm = RD = gm,e RD vin 1 + (gm + gmb ) RS where gm,e = gm /(1 + (gm + gmb ) RS ). We have eectively reduced the transconductance (and gain) of the common-source amplier by a factor 1 + (gm + gmb ) RS .

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This amplier has a smaller gain but also better linearity. For the same values of vin , we have a smaller vgs , and thus the small-signal assumption is valid for larger values of vin , vgs = vin 1 + gmb RD 1 + (gm + gmb ) RS 1, we can write

Assuming (gm + gmb ) RS

vout gm RD 1 RD = = vin (gm + gmb ) RS 1 + RS where =

gmb gm

0.2 0.3.

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Degenerated common-source amplier: input/output resistances

1. Input resistance: Since the gate current is zero, we have Rin = 2. Output resistance: To compute the output resistance, we short the input source, connect a test current source itest at the output and measure the resulting voltage across it vmeas .

+ vgs

iout gm vgs ro RS gmb vbs id + RDvmeas itest

+ vsb

Since vg = 0 and vb = 0, we can simplify the schematic to,

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iout (gm + gmb )vs + vs RS iro ro id + itest RD vmeas

The output resistance is given by vmeas Rout = = RD Rdrain (1) itest where vmeas Rdrain = iout Applying KVL at the drain node, we can write vmeas = Rs iout + ro iro Applying KCL at output node, and since vs = RS iout , we can write iro = iout +(gm + gmb ) vs = iout [1 + (gm + gmb ) RS ] (3) Substituting eq.(3) in eq.(2), we have, vmeas = iout [RS + ro + roRS (gm + gmb )] (4) and thus, Rdrain = RS + ro + roRS (gm + gmb ) So the output resistance is Rout = RD [RS + ro + ro RS (gm + gmb )] (2)

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Some comments: Note that Rdrain = if we assume ro = . The resistance looking into the drain of a transistor whose source is connected to ground via a resistor RS is much larger than that of a transistor whose source is directly connected to ground. For RS = 0, we have Rdrain,nondegen = ro but for the degenerate case we have Rdrain,degen = ro [1 + RS (gm + gmb )] + RS which if ro RS , can be approximated by Rdrain,degen ro [1 + RS (gm + gmb )] Note that the resistance is 1 + RS (gm + gmb ) times bigger in the degenerate case. It is the same amount we have reduced the gain. The reason behind this factor will become clearer when we study feedback.

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Degenerated common-source amplier

In a degenerated common-source amplier we get less gain than in a non-degenerated common-source for the same value of transistor transconductance. Why would we want to use degenerated common-source amplier? Well, gain is not all that matters If we are concerned about linearity, the degenerated is a better choice (for the same value of input signal, we get a smaller gate-to-source voltage and thus our linearity approximation is better) Also the gain in a degenerated amplier can be made less process dependent than in a non-degenerated case. We saw that for 1, we can write (gm + gmb ) RS Av = 1 RD 1 + RS

depends slightly on the process and the ratio of resistors RD and RS is tightly controlled in an IC process. In contrast, the non-degenerated amplier has Av = gm RD which is depends much more heavily on process parameters.

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Discrete common-source amplier

Lets study now the implementation of a common-source amplier in a discrete environment. Typically you will not nd this circuit in practice because MOSFETS are used mostly as switches not ampliers in discrete applications.

Consider the following common-source amplier. VDD RG1 CG vin RG2 RD CD

vout

RS

CS

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Discrete common-source amplier: DC analysis

To perform the DC analysis: Kill the AC sources (i.e., short the AC voltage sources and open the AC current sources) open all capacitors (since capacitors are open circuits at DC) and we obtain.... VDD RD

RG1

RG2

RS

We already studied this circuit in Lecture 5 . . .

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Discrete common-source amplier: AC analysis

The small-signal AC model is CG vin RGGvgs RS gm vgs ro CD RD

vout

CS

Capacitors CG and CD are called a coupling capacitors. Capacitor CG AC couples the input source to the amplier input. Capacitor CD AC couples the drain voltage to the output of the amplier. (AC couples means that it lets the AC signal through) Capacitor CS is called a bypass capacitor. In practice, we consider that these coupling/bypass capacitors act like short-circuits at the signal frequency. Note: RGG = RG1 RG2

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Coupling capacitors

Why do we consider the coupling/bypass capacitors short circuits at the signal frequency? The magnitude of the impedance of a capacitor is given by 1 |ZC | = C For these coupling/bypass capacitors, we have that at the signal frequency |ZC | is much less than the resistance at the capacitor terminals, i.e. |ZC | RC

Since their impedance is much less than the impedances they see we consider them short-circuits (we will see this in the example at the end of the lecture)

Typically, a circuit has more capacitors than just coupling and bypass capacitors. For example, we will have capacitors coming from the actual transistors. How do we recognize the coupling/bypass capacitors? Generally they are pretty large (in the order of F)

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If you remove these capacitors from the circuit, the AC signal path can be broken (for example, if instead of CG , we had an open-circuit no signal would arrive to the amplier). Also, if you remove them, the AC gain generally drops (for example, if we remove CS , at the signal frequency we have a degenerated common-source amplier instead of a non-degenerated).

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Discrete common-source amplier: AC analysis

We want to perform the AC analysis at frequencies for which the coupling and bypass capacitors act as shorts. Shorting the coupling and bypass capacitors we have, vout vin RGG vgs gm vgs ro RD

This is very similar to the small-signal model for the common source amplier (with the exception of RGG ) 1. Voltage gain: Since RGG is in parallel with vin , we can ignore RGG for the analysis and then, Av = vout vin = gm (RD ro )

2. Input resistance: The input resistance is just RGG in parallel with the resistance looking into the gate of the transistor (which is innite). Rin = RGG 3. Output resistance: The output resistance is the same as for the common-source amplier. Rout = RD ro

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Discrete common-source amplier: equivalent AC model

An equivalent AC model for this amplier is: Rout vin vRin Rin Av vRin

vout

where where Av = gm (RD Rout = RD ro .

ro ), Rin = RGG and

This is a quite useful high-level model. We will make use of it when we study multistage ampliers.

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Discrete common-source amplier: Loading eects

We now consider a common-emitter amplier with non-zero source impedance non-innite load impedance VDD RG1 Rs vin CG RG2 RD CD

vout RL

RS

CS

The DC analysis is the same that when Rs = 0 and RL = . To compute the small-signal AC gain we use the equivalent AC model we derived for the ideal case(Rs = 0 and RL = ). Rs vin vRin Rin Rout Av,ideal vRin RL vout

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The gain is, vout = vin

Rin RL Rin RL Av,ideal = vin gm Rout Rin + Rs RL + Rout Rin + Rs Rout + RL

which is just vout RGG = gm (RD RL ro ) vin RGG + Rs To have a high-gain amplier one must reduce the signal lost in the input and output divider. This means high input resistance (or high RGG ) and low output resistance (or small RD ). Av =

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common-source example

Example Design the amplier in the gure to have the following characteristics: |vout /vin | 25 at intermediate frequencies load is RL = 50k output must swing 4V peak-to-peak Supply is 5V Input source has Rs = 1k Hand analysis assume n Cox = 200A/V2 , Vt = 0.75, = 0. coupling and bypass capacitors are 10F

VDD RG1 Rs vin CG RG2 RD CD

vout RL

RS

CS

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There are many ways to design this amplier. Here we just show a possible way but keep in mind that it is not the only way.

To reduce the number of components and simplify the problem, we will design the circuit with RS = 0 and no bypass capacitor CS . 1. We start by looking at the gain specication. The small-signal gain is given by, Av = gm RGG (RD RGG + Rs RL )

where we have assumed ro = . We now make two assumptions: We assume we can make RGG suciently large so RGG /(RGG + Rs ) 1 We assume we have Rout RD RL RD . RL so that

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With those assumptions we can approximate the gain expression by, 2VRD (1) Av gm RD = VGS Vt Since we also have a requirement on the swing of 4V peak-to-peak, we must have VRD 2V. This requirement together with the gain requirement imposes a limit on the eective gate overdrive (VGS Vt ). To compensate for the gain loss due to loading we will design for an absolute gain of at least 40V/V (this is arbitrary!). Then going to equation (1), we have, VGS Vt 2 2V = 100mV 40

We choose VGS Vt = 100mV. Since Vt = 0.75V, this means VGS = 0.85V. 2. Now we continue with the swing requirement. We need a swing VM = 2V. We have two limits on VM VM ID RD We need then ID RD 2V ID RD 2.9V We choose a point in the middle so ID RD = 2.5V. Now we choose a value for RD . Since we made the RL , we have RD 50k, or assumption RD equivalently RD 5k. We choose RD = 2.5k and thus ID = 1mA. VM VDD ID RD VGS + Vt

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3. Since we have the DC drain current and gate overdrive voltage, we can design the transistor dimensions. Since we assumed that the transistor is in saturation, we have, ID = k (VGS Vt )2 so k = 1mA/(0.1V)2 = 100mA/V2 . 1 W n Cox = 100mA/V2 2 L Since n Cox = 200A/V2 , this means W/L = 1000. We can choose L = 1m and W = 1000m. 4. Now, we can compute the biasing network RG1 RG2 . We made the assumption that Rs and since we have VS = 0.85V, RG1 RG2 we have, RG1 RG2 10k 0.85 RG2 = RG1 + RG2 5 Solving the two equations above we have RG1 = 58.8k, RG2 = 11.7k

The nal circuit becomes:

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5V 58.8k 1k CG vin 11.7k 2.5k CD

vout 50k

Now we need to check that the design requirements are met. VG is just given by a voltage divider RG1 RG2 and it is exactly 0.85V Then VGS Vt = 100mV and the drain current (assuming saturation) is W (VGS Vt )2 = 1mA L Then the drain voltage is ID = kn VD = VDD ID RD = 5V 1mA2.5k = 2.5V The signal swing at the output is VM = min{1mA2.5k, 5V 2.5V 0.1V} = 2.4V which is larger than the required 2V

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The gain is RGG (RD RL ro ) RGG + Rs 2mA 10k (2.5k 50k) = 43.3V/V = 0.1V 11k which meets the requirements Av = gm

The instantaneous voltages at the transistor nodes for vin = 10mV are: Gate voltage vG = VG + vin Source voltage Drain voltage vD = VD + Av vin = 2.5V 433mV sin(t) RGG = 0.85V + 9.1mV sin(t) RGG + Rs vS = 0

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common-source example: coupling capacitors

Lets compute the magnitude of the coupling capacitors at lets say f = 1kHz 1 1 = 16 |ZC | = C 2 103 10 106 Note that this is pretty small! For example, capacitor CG is in series with Rs = 1k so at f = 1kHz it makes sense to assume that CG acts like a short. To be precise, capacitor CG sees a resistance across it RCG = Rs + Rin . (We will see this in a couple of weeks) Note that at some low frequency (for example f = 0.01Hz), the capacitor has a large impedance so we cannot consider it a short-circuit. The point here is to realize that after some reasonable frequency (low-cuto frequency) these coupling/bypass capacitors can be considered shorts because their impedance is much smaller than the impedances in the circuit. In approximately two weeks we will learn how to compute this low-cuto frequency. For now, just assume they are shorts for the frequencies of interest in the AC analysis.