MSc System on Chip ELEC6097 Analogue Coursework

Design of a CMOS Two Stage Unbuffered Operational Amplifier with High Unity Gain Bandwidth
Ahmed F. Rahim, Electronics and Computer Science, University of Southampton
II.DESIGN AND ANALYSIS Abstract The following report explores the design and implementation of an unbuffered two stage CMOS operational amplifier using Cadence IC Design Suite 5141. A 350 nm CMOS process node technology from Austria Microsystems (AMS) was used all throughout the design and the physical implementation phase. The design aims to meet the following criteria: Open Loop Gain Gain Bandwidth Product Isupply (2Ibias +Idiff + Iout) Phase Margin Slew Rate (charging) Slew Rate (discharging) > 80 dB > 15 MHz < 350 uA > 50 > 20 V/us > 20V/us a) Circuit Design, Simulation and Analysis 1) Understanding Process Parameters: It has been reported widely that the square law model used in traditional texts do not pose an accurate representation of the parameters and their inter-relationships at the submicron level. To investigate this point, a diode-connected NMOS (in saturation mode) with (a) increasing V gs and (b) increasing length was used as a test circuit. The following results were obtained: Parameter Increasing Vgs VDsat Vth gm gds ro Beff ID Ron Cgg Increase Slight Increase Increase Constant Decrease Decrease Increase Decrease Fairly Constant Increasing Length with Width kept constant Increase Decrease Decrease Decrease Increase Decrease Decrease Increase Increase

In addition to the above, the design aimed to achieve a high Gain-Bandwidth product while meeting all of the other above mentioned specifications. I. INTRODUCTION HE opamp discussed in this report, consists of a PMOS differential input pair and a common source output stage, while a Beta Multiplier current mirror was used to provide the bias current. A Miller capacitance based compensation technique was also employed to ensure stability at higher frequencies. The schematic design and testing was performed through the efficient use of Cadence Spectre Analog Design Environment, which included the following: Acquiring a better understanding of the process parameters at the sub-micron level.

Understanding the different device parameters and the trade-offs that need to be addressed in order to meet the performance specifications. Circuit Design and simulation (i.e. AC, DC and Transient analysis) The efficient use of parametric sweeps to fine tune the component values. The implementation phase included the following: Physical Layout. Design Rule (DRC) and Layout vs Schematic (LVS) Check. Analogue Extraction and Post Layout simulation.

MSc System on Chip ELEC6097 Analogue Coursework

2 The methodology followed for designing the Bias Current circuit is as follows: The length of the NMOS was chosen to be 1.05 um (a multiple of the minimum length that the process technology allows i.e. 0.35 um). Using the circuit in Figure 2, width of the NMOS was varied parametrically to achieve a V DSat = 165 mV 170mV (5% of VDD). For sub-micron processes, this should be enough to ensure that the NMOS is always turned on with a VGS value of less than VDS in order to ensure operation in saturation mode. The gain of an opamp depends on the gm (transconductance) and ro (output resistance, also 1/gds) of the transistors. Using DC Analysis of the EDA tool, the values of the were chosen as such that gm*(1/gds) for each NMOS and PMOS pair is greater than 250. A gain of ~ 250 from both stages would ensure an open loop gain of 80dB. The same process was followed for finding the correct width of the PMOS fulfilling the same parameters. The circuit was then constructed using the same topology as shown in Figure X. The width of M2 was set to be 4 times of that of M1 and R was set at an initial value of 27.2 K (as R = ID1 / VDSat). Applying a parametric sweep from 15 K to 30K, R was selected to be 20.37K which gives a value of 5 uA and 5.3 uA for ID1 and ID2 respectively. The final values for the Bias Circuitry is as follows: Device Model Valu Dimension(W/L) e M1 M2 M3 M4 R nmos4 x nmos4 x pmos4 x pmos4 x 1.7u/1.05u 6.8u/1.05u 8.5u/1.05u 8.5u/1.05u Fingers/ Bends 2 4 4 4 5

It is clearly seen from the above findings that certain parameters (e.g. Vth) do not abide by the usual norm. The threshold voltage is seen to vary with Length and Gate Voltage which is not usually taken into account by the square law model. Going forward, all tests and analysis used in the subsequent sections were ensured to take the DC operating point values (generated by the EDA tool) was used as the prime source. 2) Beta Multiplier Bias Circuit: The Beta Multiplier circuit provides a reference current against which the subsequent gain stages of the opamp are biased. A basic circuit schematic is shown in the diagram below.

rpolyh 20.37 28.05u/2u c k

Illustration 1: Beta Multiplier Bias Circuit

If the length of all MOSFETs are kept the same and the width of M2 is K times larger than M1, it can be shown that the current, Ibias = (2 / Rbias2 ) [1 - (1/K)]2. In other words, K and R are the design variables that can be tuned to determine ID. Since, the design specification asks for a high slew rate (which prefers a high tail current through the differential pair), it was decided the bias circuit should consume as little current as possible while simultaneously providing a good current resolution. A bias current of ~5 uA was selected to be appropriate for fulfilling this requirement.

MSc System on Chip ELEC6097 Analogue Coursework 3) PMOS Differential Pair, Common Source Stage & Miller based Compensation Network: The complete schematic of the opamp was constructed as shown in the figure below. M1 M2 M3 M4 R MP1 MP2 nmos4 nmos4 pmos4 pmos4 pmos4 pmos4 x x x x x x x x x x x 1K 500f 1.7u/1.05u 6.8u/1.05u 8.5u/1.05u 8.5u/1.05u 28.05u/2u 85u/1.05u 340u/1.05u 42.5u/1.05u 42.5u/1.05u 8.5u/1.05u 8.5u/1.05u 68u/1.05u 2u/2.35u 39u x 39u 2 4 4 4 5 8 8 4 4 4 4 4 5 x

Illustration 2: Two Stage Opamp Schematic

rpolyhc 18.7K

Mdiff1 pmod4 Mdiff2 pmos4 MA1 MA2 MB Rnull CC nmos4 nmos4 nmos4 rpolyhc rpolyc

The selected values also ensure that the following balance condition was fulfilled: W MP2/WMP1 = 2 x WMA1/WMB. 4) Simulation and Analysis: The final design was simulated using the following test circuits using a DC Dual Voltage Supply of +1.67V and -1.67V. For the slew rate, a DC pulse source of 1V with a period of 2 us was used as the input. The following results were achieved: Open Loop Gain Gain Bandwidth Product Isupply (2Ibias +Idiff + Iout) Phase Margin Slew Rate (charging) Slew Rate (discharging) =87.23 dB =94.04 MHz =12+65.4+267.9 ~ 345 uA =180 96.5 = 83.5 =21.5 V/us =84.4 V/us

All transistors have the same length of 1.05 um and width of each individual transistor was chosen to give a differential pair tail current (I diff) and output stage current (Iout) of 100 uA and 200 uA in order to ensure a current consumption of < 350 uA. The R null and CC of the Miller compensation network was given an arbitrary value of 1K and 1pF respectively. A first dry run using the test circuits below resulted in the following results: Open Loop Gain Gain Bandwidth Product Isupply (2Ibias +Idiff + Iout) Phase Margin Slew Rate (charging) Slew Rate (discharging) =88 dB =97.4 MHz =10 + 107 + 223 = 340 uA =180 90 = 90 =18 V/us =77 V/us

It is evident from the test results that the design does not meet the specification in terms of slew rate (charging). The slew rate (charging) depends on I out and hence a higher current in the output rail would give a better slew rate. As a result, the transistors in the differential gain stage and the output stage were adjusted in width to have an Idiff and Iout of 50 uA and 250 uA respectively. The Miller Capacitance was reduced to half of it's original value to keep the same value of I diff/(CC+Cgd+CL). Finally, the value of R bias was parametrically sweeped to fine tune the current in each rail in order to meet the design goals. The final schematic design was constructed using the values given below: Device Model Value Dimension(W/L) Fingers/ Bends

The results are very encouraging proves that the decisions taken during the design phase were correct. As a result, all the specifications have been fulfilled.

MSc System on Chip ELEC6097 Analogue Coursework

b) Physical Implementation and Post Layout Simulation 1) Floor planning and Physical Layout: The floor planning phase is important and makes the layout (a) less prone to DRC violations, (b) allows the designer to pla ce the PMOS and NMOS devices efficiently in order to reduce the length of interconnects and finally, (c) allows the designer to decide in advance on the number metal layers to be used. A diagram of the floorplan was provided in the figure below.

Illustration 3: Gain, Unity Gain Bandwidth and Phase Margin Measurement Illustration 6: Layout Floorplan
The floorplan also ensures the following: The Miller compensation network and the bias resistor are kept away from the active region. Only one layer of metal should be enough for most interconnects. However, Metal 2 connections would be required to connect the Miller Capacitor to rest of the circuit due to its built-in guard ring. The matching MOS pairs (the bias network and Differential pair) were kept next to each other in the same orientation. The physical implementation process is described below: Using PCells, all the components were placed as shown in the floorplan. All Metal 1 connections were then made. This was made simple by activating only one layer at a time. Next, all Poly and Metal 2 connections were made.

Illustration 4: Slew Rate Measurement @ Rising Edge

Illustration 5: Slew Rate Measurement @ Falling Edge

MSc System on Chip ELEC6097 Analogue Coursework 2) DRC, LVS and Analogue Extraction a) DRC: The first run of DRC reported 44 errors due to minimum distance violation. No critical Hot nwell or Latchup errors were encountered due to following good layout practices. The errors were then corrected and the next DRC run reported only 2 errors. This was due to the floating guard ring of the Miller Capacitor. Once this was connected to the vssa! rail, the final DRC run reported no errors!

Illustration 7: Layout with all layers disabled except Metal 1

The NTUB, NPLUS, PPLUS and substrate taps were put in next. The PMOS and NMOS networks were placed very close to the vdda! and vssa! metal rails respectively. This helps to avoid putting unnecessary no. of substrate taps in the active region in order to avoid Latchup and Hot nwell errors in the DRC checks. Finally the input and outputs pins were placed. All power input pins were assigned to use Metal 1 contacts whereas all signal in/out pins (v+, v- and vout) use Metal2 contacts. All metal lines were desilgned to be of 1 um width as this gives a negligible IR drop across the various interconnects. A well compact design of 200 um x 36.50 um was achieved.

Illustration 9: DRC Report

Illustration 8: Final Layout

MSc System on Chip ELEC6097 Analogue Coursework b) Extraction without Parasitics: The design was then extracted with no parasitic components and a LVS check was performed. The extraction process identifies each component of the layout and places a schematic symbol next to it. One important aspect of this Illustration 11: LVS is the fact that the extractor identifies the p-substrate and Check withou the n-well as a reverse biased Rewiring diode. This is in line with semiconductor theory and indicates that the substrate and the well taps are placed correctly to ensure that the n-well is always at a higher potential than the p-substrate bulk. LVS: LVS check matches the extracted layout with the schematic. Any unconnected nodes, device mismatches or missing components are reported after the LVS run. The first LVS run did not end in success and two mismatches were reported. The first mismatch was due to a length mismatch of the resistor used in the Miller compensation network. This was rectified by changing the length of the resistor in the schematic while keeping the same resistance value. The second error was more critical in Illustration 10: LVS nature as it indicates of report merged nets. Upon further analysis, it was revealed that this error is reported when the LVS checker had to join two nets in order to match the schematic with the layout. The LVS check was then re-run but with the rewiring option unchecked. This ensures that the LVS checker would not attempt to automatically fix or rewire any unconnected nodes. This had revealed a missing connection between the NMOS of the output stage and the NMOS of the differential stage. This issue was soon rectified and this time, the LVS check reported of a 100% match!

6 c) Analogue Extraction with Parasitics: Upon the successful run of the LVS check, the circuit was extracted with parasitic capacitances. This layout is very similar to the one extracted previously. However, this time the extractor includes all the capacitances due to interconnects, n- and p-diffusion, n-well and p-substrate. When used in simulation this model would provide a better understanding of how the design would perform in practice. The parasitic capacitances vary between 0.8 fF and 110fF, which is well within acceptable range. It is important to mention that the process technology used for this design (AMS CMOS 0.35u C35B4) does not allow any provision for parasitic resistances to be extracted. This, in practice, would have yielded more accurate simulation results. d) Post Layout Simulation: The post layout simulation phase compares the schematic design with the extracted layout. For this to happen, a new cell view was created with the tech circuits as shown in the figure below. The hierarchy editor was then configured to use the schematic for the first and the extracted analogue layout as the second device under test.

Illustration 13: Test Circuit for measuring Slew Rate

Illustration 14: Test Circuit for measuring Gain, Phase Margin and Unity Gain Bandwidth Illustration 12: Extraction with Parasitics

MSc System on Chip ELEC6097 Analogue Coursework On running the test for slew rate and current consumption, the following results were achieved: Slew Rate (Rising Edge): 23.7 V/us Slew Rate (Falling Edge): 89.2 V/us Current Consumption: 362.34 uA Compared to the schematic model, a ~4% increase in current consumption was achieved. The higher current is suspected to occur due to more accurate modeling of the extracted layout. The extracted parasitic capacitances require charging and discharging thereby consuming more current. Also, the wide metal interconnects may offer lower resistances than what was accounted for in the schematic model.

Illustration 17: Slew Rate @ Rising Edge

Illustration 15: Current Consumption for Layout

Illustration 18: Slew Rate @ Falling Edge

The following results were achieved from the extracted layout:

Illustration 16: Current Consumption for Schematic

The high slew rate achieved was due to the slight increase in current consumption since these two parameters vary proportionally. Even if the current is assumed to be 345.5 uA (what was achieved in the schematic model) and the slew rate (rising edge) is reduced by the same amount of the increase in current (~4%), an approximate slew rate of 22.5 V/us would have been achieved. This still would have exceeded the specified minimum limit. Overall, the achieved results were good and within acceptable limits.

Open Loop Gain (in dBs) at low frequencies: 86.528 dB Phase Margin: 180 97.78 = 82.22 Gain Bandwidth: 89.35 MHz The Gain-Bandwidth Product has maintained the same level, but was slightly decreased that what was achieved from the schematic model (i.e. ~ 90 MHz). The reason for the decrease is suspected to be the parasitic capacitances which increases the value of the Miller capacitance. Since, Gain Bandwidth is inversely proportional to the Miller Capacitance, it decreases slightly. The Phase Margin and the Open Loop Gain were slightly reduced but are well above the specified level. Overall, the results achieved were very encouraging.

MSc System on Chip ELEC6097 Analogue Coursework

Illustration 19: Measurement of Gan, Unity Gain Bandwidth and Phase Margin for the extracted layout
II.CONCLUSION The tasks undertaken through this report details the full custom design flow of an analog IC from Schematic Entry to Physical Implementation. This report further goes on to show that good engineering practices and efficient handling of the EDA tools can result in a very good design which meets most specifications from start till the end. Furthermore, this exercise can be used as a guideline for beginners as an introduction to Analogue IC Design. ACKNOWLEDGMENT The author would like to thank Dr. Ke Li for his continued support throughout the design, layout and testing phase of the coursework. BIBLIOGRAPHY [1] [2]
B. Razavi. Design of Analog CMOS Integrated Circuits. McGraw Hill, New York, 1999. Allen and Holberg, CMOS Analog Circuit Design, 2nd Edition, Oxford, 2002