Exercise 1

A Simple Program

Our first program adds two numbers together (both of which are found in main memory), storing the sum in memory. Table 1.1 lists an assembly language program to do this, along with its corresponding machinelanguage program. The list of instructions under the Instruction column constitutes the actual assembly language program. We know that the fetch-decode-execute cycle starts by fetching the first instruction of the program, which it finds by loading the PC with the address of the first instruction when the program is loaded for execution. For simplicity, let's assume our program is loaded starting at address 100 (in hex). Table 1.1: A Program to Add Two Numbers Instruction Binary Contents of Hex Contents of Memory Address Memory Load Add 104 105 0001000100000100 0011000100000101 0010000100000110 0111000000000000 0000000000100011 1111111111101001 0000000000000000 1104 3105 2106 7000 0023 FFE9 0000

Hex Address 100 101 102 103 104 105 106

Store 106 Halt 0023 FFE9 0000

The list of instructions under the Binary Contents of Memory Address column constitutes the actual machine language program. It is often easier for humans to read hexadecimal as opposed to binary, so the actual contents of memory are displayed in hexadecimal. This program loads 002316 (or decimal value 35) into the AC. It then adds the hex value FFE9 (decimal -23) that it finds at address 105. This results in a value of 12 in the AC. The Store instruction stores this value at memory location 106. When the program is done, the binary contents of location 106 change to 0000000000001100, which is hex 000C, or decimal 12. Figure 1.1 indicates the contents of the registers as the program executes.

Figure 1.1: A Trace of the Program to Add Two Numbers The last RTN instruction in Part c places the sum at the proper memory location. The statement "decode IR[15-12]" simply means the instruction must be decoded to determine what is to be done.

H.W a)Write a program that can shifting the contents of register R1 and R2 5 ranks left and right
respectively then add the content of R1 and R2 , put the resultant on R3? b) Trace the execution of each instruction of your program inside microprocessor?

Exercise 2
3

Resources conflict Tracing instructions execution inside five-stage pipeline by using Gantts chart
Consider the execution of the following sequence of instructions on a five-stage pipeline consisting of IF, ID, OF, IE, and IS. It is required to show the succession of these instructions in the pipeline by using Gantts chart? Assume the architecture provides a means to fetch data and instructions in parallel. This can be done with separate instruction and data paths

I1 I2 I3 I4 I5

Load Load load SL Add

5, R3; 4, R1; 6, R2; R3; R4,R1,R2

R3 R1 R2 R3 R4;

5; 4; 6; SL (R3); R1+R2;

IS IE I1 OF I1 I2 ID I1 I2 I3 IF I1 I2 I3 I4 T1 T2 T3 T4

I3 I4 I5 I3 I4 I5 I3 I4 I5 I3 I3 I4 T5 I4 I4 T5 T5 T6 T7 T8 T9 T10 T11 T12 T13

I1 I2 I2

H.W
a) Write a program that can add two numbers which are transferred to registers R1, and R2 after shifting their contents to the left one rank only , The resultant will be on register R3? b) Calculate the final product c) Calculate the total execution time when the program instruction have been executed sequentially? d) Trace the written program inside 5 stages pipeline by using Gantts chart?

Exercise 3 Data Dependency Tracing instructions execution inside five-stage pipeline by using Gantts chart
Consider the execution of the following sequence of instructions on a five-stage pipeline consisting of IF, ID, OF, IE, and IS. It is required to show the succession of these instructions in the pipeline by using Gantts chart? Assume the architecture provides a means to fetch data and instructions in parallel. This can be done with separate instruction and data paths

I1 I2 I3

Load load Add

4, R1; R1 6, R2; R2 R4,R1,R2 R4;

4; 6; R1+R2;

IS IE OF ID IF I1 1

I1 I2 2

I1 I2 I3 3

I1 I2 I1 I2 I2 nop nop I3 I3 4 5 6 7

I3 I3

H.W In the following sequence of instructions

a) Calculate the total execution time when the program instruction have been executed sequentially if the processor worked with 1GHz frequency and each stage on instruction execution takes 2 clock cycles? b) Trace the written program inside 5 stages pipeline by using Gantts chart? c) Calculate the total execution time with processor has pipe line architecture? d) calculate the speed up achieved by using pipe line technique

ercise 4 Conditional Branching

5

Tracing instructions execution inside five-stage pipeline by using Gantts chart

Consider the execution of the following sequence of instructions on a five-stage pipeline consisting of IF, ID, OF, IE, and IS. It is required to show the succession of these instructions in the pipeline by using Gantts chart? Assume the architecture provides a means to fetch data and instructions in parallel. This can be done with separate instruction and data paths

IS IE OF

ID IF

I1 I1 I2 I1 I2 I3 1 2 3

I1 I2 I1 I2 I2 I3 I4 4 5 6

I3 I3 I4

I4 I5 I3

I3 I4

I4 I5 I3

I3 I4

I4

I3 I4 I5 I3 I4 I5 I3 I4 I4 I5 I3 I4 I5 I3 I4 I5 I5 I6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

IS IE I5 OF I5

I3 I3 I3 I3 I4 I4 I4

I4 I5 I5 I5 I3 I3 I4 I3

I3 I4 I4

I4 I5 I5 I5 I3 I3 I4 I3

I3 I4 I4

I4 I5 I5 I5

ID IF

I6 I6 I7 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

IS I6 IE I6 OF

I7 I7 I7 I7

ID IF

69 70 71 72 73 74

H.W Trace the above program inside 5 stages pipeline by using Gantts chart when the starting
setting value in R2 is 7?