Section 1.

1 - Switched-Capacitor Basics

1 Discrete-Time Applications
This chapter presents the basic principles and some practical aspects regarding the design of switched-capacitor (henceforth SC) circuits, with special emphasis on their filtering applications.

1.1 Switched-Capacitor Basics

Switched capacitor (SC) circuits are sampled-data or discrete-time systems for analog signal processing successfully constructed using integrated circuit MOS technologies [Mosc84, Alle84, Greg86, Tsiv85]. They emerged from active RC networks as a solution for two main problems that these present for monolithic implementation: inaccurate RC products and large R and C values requiring prohibitive chip area. SC techniques achieve integrated circuits with accurate simulated resistors in a small area, with programmability and tuning capabilities, and are compatible with digital circuits. Generally speaking, there are three important factors to take into account when designing SC circuits: a) Design methodology to be adopted, b) Restrictions imposed by the technology, and c) Method used to derive discrete-time systems from the continuous-time domain. Some of these aspects have been treated in previous chapters; the remainder, in particular those relating to filters, will be considered here. Practical SC circuits are composed of switches, capacitors, and op-amps. Switches are the onoff type, controlled by periodic signals called clocks. Typically, clocks in a system are assigned to phases of a principal clock with a period T. That is, a time interval T is divided into n subintervals, known as clock phases. A clock with period T and four phases (1-4) is shown in Fig.1.

T 1
1 2 3 4

(nT-T)

nT (n+ 1 )T 4

(n+ 3 )T 4

Fig. Four phases clock signal Figure 5-1. 1 : Four phase clock signal

A switch will be closed when the clock phase controlling it assumes the high value; otherwise it is open. In circuits using several phases, part of the switches are closed and part are open during an interval T, thus a distinct equivalent circuit is obtained during each clock phase. The ideal operation of the network may be analyzed by replacing closed (open) switches with short (open) circuits.

Chapter 1 - Discrete-Time Applications

i1

1 (S1)

2 (S2) C

i2

(n 1 )T 2

nT

1 (n+)T 2

V1

V2

(a)
I1 aver. R=T/C I2 aver.

i1(f) V1 V2 i2(f)

(c)

(b) Fig. 2. SC realization of a two terminal resistor. a) Parallel capacitor SC structure. b) Clocks and
current waveforms. c) Equivalent average circuit

To understand the basic principles of SC circuit operation, let us consider the simple circuit in Fig.2a. There, capacitor C is periodically switched between two voltage sources: v1 and v2. Considering ideal switches, the circuit operates as follows: during 1 (i.e., 1 high, nT t ((n + 1/ 2)T), S1 (S2) is closed (open) and capacitor C is charged to v1; hence the charge stored in C varies accordingly during this interval:
q 1 = C [ v 1 v C ( nT

)]

(1)

where vC(nT --) represents the initial voltage in C before closing S1. This charge flows from the voltage source v1 as a sharp current pulse, i1(t), shown schematically in Fig.2b. Next, during 2[(n + 1/2)T variations in C are:

t (n + 1)T)] the capacitor is charged to v2; thus the charge

q 2 = C v v n + 1 T -2 C 2

(2)

where vC((n + 1/2)T ) is the voltage in C before S2 is closed, and thus equals the final value achieved during the previous phase; that is, vC((n + 1/2)T -)=v1. Hence, a charge q2 = C(v2 - v1) now flows from the source v2 as a sharp current pulse i2(t). If C is alternately charged to v1 and v2, an average equivalent current can be defined as the charge flowing in each clock period T divided by T. Assuming the polarities indicated in Fig.2a and that v1 and v2 do not change with time, the average currents will be:
q 1 q 2 C ( v1 v2 ) I 1aver = I 2aver = -------- = ----------- = -----------------------T T T

(3) It can be deduced from (3) that the SC structure in Fig.2 usually behaves as a continuous resistor R = T/C connected between sources v1 and v2 (Fig.2c). Table 1 presents a summary of other SC structures available for resistor simulation. All of these structures can be analyzed as previously explained. The equivalent R value for each case is included in this Table.

Section 1.1 - Switched-Capacitor Basics

SC structure

Circuit

i1

i2
1 C 2 +

Parallel or toggle.

T C

V1

V2

Series.
V1 1 C 1 2 V2

T C

Bilineal.

V1 C 2 1

V2

T 4C

1 +

1 +

Stray-insensitive positive R.

V1 1 +

V2 2 +

T C

Stray-insensitive negative R.

V1

V2

-T C

Table 1 SC structures simulating linear resistors.

It must be pointed out that whenever v1 and v2 change with time, I1aver I2aver and the SC in Table 1 will generally not be equivalent to a two terminal resistor. However, when T is small enough so that v1(t +T) and v2(t + T) do not differ significantly from v1(t) and v2(t) respectively, the resistor equivalence holds. In other words, the SC structures in Table 1 simulate linear resistors if v1(t) and v2(t) have a frequency much smaller than the clock frequency (f << fc = 1/T), or they are sampled and held for the necessary time interval. The simplest design technique for SC circuits is to replace all resistors in an active RC network with equivalent SC structures. Hence, time constants like = RC1 will be transformed into equivalent time constants proportional to C1(T/C). This approach solves two main problems encountered

Chapter 1 - Discrete-Time Applications

in active implementation: a) Largeresistors can be obtained with small capacitors by using the appropriate clock frequency fc = 1/T. For instance, for C = 1pF and fc = 100 kHz, an equivalent resistor of 10M can be implemented. b) Time constant accuracy now depends on the clock frequency accuracy (very precise when crystal generators are used) and on the capacitor ratio accuracy (0,1%). In spite of these advantages, one of the most important drawbacks of SC circuits is the existence of stray capacitances related to capacitors, switches, and op-amps in MOS technology. Generally the success or failure of an integrated SC circuit depends on the influence of these stray parasitics. As an example of stray effects, let us once again consider the circuit in Fig.2a. In monolithic MOS capacitors there are two unavoidable nonlinear parasitic capacitances associated with C: the capacitance of the top plate, Ct, and of the bottom plate, Cb. The value of Cb depends on the area of C, and may be as much as 10% of C; however, Ct is smaller and independent of the C value. If the bottom plate of C in Fig.2a is connected to both switches at its top plate to ground, the actual equivalent resistor will be T/(C + Cb) instead of T/C. Thus, the parasitics affect both the accuracy and the linearity of the circuit. [Hasl81] showed that SC circuits can be made insensitive to stray capacitances if they meet the following topological constraints: a) The resulting equivalent circuit in each clock phase contains no nodes other than input voltage source, op-amps input and output, and ground nodes. b) A capacitor terminal is never switched from a low impedance node in a phase to a virtual ground (high impedance node) in another phase and viceversa. Bearing this in mind it is easy to realize that if any v1 or v2 terminals of the circuits in Table 1 are connected to the virtual ground in an opamp, only the last two structures lead to stray-insensitive resistor simulation. In addition to parasitic capacitors, other nonidealities must be taken into account in SC circuits, mainly those related to real MOS switches and nonideal op-amps. Since the analysis of SC circuits considering these effects is quite complicated, we will assume only ideal elements in this chapter. Some general considerations for practical SC realizations with nonideal components will be made at the end of the chapter. As shown, for time variants v1 and v2, the simplest approach to design SC circuits using oneby-one resistor replacement in a continuous-time active prototype requires high ratio between clock and input signal frequencies. We will see how this ratio effects the accuracy of the simulation depending on the realization chosen and the circuit in which it is included. In any case, this approach always leads to approximate filter design. Hence, we will introduce alternative design methodologies which allow exact sampled-data realizations of filtering functions.

1.2 Description of SC Circuits in the Time and Frequency Domains

An important aspect to bear in mind when analyzing SC circuits is that they are time-variant systems that process continuous time signals, which are usually of the sample-and-hold type. The time-variant nature of SC circuits is the result of the switching action of clock signals which alternately change the circuit topology as the switches open and close. The resulting circuits are interrelated, where the state of one determines the initial conditions for another. The analysis of SC networks is mathematically complex when no restrictions are imposed on the switching pattern or the form of the input signals. [Tsi83] introduced analysis techniques to derive general input-output difference equations, as well as the frequency-domain descriptions of SC networks. In this section we will not go into the detail of such analysis techniques, but rather

Section 1.2 - Description of SC Circuits in the Time and Frequency Domains

remark on those aspects that are important for correct interpretation of the circuits described herein. The fundamental point in deriving SC circuit functions is the nature of their input and output signals. For the time domain description of SC circuits, branch voltages and injected charges in capacitors are used as variables. Injected charge refers to charge variation q(t) in a capacitor during a specified period of time, which satisfies the charge conservation principle expressed as:

charges injected in time slot Ik(nT +k, t)

or

charges stored in the C at the instant t

charges stored in C at the instant nT + k

( q ) ( k ) ( t ) = C [ v ( t ) v ( nT + k ) ]

(4)

where v is the voltage between both terminals of the capacitor C. Since charge variations are used instead of currents, Kirchhoffs Current Law must be written in terms of q as:
n

( q ( t ) )
j=1

= 0

(5)

A simplified representation of an SC circuit is as a discrete-time system whose input and output are sampled during the same sampling period. The samples are viewed as simple discrete sequences, regardless of the exact point within each period they appear. Thus, the general difference equation describing the network is expressed as:
N M

ai yD
i=0

(n i) T =

bi xD
i=0

(n i) T

(6)

where xD(.) and yD(.) represent the input and output digital sequences, respectively. Applying the ztransform to the above equation results in the following transfer function H(z):
M

YD ( z ) H ( z ) = -------------- = i = 0 -----------------------N XD ( z ) i ai z
i=0

bi z

(7)

where the equality z = e can be used to mathematically relate the z-transform for discrete-time systems to the Laplace transform for continuous-time systems. Thus, the discrete-frequency response may be evaluated using z= ejwT, which implies evaluation of z-plane in the unit circle. When the exact sampling instants are considered for either input or output, the general equation describing the network is:
N M

sT

a1 y ( nT iT + 2 )
i=0

b1 x ( nT iT + 1 )
i=0

(8)

where only one sample per period x(nT + 1) and y(nT + 2) is considered. Now, the z-transform is not directly applicable to (8). However, analysis using phasor concepts and defining the symbol z = es associated to time delay , obtains the following transfer function [Tsiv83]:

Chapter 1 - Discrete-Time Applications

M i b1 z ( 1 2 ) -------------------T i=0 ------------------------z N i a1 z

H(s) =

(9)

i=0

which evaluated in s = jw gives the frequency response H(jw) of the circuit. A complete description of any system response almost always requires knowing the waveform between sampling instants. In this sense, the two transfer functions (8) and (9) are not complete descriptions. However, in most practical SC applications the samples at instants nT + of the output remain constant during a whole switching period T. In these cases, the low-pass filtering effect of the zeroorder holder must be introduced at the output. The transfer function should then be modified by the product of the sinc function. Thus, when there is no continuous path between input and output, the generic response description is obtained from (9) as:
wT sin -----2 --------------wT -----2

H ( jw ) = H ( jw )H SH ( jw ) = H ( jw )e

jwT --------2

(10)

Note that if the input is also a sampled-and-held signal for the same switching period T, the low-pass filtering effect also appears at the input spectrum. The transfer function in the z-domain, H(z) is then enough to describe the circuit. More complex descriptions are required if continuous paths exist between input and output. Details regarding these cases are available in [Tsiv83].

1.2.1 Switched-Capacitor Integrators

It is well known that integrators are basic components in active RC filters. These circuits also serve as building blocks for higher-order SC filters. SC integrators are derived from continuoustime active integrators by replacing resistors with SC structures. Figure 3 shows the standard parasitic-free lossless inverting and noninverting integrators (Fig.3b and c, respectively) derived from the Miller integrator (Fig.3a). As the transfer function describing SC circuits depends on the sampling patterns, two output are drawn as dashed lines, indicating that the output can be sampled at the end of 1 (labelled vo(1)) or at the end of 2 (labelled vo(2)). To analyze these circuits let us assume that: a) Switches are controlled by two nonoverlapping clock signals 1 and 2 with approximately 50% duty cycle. b) Input voltage vi is instantaneously sampled at the beginning of phase 2 and remains constant during the next phase: vi[(n +1/2)T] = vi(nT). (For simplicity, in the following we will use v(n) instead of v(nT) to indicate the value of the sample at instant t=nT.) First consider the integrator in Fig.3b. The equivalent circuits for both phases are presented in Fig.4. During 1 both terminals of C1 are grounded; thus C1 is discharged. Since C2 and the opamp are isolated, the output vo does not change. During 2, the current flows through C1 connecting vi and virtual ground, and through C2. Thus, the charges of both capacitors C1 and C2 change. The charges injected into C1 and C2 during 2 can be obtained applying the charge conservation prin-

Section 1.2 - Description of SC Circuits in the Time and Frequency Domains

ciple:

q1 ( n ) q2 ( n )

1 = C 1 v i ( n ) v C n -- 1 2 1 = C 2 v o ( n ) + v o n -- 2

(11)

(12)

where vC1(n - 1/2) and vo(n - 1/2) are the voltage in C1 and at the output node, respectively, during the previous 1 phase. Analysis of the equivalent circuit in Fig.4a results in:
1 v C n -- = 0 1 2

(13)

C2 R vi

_ +
(a)
v0

Vo(s) 1 H(s)= = V1(s) sRC2

C2 2 vi 1 1 C1 2 1
(1)

_ +

v0 v0 2
(2)

V0 (z)= V0 (z)=
(2)

(1)

c1 z-1/2 (2) V(z) c2 1-z-1 i c1 1 (2) (z) -1 Vi c2 1-z

v0

(b)

C2 2 vi 1 2 C1 1 1
(1)

_ +

v0 v0 2
(2)

V0 (z)= V0 (z)=
(2)

(1)

c1 z-1/2 (2) V(z) c2 1-z-1 i c1 z-1 (2) V(z) c2 1-z-1 i

v0

(c)

1 2

t
(n-1)T 1 (n ) 2 nT

Fig. 3. a) Continuous-time Miller integrator.,b) Parasitic-free inverting BE (Vo(2)) or LDI (Vo(1)) integrator.c) Parasitc-free noninverting FE (Vo(2)) or LDI (Vo(1)) integrator.

Chapter 1 - Discrete-Time Applications

C2 C1

_ +
(a)

vi v0

q1 C1

q2

C2

_ +
(b)

v0

Fig. 4. Equivalent circuits for the inverting integrator during a) 1 and b) 2

1 v o n -- = v o ( n 1 ) 2

(14)

Substituting (13) and (14) into (11) and (12), and using the equivalent Kirchhoffs Current Law at the virtual ground node, q1 - q2 = 0, we obtain
C1 v o ( n ) = v o ( n 1 ) ----- i ( n ) -v C2

(15)

Equation (15) is the first-order difference equation describing the circuits operation. Applying the z-transform to Eq. (15), results in the following transfer function:
( 2, 2 )

Vo ( z ) C1 1 ( z ) = ---------------- = ----- --------------(2) C2 1 z1 Vi ( z )

(2)

(16)

where the superscript (2,2) means that both input and output signals are sampled at the same clock phase 2. Note that the same vo is available during the next 1 phase; thus, sampling vo in this phase introduces a half period delay, resulting in the following transfer function:
2 Vo ( z ) C1 ( 2, 1 ) z HI ( z ) = ---------------- = ----- --------------(2) C2 1 z1 Vi ( z ) (1) 1 --

(17)

which confirms that transfer functions of SC circuits depend on the switching pattern. The noninverting integrator in Fig.3c can be analyzed in a similar manner. There, at the end of 2, capacitor C1 is charged to vi(n) and capacitor C2 does not change the charge acquired in the previous phase 1. Thus, during 2,
v C1 ( n ) = v i ( n ) 1 v o ( n ) = v o n -- 2

(18) (19)

Applying the charge conservation principle at the virtual ground node of the opamp during the next 1 we have,
1 q 1 n + -- = C 1 v i ( n ) 2 1 1 q 2 n + -- = C 2 v o n + -- + v o ( n ) 2 2

(20)

(21)

Thus q1 - q2 = 0 gives:

Section 1.2 - Description of SC Circuits in the Time and Frequency Domains

C1 1 v o n + -- = v o ( n ) + ----- v i ( n ) 2 C2

(22)

Considering (19) and z-k for a k-time delay operator, the following transfer function in the zdomain is obtained from (22):
( 2, 1 )

Vo ( z ) C1 1 ( z ) = ---------------- = ----- ----------------(2) C2 1 1 --Vi ( z ) 2 2 z z

(1)

(23)

which can be written as

C1 z 2 ( 2, 1 ) H ( z ) = ----- --------------C2 1 z1
1 --

(24)

Once again, note that vo remains constant during the next 2 phase, vo(n+1) = vo(n+1/2), and thus,
( 2, 2 )

C1 z 1 = ----- --------------C2 1 z1

(25)

At this point, we can confirm that both SC integrators in Fig.3b and c, implement discrete transfer functions in the z-domain, but now the question arises of how closely these transfer functions resemble their continuous time counterparts H(s) = 1/sRC2, derived from the circuit shown in Fig.3a. Comparing H(s) and the different H(z), shows that each H(z) can be obtained from H(s) through a particular transformation from the s-domain to the z-domain. Thus, considering R = T/C1, the following transformations result:
H(s) C1 z1 H ( z ) = ----- --------------1 C2 1 z1 s -- ( z 1 ) T

(26)

H(s)

1z 1 s -- ---------T z

C1 1 H ( z ) = ----- --------------C 2 1 z 1

(27)

C1 z 2 H(z) H ( z ) = ----- --------------1z 1 C 2 1 z 1 s -- ---------T z

1 -2

1 --

(28)

The above s-z relations are known respectively as Euler Forward, Euler Backward and Lossless difference transformations. They are derived by considering numerical approximations of the derivative operator. For this reason, the discrete time integrator with H(z) in Eq.(26) is known as a Forward Euler integrator (FE); with H(z) in Eq.(27) is known as a Backward Euler integrator (BE); and Eq.(28) refers to the H(z) of a Lossless Discrete Integrator (LDI). These results lead to the following conclusions: a) The circuits in Fig.3b and c can both serve independently as parasitic-free inverting and noninvertingLDI integrators, respectively Eq.(17) and (24).

10

Chapter 1 - Discrete-Time Applications

b) Owing to the phasing requirements, the inverting integrators can be BE or LDI, and the noninverting will be FE and LDI. c) The cascade of a BE integrator and a FE integrator is equivalent to the cascade of two LDI integrators. Note that to properly connect two LDI integrators, they must be switched in opposite phases. In addition to the Euler and LDI integrators, Bilinear SC integrators may be realized. They correspond to the s-z mapping,
2z 1 s -- ---------Tz + 1

(29)

The circuit in Fig.5 is a stray-insensitive bilinear SC integrator. It requires a sample-and-held circuit at the input and thus, two op-amps are necessary. Other simpler realizations are possible but they are sensitive to parasitics. However, as we will see later, transfer functions obtained using the bilinear transformation can be easily implemented with the simpler LDI integrators.

2 1 1 CH Vi 2

2 (1) 1 (2) 2 ( 1)

C2

1 Vi

C1 C1 1

_ +

1 (2)

Fig. 5. Stray-insensitive inverting bilinear integrator (noninverting when clock phases in

parenthesis are used).

To know the degree of approximation achieved when using a particular type of integrator, it is important to understand the difference in the frequency characteristics of the continuous-time integrator and its discrete-time counterpart. For sinusoidal inputs, the continuous-time characteristic results, (30) which means that the integrator has a phase shift of /2 for all frequencies and a magnitude equal to 1/wR1C2. Making z=ejwT (T being the clock period) in the z-domain transfer functions of the previous
1 1 H ( jw ) = --------- ----- RC 2 jw

Section 1.2 - Description of SC Circuits in the Time and Frequency Domains

11

integrators obtains the results summarized in Table 2. These results show that all SC integrators only

Integrator. Continuous.

z-domain s-z mapping. transfer function.

frequency response. 1 ---------------jC 2 R

B.E.

F.E.

1 s -- ( z 1 ) T

C1 z1 ----- --------------C2 1 z1
1 -2

T jT ------ --------C1 2 2 --------------- -------------------- e jTC 2 T sin ------- 2 T ------C1 2 --------------- -------------------jTC 2 T sin ------ 2 T ------C1 2 --------------- -------------------jTC 2 T tan ------ 2

1 z 1 s -- ---------L.D.I. T 1 - 2 z

C1 z ----- --------------C 2 1 z 1

2z 1 Bilinear. s -- ---------Tz + 1

C1 1 + z1 ----- --------------C2 1 z1

Table 2

approximately simulate the continuous-time integrator. Both Euler and LDI integrators introduce a magnitude error equal to |(wT/2)|sin(wT/2)|, while the deviation provoked by the bilinear integrator is equal to |(wT/2)|tan(wT/2)|. On the other hand, the integrator phase shift equals /2 (like the continuous time) in both the LDI and bilinear integrators, while an extra phase shift of wT/2 exists for the Euler integrators. Fortunately this phase error is cancelled in some applications where a two integrator loop is used. However, maintaining a minimal magnitude error requires clocking the circuit with sufficiently high frequency so that wT<<1, and thus sin(wT/2)(wT/2). That is, input signal frequencies f fulfill the following,
fclock f --------------2

(31)

and the frequency responses of the SC lossless standard integrators are of the form,
C1 e 2 jwt H ( e ) = ----- --------------C 2 jwT
wT j -------a

(32)

where a=0 for LDI and bilinear integrators, and a=1 for Euler integrators. Note that whenever (31) is fulfilled, the transfer function in (32) is identical to that for the con-

12

Chapter 1 - Discrete-Time Applications

tinuous time integrator for R = T/C1, except for the excess of phase. This excess of phase is the main cause of error in SC approximations where integrators are used to simulate reactive elements from a passive prototype. Concretely, the integrator phase error is reflected in the Q of the element being simulated. To illustrate this effect, let us consider the general continuous integrator transfer function,
1 i H ( jw ) = ------------- e jwRx i

(33)

where xi represents a generic element. Assuming <<2, then,

1 + j 1 H ( jw ) ------------- = ------------- + ----------jwRxi jwRx i wRxi

(34)

Now let us consider a reactive element xi with a Q factor Qxi, represented as,
1 1 1 H ( jw ) = ------------------------ --------- 1 + j -----wx i jwx i Qx i jwxi + ------Qx
i

(35)

Comparing (34) and (35) gives,

Qx
1
i

(36)

Thus, since 0 infers that Q , the effect of integrator phase error is analogous to dissipation in an L or C element of the passive circuit.

1.2.2 Lossy Integrators.

Besides lossless integrators, lossy integrators are also needed for the design of SC filters. Lossy integrators are damped integrators which can be obtained by connecting a switched-capacitor simulating a linear resistor across the integrating capacitor C2 of a lossless integrator. The circuit in Fig.6a is a damped inverting integrator; its transfer function can be derived directly in the z-domain by considering the circuit as an integrator with two inputs, Vi(z) and Vo(z), and applying the superposition principle. Thus,
C1 C3 1 1 V o ( z ) = ----- --------------- V i ( z ) ----- --------------- V o ( z ) 1 C2 1 z C2 1 z1

(37)

which leads to the transfer function

H
( 2, 2 )

C1 C1 1 ( z ) = -------------------------------------------- = ----- ---------------------------------1 C 3 C2 1 C2 ( 1 z ) + C3 1 + ----- z - C2

(38)

The pole of H(z) is zp = 1/((1 + (C3/C2)), which is inside the unit circle and thus the integrator is stable. Note that this is a consequence of adding a positive SC resistor in the feedback path around the opamp. In SC circuits, the total number of switches required may be reduced by sharing a set of them. This is illustrated in Fig.6b for the lossy inverting integrator. Note that capacitors C1 and C3 are connected to the input of the opamp or to the ground at the same clock-phase; hence we can use the scheme in Fig.6b to the same end, thus reducing the number of switches. For physical frequencies it results from (38),

Section 1.2 - Description of SC Circuits in the Time and Frequency Domains

13

2 Vo C1 e ----- ( jw ) = ----- -------------------------------------------------------------------------------------Vi C2 C3 wT 2j sin ------ + ----- cos wT + j sin wT ----------- 2 C2 2 2

jwT ---------

(39)

Thus, the damping term in the denominator is a function of frequency and the capacitor C3 also contributes to alter the imaginary part. A constant damping factor results only for (wT/2)<< 1. In this case, the transfer function is
Vo ----- ( jw ) Vi
2 C1 e ----- ----------------------------------------------wT C 2 C3 C3 ------- 1 2 jwT 1 + --------- + ---- 2C 2 C 2 jwT ---------

(40)

which results in a 3dB frequency equal to C3/T(C2+C3/2).

2 C3 2

1 C2 2 vi 1 1 C1 2

_ +

v0

(a)
C3 2

1 C2 2 vi 1 1 C1 2

_ + (b)

v0

Fig. 6. Lossy integrators

1.2.3 General First-Order SC Building Blocks.

Many applications require more general building blocks to simultaneously perform several functions such as summation, amplification, and integration. The circuit in Fig.7 is a general form of a strayinsensitive first-order building block. It has three feed-in branches and a damped path. The output voltage of this building block can be expressed as:

14

Chapter 1 - Discrete-Time Applications

C1 1 C2 z 1 C3 C4 1 V o ( z ) = ----- --------------- V 1 ( z ) + ----- --------------- V 2 ( z ) ----- V 3 ( z ) ----- --------------- V 0 ( z ) C 1 z1 C 1 z1 C C 1 z 1

C4

1 C3 V3 C1 V1 2 1 1 1 C

_ +
1

2 V0

2 V2 1

C2

Fig. 7

Use of this general block enables realization of different forms of integrator-summators for special cases. For instance, if all input are connected to the same voltage source Vi, the following transfer function results:
Vo ( z ) C1 + C2 z C3 ( 1 z ) ------------ = -----------------------------------------------------------1 Vi ( z ) C(1 z ) + C
4 1 1

(41)

1.2.4 Synthesis and Design of SC Filters

Due to the sampled data nature of SC filters, their frequency response characteristics are described in the discrete z-domain. Consequently, the first step in the synthesis of SC filters is to find an appropriate transfer function in the complex variable z, which meets certain frequency specifications. Direct approximation methods are seldom used to obtain this transfer function; instead, one resorts to the experience and information (programs and tables) related to continuous filters. Thus, in many practical applications the frequency requirements are specified in the continuous domain, although they must be implemented using a sampled-data system. Methods to convert continuous filters to sampled-data filters are commonly based on a mathematical s-z transformation. Given a continuous transfer function HA(s), a transfer function HD(z) of the sampled-data system counterpart is obtained by simply replacing s in HA(s) by some function
s = f( z)

(42)

It is well known that to carry out HD(z), in addition to transferring the essential properties of continuous systems to discrete systems, the following conditions must be imposed on f(z): a) f(z) must be a rational function of z. Hence, a rational function HA(s) can be transformed into a rational function HD(z). Note that since HD(z) and HA(s) are basically different functions, we use the subindexes D (discrete) and A (continuous) to distinguish them.

Section 1.2 - Description of SC Circuits in the Time and Frequency Domains

15

b) The imaginary axis of the s-plane should be mapped onto the unit circle in the z-plane. c) For |z|<1, the real part of s = f(z) must be negative, and viceversa; for Re(s) < 0 the corresponding z value must have an absolute value of less than 1. In any case a nonlinear relation between the analog and the discrete frequencies is obtained. This relation is known as the warping effect, which is reflected as a distortion of the frequency axis scale, expressed as,
WA = Im [ f ( e
jW D T

)]

(43)

where T is the clock period. This effect must be considered in the frequency specifications of the filter to be compensated. Many functions f(z) satisfying the above cited conditions can be determined through diverse procedures. However, the most generally accepted approaches in the SC filter field are those based on numerical approximation of the integrator and/or differential operator. Several s-z mappings were shown to be realizable by |SC integrators in Section 3. However, it can be seen than only the bilinear mapping fulfills the three necessary requirements for a good transformation between the continuous and discrete domains. Backward and Forward Euler transformations do not meet conditions b and c, and consequently they are undesirable mappings. On the other hand, the LDI mapping does not meet condition c, since a given s = so is always mapped on two values of z, namely zo and -zo-1. Consequently, the LDI transformation leads stable continuous systems to unstable discrete filters and should not be used. However, SC filter designs based on the LDI transformation are widely used. The reasons for this will be clear soon, although we may state in advance, that all the LDI realizations result in approximated realizations which are only sufficient for relatively high oversampling ratios (ratio of the clock signal frequency to the cutoff frequency of the filter). Moreover, these approximated realizations correspond to leapfrog structures which simulate doubly terminated LC passive filters, hence they have very good sensitivity features. In other realizations, for example, the cascade of biquadratic functions, the LDI transformation is seldom used. There are many design methods and SC topologies which can be used to realize a given HD(z) [Greg86,??????]. The majority of the practical implementations are based on one of the two following approaches: 1) Cascade of first- and second-order sections. 2) Simulation of doubly-terminated LC ladder networks. In any case, the general procedure to obtain SC filter topologies is equal to that followed for active RC realizations, with two additional steps for the SC case: a) Prewarping. Since the approximation is made in the continuous-time domain, prewarping of the desired frequency specifications must be carried out. This means that at the first stage of the design procedure we must apply the following frequency transformation to the sampled-data specifications For LDI:
Wd T 2 W a = -- sin ---------- T 2

(44)

For Bilinear:

16

Chapter 1 - Discrete-Time Applications

Wd T 2 W a = -- tan ---------- T 2

(45)

where Wa and Wd denote frequencies in the continuous and discrete domains, respectively. Fig.8 shows the warping effects for a low-pass filter; we can see how the frequency axis is altered. Consequently, the reference continuous filter corresponding to an LDI filter is more selective than that corresponding to a Bilinear realization. Thus, LDI realizations could require higher order topologies than Bilinear realizations.
d 2 a = -- tan ----- T 2

a /T
3/T 2/T Bilinear.

a=d
d 2 a = -- sin ----- T 2
L.D.I.

a
2/T

s p /T d
H(j

2/T

3/T

a)
For L.D.I. For BILINEAR.

p s
Fig. 8. Warping effects

b) Impedance scaling. In addition to the common use of scaling to increase the dynamic range and reduce element spreads, the impedance scaling step must be included in some integrator-based topologies to obtain realizable SC implementations. Detailed coverage of this point will be presented when dealing with the design of LC ladder-based implementations. Fig. 9 presents the two procedures for synthesizing SC filters. Details are given in the following subsections.

1.2.5 Cascade realizations

Similar to the case of an active RC filter, in the cascade approach the high order function HD(z) is factored into the product of first- and second-order functions.
N

HD ( z ) =

Hi ( i )
i=1

(46)

Second-order functions, known as biquads, have the generic form

a 2i z + a 1i z + a 0i H i ( z ) = K i ----------------------------------------2 z + b 1i z + b 0i
2

(47)

Section 1.2 - Description of SC Circuits in the Time and Frequency Domains

17

Frequency specifications. Choose s-z transform.

Prewarping.
Obtain HA(s).

Cascade approach.

LC ladder simulation

Nj ( s )
j H A ( s ) = ------------------- Dj ( s ) j

Obtain LC prototype.

* Pole-zero pairing. * Cascading sequence. * Gain distribution. HA ( s ) = Hi ( s )

i

Generate signed flow Graph (SFG)

Hi ( s ) Hi ( z )

Convert SFG to a SC network.

Use of universal SC biquad topology to implement each Hi(z). - Scaling the first design. - Choose capacitance values.

Evaluate capacitor ratios.

Scaling for maximum dynamic range.

Connect all biquads.

Adjust capacitance value for minimum total area.

SC filter
Fig. 9.

SC filter

The resulting functions are realized using integrators as building blocks, and are connected in cascade in such a way that their product is the wasted HD(z). The cascade design is very popular mainly due to the following: - Any low-pass, band-pass, and high-pass filter function can be realized by the cascade method. - Different and easy-to-design SC biquad topologies can be efficiently used. - It results in easy-to-tune filters because their critical frequencies are performed individually by each biquad.

18

Chapter 1 - Discrete-Time Applications

The main drawback of the cascade approach is that the resulting implementations are more sensitive to component variations than the ladder simulation approach. The systematic procedure for the design of cascaded SC filters is fundamentally the same as that for RC filters, and hence it is sufficiently well known so as not to be included in this section. As shown in Fig.9, after prewarping the frequency specifications, all the synthesis is carried out in the continuous domain; thus, the pole-zero pair assignment, cascading sequence, and gain distribution for the biquads used are handled in the variable s. All we require for the SC design is the way the function Hi(s) are transformed into Hi(z), and how these z-domain biquads are implemented. The building blocks for cascade realizations are biquads implementing the biquadratic functions.
a2 z + a1 z + a0 H ( z ) = k -----------------------------------2 z + b1 z + b0
2

(48)

which are obtained from biquadratic H(s) functions by an s-z transformation. We will assume in the following that this transformation is the exact bilinear mapping. For the SC realization of H(z) a family of SC biquad building blocks has been proposed [Flus79] whose transfer function resembles (49). The schematic of this general topology is shown in Fig.11. It consists of a loop of two general first-order building blocks like that shown in Fig.7. Sampling Vi in 1 and maintaining it for the full period T, results in the following two z-domain transfer functions,
V1 ( z ) [ zC + E ( z 1 ) ] [ zI J + k ( z 1 ) ] [ zF + B ( z 1 ) ] [ zG H + L ( z 1 ) ] H 1 ( z ) = ------------- = -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------A [ zC + E ( z 1 ) ] + D ( z 1 ) [ zF + B ( z 1 ) ] Vi ( z )

(49)
V2 ( z ) [ zC + E ( z 1 ) ] [ zI J + k ( z 1 ) ] [ zF + B ( z 1 ) ] [ zG H + L ( z 1 ) ] H 2 ( z ) = ------------ = = -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------Vi ( z ) A [ zC + E ( z 1 ) ] + D ( z 1 ) [ zF + B ( z 1 ) ]

(50) The main features of this topology are: a) Two output available, V1 and V2. b) Provide the capability of realizing all stable z-biquadratic functions. The denominator is determined by the capacitors in the loop (A, B, C, D, E, F) and the numerator, by the feedin capacitors (G, H, I, J, K, L). c) Provide enough flexibility for dynamic range optimization and scaling for minimum total capacitance. To this respect, note that capacitors A and D can be replaced by nA and nD, respectively, reducing the signal level of V1 by the factor n while not altering the level of V2. On the other hand, replacing capacitors B, C, F, and E by capacitors B/n, C/n, F/n, and E/n respectively, an increase of V2 in a factor of n results without changing V1. d) Capacitor E and F in the feedback paths are redundant both providing a means for clamping the poles. This redundancy is eliminated in practical cases where one E or F is set to zero. Hence, two cases of circuits are available, the so-called E-circuit where F = 0, and the Fcircuit where E = 0. In sum, the general circuit in Fig.10 with 12 capacitors (or 11) gives the designer sufficient freedom to realize any set of 6 parameters (a2, a1, a0, b1, b0, k) in (49), achieving an acceptable compromise between minimum total capacitance and sensitivity.

Section 1.2 - Description of SC Circuits in the Time and Frequency Domains

19

Some guidelines for simple and good designs are given in [Flus79]. For instance, setting K = L = 0 reduces the number of switches through switch sharing; this schematic is shown in Fig.11. In addition, for a first design B, D, and A can be normalized to unity, resulting in the two functions,
2 V1 ( IC + IE FG G )z + ( FH + H JC JE IE )z + ( EJ H ) H 1 = ------- = ------------------------------------------------------------------------------------------------------------------------------------------------------2 V in ( 1 + F )z + ( C + E F 2 )z + ( 1 E )

(51)

2 V2 Jz + ( G I J )z + ( J H ) H 2 = ------- = --------------------------------------------------------------------------------------------2 V in ( 1 + F )z + ( C + E F 2 )z + ( 1 E )

(52)

Now, an evident salient feature of H2 is that poles and zeros can be adjusted independently. This fact is not determinant for the choice of H2 instead of H1, and other features like sensitivity and minimum area ..... do preferable the function H1. Once the initial design is complete, the stages may be properly scaled for both appropriate signal level and minimum total capacitances. This later scaling is realized in the groups of capacitors connected to the virtual ground of each op-amp. First, the smallest capacitance x1 of a group is made equal to the smallest value allowed by the technology (Cmin); then, all the capacitors in the group are multiplied by k = Cmin/xi. The advantages for using H1 or H2, as well as E or F circuits are not clear. Designers usually prefer to use H2 in (53). However, choosing E-circuits (F = 0) for high-Q designs and F-circuits (E = 0) for low-Q designs yields less capacitance spread (ratio of maximum to minimum capacitances).

L 2 E 1 2 2 1 K 1 2 I H G 1

1 2

1 2 D 1 2 2

F 2 B

_ +

2 v1 1

1 2

vi

_ +
1

1 v2

2 1

1 2

Fig. 10. Stray-insensitive generic SC biquad circuit

20

Chapter 1 - Discrete-Time Applications

C E

F D 1 2 2 2 1 I F H G 1

2 B 2 v1 1 2 A 1

_
vi

_ +
v2

Fig. 11. Alternative generic SC biquad circuit.

Note: Choose F = 0 for high-Q biquads: E = 0 for low-Q biquads.