Académique Documents
Professionnel Documents
Culture Documents
IM 34M6P13-01E
Yokogawa Electric Corporation
2nd Edition
Applicable Product:
G Range-free-controller FA-M3
Model Name: F3SP28, F3SP38, F3SP53, F3SP58, F3SP59 Name: Sequence CPU Modules
The document number and document model code for this manual are given below. Refer to the document number in all communications; also refer to the document number or the document model code when purchasing additional copies of this manual. Document No. Document Model Code : : IM 34M6P13-01E DOCIM
Media No. IM 34M6P13-01E (CD) 2nd Edition : Oct 1, 2002 (AR) All Rights Reserved Copyright 1992, Yokogawa Electric Corporation
IM 34M6P13-01E
ii
Important
About This Manual
This Manual should be passed on to the end user. Before using the controller, read this manual thoroughly to have a clear understanding of the controller. This manual explains the functions of this product, but there is no guarantee that they will suit the particular purpose of the user. Under absolutely no circumstances may the contents of this manual be transcribed or copied, in part or in whole, without permission. The contents of this manual are subject to change without prior notice. Every effort has been made to ensure accuracy in the preparation of this manual. However, should any errors or omissions come to the attention of the user, please contact the nearest Yokogawa Electric representative or sales office.
Danger. This symbol on the product indicates that the operator must follow the instructions laid out in this instruction manual to avoid the risk of personnel injuries, fatalities, or damage to the instrument. Where indicated by this symbol, the manual describes what special care the operator must exercise to prevent electrical shock or other dangers that may result in injury or the loss of life.
Protective Ground Terminal. Before using the instrument, be sure to ground this terminal.
Function Ground Terminal. Before using the instrument, be sure to ground this terminal.
IM 34M6P13-01E
iii
The following symbols are used only in the instruction manual.
WARNING
Indicates a Warning. Draws attention to information essential to prevent hardware damage, software damage or system failure.
CAUTION
Indicates a Caution Draws attention to information essential to the understanding of operation and functions.
TIP
Indicates a TIP Gives information that complements the present topic.
SEE ALSO Indicates a SEE ALSO reference. Identifies a source to which to refer.
For the protection and safe use of the product and the system controlled by it, be sure to follow the instructions and precautions on safety stated in this manual whenever handling the product. Take special note that if you handle the product in a manner other than prescribed in these instructions, the protection feature of the product may be damaged or impaired. In such cases, Yokogawa cannot guarantee the quality, performance, function and safety of the product. When installing protection and/or safety circuits such as lightning protection devices and equipment for the product and control system as well as designing or installing separate protection and/or safety circuits for fool-proof design and fail-safe design of processes and lines using the product and the system controlled by it, the user should implement it using devices and equipment, additional to this product. If component parts or consumable are to be replaced, be sure to use parts specified by the company. This product is not designed or manufactured to be used in critical applications which directly affect or threaten human lives and safety such as nuclear power equipment, devices using radioactivity, railway facilities, aviation equipment, air navigation facilities, aviation facilities or medical equipment. If so used, it is the users responsibility to include in the system additional equipment and devices that ensure personnel safety. Do not attempt to modify the product.
IM 34M6P13-01E
IM 34M6P13-01E
IM 34M6P13-01E
vi
G Keep spare parts on hand:
Stock up on maintenance parts including spare modules, in advance.
IM 34M6P13-01E
vii
Introduction
I Overview of the Manual
This manual describes the sequencing functions of sequence CPU modules (For F3SP28-3N/3S, F3SP38-6N/6S, F3SP53-4H/4S, F3SP58-6H/6S, F3SP59-7S)designed for use with the Range-free Multi-controller FA-M3.
Work Flow from System Design to System Operation, and Relevant Chapters
Design Target machine
Start Determination of system configuration System design Chapter 2, "System Configuration" Assignment of I/Os, registers and relays Basic design Chapter 4, "Devices," and Chapter 5, "Programs"
Start
Wiring
I/O verification
Input: Verification of I/Os with LED lamps Output: Forced SET and RESET instructions Chapter 6, "Functions"
Program downloading Coding Configuration of a ladder diagram Ladder symbols Mnemonic language Chapter 1, "Overview of Instruction Words," Chapter 2, "Basic Instructions," and Chapter 3, "Advanced Instructions," in the Instructions volume of the 3rd or later edition of the Sequence CPUs instruction manual Program input for simulation Performance check Verification of basic logic Program modification Chapter 6, "Functions"
Programming
End of flow?
End
End of flow?
End
F000001.VSD
IM 34M6P13-01E
G For information on the instructions used with sequence CPUs, refer to:
Sequence CPU Instruction Manual - Instructions (IM34M6P12-03E)
G For information on the commands and responses of personal computer link functions
Personal Computer Link Command Instruction Manual (IM34M6P41-01E).
G For information on the specifications*, configuration*, installation, wiring, trial operation, maintenance and inspection of the FA-M3, as well as information on the system-wide limitation of module installation, refer to:
*:
G For information on the functions of F3SP21, F3SP25 and F3SP35 sequence CPU modules, refer to:
Sequence CPU Instruction Manual - Functions (for F3SP21, F3SP25 and F3SP35) (IM34M6P12-01E).
G For information on the functions of FA link H and fiber-optic FA link H modules, refer to:
FA Link H Module, Fiber-optic FA Link H Module (IM34M6H43-01E).
IM 34M6P13-01E
ix
Trademarks
The trade and company names that are referred to in this document are either trademarks or registered trademarks of their respective companies.
IM 34M6P13-01E
Blank Page
TOC-1
FA-M3
Sequence CPU Instruction Manual - Function
(For F3SP28-3N/3S, F3SP38-6N/6S, F3SP53-4H/4S, F3SP58-6H/6S, F3SP59-7S)
IM 34M6P13-01E 2nd Edition
CONTENTS
Applicable Product ................................................................................... i Important .................................................................................................. ii Introduction ............................................................................................ vii Copyrights and Trademarks................................................................. Viii 1. Specification and Basic Configuration ....................................... 1-1
1.1 1.2 Overview ................................................................................................... 1-1 Specification............................................................................................. 1-3 1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 1.3 1.3.1 1.3.2 1.3.3 Tables of Performance Data......................................................... 1-3 Device List .................................................................................... 1-7 Configuration ................................................................................ 1-9 Components and Their Functions .............................................. 1-14 External Dimensions .................................................................. 1-15 Unit ............................................................................................. 1-16 Slot Number................................................................................ 1-17 I/O Relay Number....................................................................... 1-19
2.
3.
TOC-2
3.3.3 3.3.4 3.4 3.5 3.6 Operation in Case of Complete Power Failure............................. 3-6 Specifying the Range of Devices to Be Latched in Case of Complete Power Failure.............................................. 3-6
Computation Method ............................................................................... 3-7 Method of Executing Peripheral Processes.......................................... 3-9 Method of I/O Processing ..................................................................... 3-11 3.6.1 3.6.2 3.6.3 Method of I/O Processing........................................................... 3-11 Response Delay ......................................................................... 3-12 I/O Processing in Multi-CPU System.......................................... 3-13 Tool Service ................................................................................ 3-14
3.7 3.8
Method of Executing Commands from the WideField2 ..................... 3-14 3.7.1 Method of Executing Commands through Personal Computer Link ....................................................................... 3-15 3.8.1 Personal Computer Link Service................................................ 3-15 Method of Updating Shared Data............................................... 3-16 Setting the Mode of Shared Refreshing ..................................... 3-18 CPU Service ............................................................................... 3-22 Method of CPU-to-CPU Data Communication .................................... 3-16 3.9.1 3.9.2 3.9.3
3.9
3.10
Method of Link Data Updating .............................................................. 3-23 3.10.1 Link Data Updating ..................................................................... 3-23 3.10.2 Link Refreshing........................................................................... 3-24
3.11
Method of Interrupt Processing .......................................................... 3-26 3.11.1 Interrupt Processing ................................................................... 3-26 3.11.2 Interrupt Processing Control....................................................... 3-27 3.11.3 Interrupt Timing........................................................................... 3-28 3.11.4 Interrupt Priority .......................................................................... 3-32
4.
Internal Relays (I), Shared Relays (E) and Extended Shared Relays (E) ................................................................... 4-6 4.2.1 4.2.2 Internal Relays (I) ......................................................................... 4-6 Shared Relays (E) and Extended Shared Relays (E) .................. 4-7 Link Relays (L)............................................................................ 4-13 Link Registers (W)...................................................................... 4-14 System Numbers ........................................................................ 4-15 Configuring Link Relays (L) and Registers (W).......................... 4-16 Link Refreshing Range............................................................... 4-17 Block Start Status ....................................................................... 4-19 Utility Relays............................................................................... 4-20
IM 34M6P13-01E 2nd Edition : Oct 1, 2002
4.3
Link Relays (L) and Link Registers (W) ............................................... 4-12 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5
4.4
TOC-3
4.4.3 4.4.4 4.4.5 4.5 4.5.1 4.5.2 4.5.3 4.6 4.7 4.6.1 Sequence Operation and Mode Status Relays .......................... 4-22 Self-diagnosis Status Relays...................................................... 4-23 FA Link Module Status Relays.................................................... 4-24 100-s, 1-ms, 10-ms, and 100-ms Timers ................................. 4-25 100-ms Continuous Timer .......................................................... 4-27 Selecting Timers ......................................................................... 4-28 Selecting Counters ..................................................................... 4-30
Counters (C) ........................................................................................... 4-29 Data Register (D), Shared Register (R) and Extended Shared Register (R) .............................................................. 4-31 4.7.1 4.7.2 4.7.3 Data Registers (D)...................................................................... 4-31 Shared Registers (R) and Extended Shared Registers (R) ...... 4-32 Setting Initial Data for Data Registers (D) .................................. 4-38 Sequence Operation Status Registers ....................................... 4-39 Self-diagnosis Status Registers.................................................. 4-40 Utility Registers........................................................................... 4-41 FA Link Module Status Registers................................................ 4-42 Sequence CPU Module Status Registers .................................. 4-43
4.8
Special Registers (Z) ............................................................................. 4-39 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5
4.9 4.10
Index Registers (V) ................................................................................ 4-44 File Registers (B) ................................................................................... 4-45 Programming Language ......................................................................... 5-1 5.1.1 5.1.2 Structured Ladder Language........................................................ 5-1 Mnemonic Language .................................................................... 5-2 Blocks and Executable Programs ................................................ 5-3 Programs Composing an Executable Program............................ 5-5
5.
Programs....................................................................................... 5-1
5.1
5.2
5.3
Program Memory ................................................................................... 5-10 Function List ............................................................................................ 6-1 Operation Setup Function....................................................................... 6-3 Constant Scan 6.3.1 ...................................................................................... 6-5 Setting the Constant Scan Time................................................... 6-5 Executing All Blocks ..................................................................... 6-6 Executing Specified Blocks .......................................................... 6-7 Operation When Specified Blocks Are Enabled ........................... 6-8 Operation When Specified Blocks Are Disabled ........................ 6-10 Operation When Specified Blocks Are Executed ....................... 6-11 Forced SET/RESET ................................................................ 6-13
6.
Executing All Blocks/Specified Blocks ................................................. 6-6 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5
6.5
Debugging Functions............................................................................ 6-13 6.5.1 6.5.2 Changing Setpoints, Current Values and Data Values............... 6-13
IM 34M6P13-01E 2nd Edition : Oct 1, 2002
TOC-4
6.5.3 6.6 6.6.1 6.6.2 6.7 6.8 Stopping Refreshing ................................................................. 6-14 Executable Program Protection.................................................. 6-15 Block Protection.......................................................................... 6-16 Protecting Programs ............................................................................. 6-15
Online Editing ...................................................................................... 6-17 Making Programs Resident Using ROM Writer Functions ................ 6-18 6.8.1 6.8.2 6.8.3 Making Programs Resident in ROM........................................... 6-18 Setting Devices Current Values to Be Made Resident in ROM ............................................................. 6-20 ROM Writer Functions and ROM Writer Mode ........................ 6-21
Exclusive Access Control ..................................................................... 6-23 Sampling Trace Function ...................................................................... 6-24 Personal Computer Link Function ....................................................... 6-28 6.11.1 System Configuration ................................................................. 6-29 6.11.2 Differences from Personal Computer Link Module .................... 6-30 6.11.3 Specification of Personal Computer Link Function .................... 6-32 6.11.4 Setting Up the Personal Computer Link Function ...................... 6-33 6.11.5 Communication Procedure......................................................... 6-34 6.11.6 Commands and Responses ....................................................... 6-36
6.12 6.13
Device Management Function .............................................................. 6-45 Macro Instructions................................................................................. 6-46 6.13.1 What Are Macro Instructions? .................................................... 6-46 6.13.2 Specification of Macro Instructions............................................. 6-50 6.13.3 Devices Dedicated to Macro Instructions ................................... 6-51 6.13.4 Nesting Macro Instructions......................................................... 6-54 6.13.5 Handling Macro Instruction Errors.............................................. 6-56 6.13.6 Protecting Macro Instructions..................................................... 6-57 6.13.7 Debugging Operation ................................................................. 6-57 6.13.8 Input Macro Instructions ........................................................... 6-58 6.13.9 Structure Macro Instructions ..................................................... 6-60
6.14 6.15
User Log Management Function .......................................................... 6-62 Sensor Control Function....................................................................... 6-64 6.15.1 Schematic Operation Diagram ................................................... 6-64 6.15.2 Features ..................................................................................... 6-65 6.15.3 Specifications and Restrictions................................................... 6-66 6.15.4 Function Setup Items ................................................................. 6-70 6.15.5 Procedures for Using Sensor Control Function.......................... 6-77 6.15.6 Error Handling ............................................................................ 6-77 6.15.7 Programming Precautions.......................................................... 6-79
6.16 6.17
Partial Download Function ................................................................. 6-81 Function for Storing Comments to CPU ........................................... 6-83 6.17.1 Performing Setup to Download Comments................................ 6-83 6.17.2 Number of Steps Needed for Comments ................................... 6-84 6.17.3 Online Editing of Comments....................................................... 6-85
IM 34M6P13-01E
TOC-5
6.18 6.19 Function for Storing Tag Name Definitions to CPU ........................... 6-86 Structures ............................................................................................... 6-87 Information on Scan Time....................................................................... 7-1 Setting Scan Time Monitoring Time....................................................... 7-4 Examples of Calculating the Scan Time................................................ 7-5 Examples of Calculating the I/O Response Time ................................. 7-7 Instruction Execution Time..................................................................... 7-9 Self-diagnosis .......................................................................................... 8-1 8.1.1 8.2 Setting Operation Mode in Case of Failure and External Output Mode in Case of Sequence Stop........................ 8-9
7.
8.
Recovering Normal Operation after Correcting Non-fatal/Minor Errors........................................................................... 8-10 Comparison of Performance Data.......................................................... 9-1 Configuration ........................................................................................... 9-3 Special Relays (M) and Special Registers (Z) ....................................... 9-5 CPU Module to CPU Module Communication Method......................... 9-7 High-speed Processing of Application Instructions ............................ 9-7 Instructions .............................................................................................. 9-8
9.
- S and F3SP
Partial Download Function ................................................................... 10-1 Storing Comments or Tag Name Definitions in CPU.......................... 10-1 New Instructions and Instruction Related Functions ........................ 10-2 Changes in Specifications .................................................................... 10-3 Block Start Status ............................................................ App.1-1 Utility Relays .................................................................... App.1-2 Sequence Operation and Mode Status Relays ............. App.1-3 Self-diagnosis Status Relays.......................................... App.1-4 FA Link Module Status Relays ........................................ App.1-5 Sequence Operation Status Registers .......................... App.2-1 Self-diagnosis Status Registers ..................................... App.2-2 Utility Registers................................................................ App.2-3 FA Link Module Status Registers ................................... App.2-4 Sequence CPU Module Status Registers ...................... App.2-5
Appendix 3. Forms for System Design ..................................... App.3-1 Index................................................................................................Index-1 Revision Information ................................................................................ i
IM 34M6P13-01E
Blank Page
1-1
1.
1.1
Overview
This section describes the overview, features, main functions of the sequence CPU module.
I Overview
Models F3SP28-3N, F3SP38-6N, F3SP53-4H, F3SP58-6H, F3SP28-3S, F3SP38-6S, F3SP53-4S, F3SP58-6S and F3SP59-7S are CPU modules with built-in memory for use with the FA-M3. In addition to high-speed operation and large memory capacity, these modules have many more features that help increase your development and maintenance efficiency.
G Object Ladder
The FA-M3 Programming Tool WideField2, an object-oriented ladder language development tool, is available with the CPU module. This tool increases your productivity of programs more than structured programming does. In addition, it makes program maintenance easy.
- S
Circuit comments, subcomments, and tag name definitions (including I/O comments) can be stored in the sequence CPU or the ROM pack. This function allows you to debug a program using tag names, even during unscheduled maintenance.
IM 34M6P13-01E
1-2
G Other Features
Has a compact body, enabling you to reduce panel enclosure size. Operates large-capacity programs and has large device sizes and, therefore, can cope with advanced, complex control applications. - Uses index modification and structured ladder language for easy program design and maintenance. - Allows the device size and operating method to be flexibly configured according to your application needs. - Provides various functions, e.g., a forced SET/RESET function independent of program computation results, for easy program debugging and maintenance. - Has a carefully designed self-diagnosis function, in addition to a highly reliable design. - Provides macro instruction functions to allow you to create and register new instructions. - Has a sampling trace function capable of acquiring and displaying the states of a maximum of 1024 scans worth of devices. - Can connect to a host computer or a monitor without the need for a personal computer link module, as the programming tool connection port supports a personal computer link function. - Has a logging function capable of recording errors encountered in a program, as well as messages created and registered in advance. - Allows you to mount F3SP28, F3SP38, F3SP53, F3SP58 or F3SP59 modules in slots 2 to 4 of the main unit, for use as add-on CPU modules for sequence processes added to the main CPU module (F3SP21, F3SP25, F3SP28, F3SP35, F3SP38, F3SP53, F3SP58 or F3SP59). - Allows you to attach a ROM pack so that you can perform ROM-based operation and store programs. - Has a program protection function to ensure security. - The partial download function allows the downloading of specified blocks only, which increases debugging efficiency especially in program development by a team. F3SP - S - Indirect designation via devices is available, allowing large volume data handling and creation of efficient programs. F3SP - S - Structure macros simplify passing of data to macros and updating of these data structures. F3SP - S
G Functions
Sensor control Configuration (setup of parameters, including device size, range of devices to be latched in case of power failure, and external output to be retained in case of sequence stop) - Constant scan (at an interval of 1 to 190 ms, in 0.1 ms increments) - Sampling trace - Debugging (forced SET/RESET instructions, online editing, etc.) - Error logging, user logging - Clock (year, month, day, hour, minute, second, and day of the week) - Support for programming tool connection port with the personal computer link function - Program protection - Program/data storage in ROM pack - Circuit/sub-comment, tag name definitions storage in ROM pack. F3SP - S - Circuit/sub-comment storage function and tag name definition storage function. F3SP - S - Partial download function. F3SP - S See Section 1.2, Specification, for more information.
IM 34M6P13-01E 2nd Edition : Oct 1, 2002
1-3
1.2
Specification
This section describes the basic specifications of the FA-M3 sequence CPU module for each CPU type. For performance and specifications, see Section 1.2.1, "Table of Performance Data." For the types and number of devices, see Section 1.2.2, "Device List." For configuration setup ranges, see Section 1.2.3, "Configuration." For the names and functions of the components of the sequence CPU module, see Section 1.2.4, "Components and Their Functions." For the external dimensions of the sequence CPU module, see Section 1.2.5, "External Dimensions."
- S) (1/2) Specifications
F3SP28-3S F3SP53-4S F3SP38-6S F3SP58-6S F3SP59-7S Repetitive computation based on stored programs Refreshing by DIRECT REFRESH instruction Structured ladder language and mnemonic language 4096 max. 8192 max., including remote I/O points 16384 32768 65535 2048 2048 8192 16384 9984 1024 2048 1024 16384 32768 65535 1024 3072 32768 8192 1024 1024 4 16-bit instruction: 32-bit instruction: 16-bit instruction: 32-bit instruction: 16-bit instruction: 32-bit instruction: 262144 16384
Constants
-32768 to 32767 -2147483648 to 2147483647 $0 to $FFFF (hexadecimal number) $0 to $FFFFFFFF (hexadecimal number) e.g. AB, etc e.g. ABCD, etc. 32-bit instruction: e.g. 1.23, -3.21 Approximately -3.41038 to 3.41038 0 to 2047 254K steps 30K steps max. 56K steps max. 120K steps max.
max.
Program size (ROM resident) (Program + Tag Name Definition) size ROM-resident size (Program + Tag Name Definition) Number of program blocks Basic instructions Number of Application instructions instructions Number of macro instructions Basic instruction Application instruction
360K steps
max.
120K steps max. 1024 max. 37 329 256 max. 0.045 to 0.18s per instruction 0.18s min. per instruction 0.0175 to 0.07s per instruction 0.07s min. per instruction
IM 34M6P13-01E
1-4
Table 1.2 Performance Data (F3SP Item
Special module High Speed Read Instruction (HRD Instruction)/Special module High Speed Write Instruction (HWR Instruction) Sampling trace function Support for personal computer link function by programming tool connection port User log function Number of personal computer link modules Macro instruction function Scan time monitoring time Startup at power-on or recovery from power failure Sensor control function Constant scan Self-diagnosis Link function Comment storage function F3SP28-3S
64 instructions each Available. This function collects and displays the states of multiple devices for a maximum of 1024 scans. Available. This function allows a personal computer or a monitor to be connected to the programming tool connection port to perform communications equivalent to the personal computer link module. Available. This function allows the user to execute a user log command to log (record the history of) errors in the user system, including information on the state of occurrence and system operation, etc. 6 max. Available. This function allows the user to create and register new user-defined instructions. Variable from 10 to 200 ms. Automatic (Auto-logging of power-on time, power-off time and momentary power failure time) Available. In addition to normal scanning, this function allows one specified block to be scanned at high-speed fixed intervals. 1 to 190 ms, user-definable in 0.1 ms increments. Detection of memory failure, CPU failure and I/O module failure, syntax checking, etc. FA link, FL-net, personal computer link, and remote I/O link (fiber-optic FA-bus, -bus) Available. Circuit comment, sub-comment, tag name definition (including I/O comment). - Online editing - Forced SET/RESET instructions - Clock (year, month, day, hour, minute, second, and day of the week) - Configuration (setup of parameters, including device capacities, range of devices to be latched at power failure, and external outputs to be latched at sequence stop) - Protection - Stop refreshing function
Other functions
IM 34M6P13-01E
1-5
Table 1.3 Performance Data (F3SP Item
Control method I/O computation method Programming language Number of I/O points Number of internal relays (I) Number of shared relays (E) Number of extended shared relays (E) Number of link relays (L) Number of special relays (M) Number of timers (T) Number of counters (C) Number of data registers (D) Number of shared registers (R) Number of extended shared registers (R) Number of file registers (B) Number of link registers (W) Number of special registers (Z) Number of labels Number of input interrupt processing routines Decimal constant Hexadecimal constant Character-string constant Floating-point constant
- N, F3SP
- H) (1/2)
Specifications
F3SP28-3N F3SP53-4H F3SP38-6N F3SP58-6H Repeated computation based on stored programs Refreshing by DIRECT REFRESH instruction Structured ladder language and mnemonic language 4096 max. 8192 max., including remote I/O points 16384 32768 2048 2048 8192 16384 9984 1024 2048 1024 16384 32768 1024 3072 32768 8192 1024 1024 4 262144 16384
Constants
16-bit instruction: -32768 to 32767 32-bit instruction: -2147483648 to 2147483647 16-bit instruction: $0 to $FFFF (hexadecimal number) 32-bit instruction: $0 to $FFFFFFFF (hexadecimal number) 16-bit instruction: e.g. AB, etc 32-bit instruction: e.g. ABCD, etc. 32-bit instruction: e.g. 1.23, -3.21 approximately -3.41038 to +3.41038 30K steps max. 1024 max. 33 312 64 max. 0.045 to 0.18s per instruction 0.18s min. per instruction 64 instructions each 0.0175 to 0.07s per instruction 0.07s min. per instruction 0.045 to 0.18s per instruction 0.18s min. per instruction 0.0175 to 0.07sper instruction 0.07s min. per instruction 56K steps max. 120K steps max.
Program size (that can be ROM resident) Number of program blocks Basic instructions Number of Application instructions instructions Number of program blocks Instruction execution time Basic instruction
Application instruction Special module high speed read instruction (HRD instruction)/special module high speed write instruction (HWR instruction)
IM 34M6P13-01E
1-6
Table 1.4 Performance Data (F3SP Item
Sampling trace function Support for personal computer link function by programming tool connection port User logging function Number of personal computer link modules Macro instruction function Scan time monitoring time Startup at power-on or recovery from power failure Sensor control function Constant scan Self-diagnosis Link function
- N, F3SP
- H) (2/2) Specifications
F3SP28-3N F3SP53-4H F3SP38-6N F3SP58-6H Available. This function collects and displays the states of multiple devices for a maximum of 1024 scans. Available. The function allows a personal computer or a monitor to be connected to the programming tool connection port to perform communications equivalent to the personal computer link module. Available. This function allows the user to execute a user log instruction to log (record the history of) errors in the user system, including information on the state of occurrence and system operation, etc. 6 max. Available. This function allows a user to create and register new user-defined instructions.
Other functions
IM 34M6P13-01E
1-7
1.2.2
Device List
Table 1.5 Device List
Device Code X Y I F3SP28-3N/-3S F3SP53-4H/-4S Range Quantity X00201 to X71664 (discontinuous) 4096 Y00201 to Y71664 (discontinuous) I00001 to 16384 I16384 E0001 to 2048 E2048 E2049 to E4096 L0001 to L72048 (discontinuous) M0001 to M9984 T0001 to T0016 F3SP38-6N/-6S F3SP59-7S F3SP58-6H/-6S Range Quantity Range Quantity X00201 to X00201 to X71664 X71664 (discontinuous) (discontinuous) 8192 8192 Y00201 to Y00201 to Y71664 Y71664 (discontinuous) (discontinuous) I00001 to I00001 to 32768 65535 I32768 I65535 E0001 to E0001 to 2048 2048 E2048 E2048 E2049 to E4096 L0001 to L72048 (discontinuous) M0001 to M9984 T0001 to T0016 E2049 to E4096 L0001 to L72048 (discontinuous) M0001 to M9984 T0001 to T0016 Remarks The range used depends on the module type
Input relay Output relay Internal relay Shared relay Nonlatched Extended type shared relay Nonlatched type 100s Timer 1ms Timer 10ms Timer 100ms Timer 100ms Timer Latched type
2048
2048
2048
L M
8192 9984
16384 9984
16384 9984
These devices default to zero in quantity. Be sure to configure the devices when using the CPU module in a multiCPU configuration. Used in FA link and FL-net communications. Configurable for up to 16 timers Configuration limit correlated to counters (C) (*1).
Timer
T0001 to T2048
3072 in total
C D B W Z V
C0001 to C2048 D00001 to D16384 B000001 to B32768 W00001 to W72048 (discontinuous) Z0001 to Z1024 V001 to V256 R0001 to R1024 16384 32768 8192 1024 256 1024
C0001 to C3072
C0001 to C3072
Latched type Latched File register type NonLink register latched type Special register Index register Shared register Extended shared register
D00001 to D00001 to 32768 65535 D32768 D65535 B000001 to B000001 to 262144 262144 B262144 B262144 W00001 to W00001 to Used in FA link 16384 W72048 16384 and FL-net W72048 (discontinuous) (discontinuous) communications. Z0001 to Z0001 to 1024 1024 Z1024 Z1024 V001 to V256 R0001 to R1024 R1025 to R4096 256 1024 V001 to V256 R0001 to R1024 R1025 to R4096 256 1024 These devices default to zero in quantity. Be sure to configure the devices when using the CPU module in a multiCPU configuration.
Nonlatched type
IM 34M6P13-01E
1-8
Table 1.6 Device Capacities and Setup Restrictions
Device Timer Counter Shared relay Extended Shared relay Shared register Extended shared register Code T C E E R R F3SP28-3N/-3S F3SP53-4H/-4S Default Setup Restrictions value 1024 Total for timers and 1024 0 0 0 0
counters: 2048 max. Initial value for 100-s and 1-ms timers: 0
F3SP38-6N/-6S F3SP58-6H/-6S Default Setup value Restrictions 2048 Total for timers and 1024 0 0 0 0
counters: 3072 max. Initial value for 100-s and 1-ms timers: 0
F3SP59-7S Default Setup Restrictions value 2048 Total for timers and 1024 0 0 0 0
counters: 3072 max. Initial value for 100-s and 1-ms timers: 0
IM 34M6P13-01E
1-9
1.2.3
Configuration
This section describes the configuration function. The configuration setup ranges are summarized in the table below.
I Configuration Function
The sequence CPU contains the predefined defaults of device sizes and operation methods. You can use these defaults to run programs. In some applications, however, they may not suit your specific purpose of use. In such a case flexibility allows for defaults to be changed to meet your needs. Changing the defaults is called configuration and can be performed through the FA-M3 programming tool WideField2 (hereinafter simply referred to as WideField2).
IM 34M6P13-01E
1-10
I Tables of Configuration Ranges
Table 1.7 Configuration Range (1/5)
F3SP28-3N/-3S F3SP53-4H/-4S Item Shared relay (E) Shared Device (E, R) Extended shared relay (E) Shared register (R) Extended shared register (R) Link relay (L) Device capacities Link Device (L.W) Link register (W) 100s timer 1ms timer 10ms timer 100ms timer 100ms continuous timer Counter Default 0 0 0 0 FA links 1 to 4: 2048 FA links 5 to 8: 0 FA links 1 to 4: 2048 FA links 5 to 8: 0 0 0 512 448 128 1024 Configuration Range
2048 points max. on 32 points basis for all CPUs combined 2048 points max. on 32 points basis for all CPUs combined 1024 points max. on 2 points basis for all CPUs combined 3072 points max. on 2 points basis for all CPUs combined
8192 points max. on 16 points basis (Note) for all links combined. 8192 points max. on 16 points basis (Note) for all links combined. 2048 points on 1 point basis for timers and counters combined; 16 max. for 100s timers; Timer numbers are continuous. 2048 points on 1 point basis for timers and counters combined.
Configuration of Timers(T)/counters(C)
IM 34M6P13-01E
1-11
Table 1.9 Configuration Range (3/5)
F3SP28-3N/-3S F3SP53-4H/-4S F3SP38-6N/-6S F3SP58-6H/-6S F3SP59-7S Item Internal relay (I) Shared and extended shared relay (E) Link relay (L) Extended device configuration Configuration of the range of devices to be latched in case of power failure Timer (T) Counter (C) Data register (D) Shared and extended shared registers (R) Link register (W) Default I0001 to I1024 Non-latched type Non-latched type Non-latched type (except for continuous timers) All latched All latched Non-latched type Non-latched type Configuration Range Configurable on 32 point basis; continuous from the starting number Configurable on 16 points basis
(Note)
Configurable on 1 point basis; continuous from the starting number (Note) Configurable on 2 points basis; continuous from the starting number (Note) Configurable on 16 points basis
(Note)
Note: The configuration range of each of shared and extended shared relays (E) and shared and extended shared registers (R) to be latched in case of power failure is assigned numbers continuous from the starting number. However, if the number of shared relays (E) is smaller than 2048, the last of them is followed by the first extended shared relay (E) numbered E2049. Likewise, if the number of shared registers (R) is smaller than 1024, the last of them is followed by the first extended shared register (R) numbered R1025. Example) In a case where there are 1024 shared relays (E) and 2048 extended shared relays (E): If you define the starting number as 513 and the number of units as 1024 for the range of devices to be latched in case of power failure, then the devices that are latched include: E513 to E1024 shared relays (E); and E2049 to E2560 extended shared relays (E). Note: The configuration range of each of link relays (L) and registers (W) to be latched in case of power failure is assigned numbers continuous from the starting number. However, the following exceptions apply. The number following L/W01024 is L/W11024. The number following L/W11024 is L/W21024. The number following L/W21024 is L/W31024. The number following L/W31024 is L/W41024. The number following L/W41024 is L/W51024. The number following L/W51024 is L/W61024. The number following L/W61024 is L/W71024. (The rules noted above are true when the number of link relays (L) or registers (W) to be used is defined as 1024. If the number is 2048, the number following L/W02048 is L/W10001.) Example) When there are 1024 link relays (L) each for link 1, link 2 and link 3: If you define the starting number as 10513 and the number of units as 1024 for the range of devices to be latched in case of power failure, then the devices included in the latching are: L10513 to L11024 link relays (L) for link 1; and L20001 to L20512 link relays (L) for link 2.
IM 34M6P13-01E
1-12
Table 1.10 Configuration Range (4/5)
F3SP28-3N/-3S F3SP53-4H/-4S F3SP38-6N/-6S F3SP58-6H/-6S F3SP59-7S Item Initial data for data register (D) Scan time monitoring time Constant scan time I/O module error I/O comparison error Instruction processing error Scan time exceeded Subroutine error Interrupt error Sub-unit communications error Sensor control block scan timeout Data register (D) Default None 200ms Unused Stop Stop Stop Stop Stop Stop Run Stop All Blocks Specified Blocks Run or Stop (user-definable) Configuration Range Configurable for up to 1024 contiguous points from a starting number Configurable from 10 to 200 ms on 10 ms basis Configurable from 1.0 to 190.0 ms on 0.1 ms basis
Enabled only if F3PU10-0N F3PU16-0N Momentary power F3PU20-0N F3PU26-0N or failure detection mode F3PU30-0N Power supply module is used Peripheral management (minimal operation) time Execution span Sensor control block Setup interrupt Input module interrupt handling Timing of interrupt Timing of interrupt
Standard
Standard or Immediate
Not Setup 200s Immediate (during instruction execution) After Instruction Sensor control block interrupt has priority Use BIN 16ms Reset None
100s to 190ms on 100s basis 200s to 25.0ms on 100s basis Immediate or After Instruction Immediate or After Instruction Sensor control block has priority or input module interrupt has priority Use/Do Not Use/Use in sensor control block; configurable on 16 points basis BIN/BCD; configurable on 16 points basis 16ms/1ms/250s/62.5s/constant; configurable on 16 points basis Reset/Hold; configurable on 16 points basis Up to 32768 contiguous points from a starting number
Priorities of sensor control block and input module interrupts Use and non-use of modules Setup DIO module Data code Input sampling interval Reset/Hold of external outputs when sequence stops Device current values Data registers (D) to be resident in ROM File registers (B)
Setup ROM
(Note) Configure on 32 points basis when using the same input module for both sensor control blocks and regular blocks.
SEE ALSO
Instruction manual (IM34M6H45-01E), Fiber-optic FA-bus Module, Fiber-optic FA-bus Type 2 module, for more information on the subunit line failure.
IM 34M6P13-01E
1-13
Table 1.11 Configuration Range (5/5)
F3SP28-3N/-3S F3SP53-4H/-4S F3SP38-6N/-6S F3SP58-6H/-6S F3SP59-7S Item Default Configuration Range Mode 0: 9600bps, even parity Mode 1: 9600bps, no parity Mode 2: 19200bps, even parity Mode 3: 19200bps, no parity Mode 4: 38400bps, even parity Mode 5: 38400bps, no parity Mode 6: 57600bps, even parity Mode 7: 57600bps, no parity Mode 8: 115200bps, even parity Mode 9: 115200bps, no parity Unused/Used Yes/No Yes/No Yes/No Yes/No Link number from 1 to 8 Slot numbers from 1 to 16 Run/Stop, configurable for shared relays(E) , shared registers(R) , extended shared relays (E), extended shared registers (R) of each CPU Yes/No Peripheral process /Control process
Mode
Setup FA link system (Mapping between FA link and FL-net numbers and slot numbers)
Range for shared refreshing (partial stop) Shared refreshing Simultaneity of shared refreshed data Mode of shared refreshing (control process)
IM 34M6P13-01E
1-14
1.2.4
RDY (= READY, green) --------------------On = Normal Off = Major failure RUN (= RUN, green) ---------------------- On = Program in progress Off = Program at a stop ALM (= ALARM, yellow) ------------------ On = Minor failure Off = Normal ERR (= ERROR, red) --------------------- On = Moderate failure Off = Normal
PROGRAMMER
Major failure --------------- The CPU module is inoperable due to a hardware failure. Moderate failure ----------The CPU module cannot run or continue to run a program. Minor failure --------------- The CPU module still can run or continue to run a program though it has detected a failure. Programming tool connector ------------------------ Connected to a personal computer or handy programming console. A personal computer or a monitor can be connected to this connector when the personal computer link function is in use.
F010201.EPS
Table 1.6 summarizes combinations of the LED indicators as classified by the severity of failure.
Table 1.12 LED Indicator Combinations Based on the Severity of Failure
Status LED Indicator RDY RUN ALM ERR
: ON, : OFF,
Normal
Major Failure
Moderate Failure
Minor Failure
: ON or OFF
Weight
130g 210g
IM 34M6P13-01E
1-15
1.2.5
External Dimensions
F3SP28 F3SP38 mm Unit: mm
83.2 2
28.9
100
F010202.VSD
100
F010203.VSD
IM 34M6P13-01E
1-16
1.3
Basic Configuration
This section describes units, slot numbers and I/O relay numbers which form the basic configuration of an FA-M3. Units, slots, and input/output relays are identified with unique numbers. These numbers are used in parameters of ladder instructions and configuration setup.
1.3.1
Unit
A unit is a system with the minimum configuration consisting of the following modules. Install these modules on the base module to compose the unit.
Table 1.14 Unit Components (Modules)
Name Base module Power supply module CPU module I/O module Special module Description Five types are available depending on the number of modules to the mounted. One power supply module must always be mounted on the base module. At least one CPU module is required. Several types are available depending on the functionality. Various types are available depending on the type of I/O and the number of I/O points. Various types are available, including analog I/O and communication modules.
I Main Unit
Install the power supply module in the leftmost slot of the base module and the CPU module in the slot on the immediate right of the power supply module. Then, install required I/O and special modules in the remaining slots. A system with this configuration is called a main unit.
CPU module
I Subunit
A subunit is an I/O expansion unit. It is connected to the main unit through a fiber-optic FA-bus or fiber-optic FA- bus type 2. A maximum of seven subunits can be connected to the main unit and are identified by their unit numbers. With fiber-optic FA-bus type 2, you can separate any single subunit into a maximum of eight stations. For more information on the method of separation, see the instruction manual (IM34M6H45-01E), Fiber-optic FA-bus Module, Fiber-optic FA-bus Type 2 Module.
See Also
For details on unit numbers, see Section 1.3.2.
IM 34M6P13-01E
1-17
1.3.2
Slot Number
A slot number indicates the position of a slot where a module is installed. The slot number is defined as a three-digit integer, as shown below.
Slot number
Slot positions 01 to 16 are assigned to the slot on the immediate right of the power supply module through to the rightmost slot of a base module. Unit number Main unit = 0 Subunit = 1 to 7
F010302.EPS
IM 34M6P13-01E
1-18
Fiber-optic FA-bus type 2 module (can be installed in any position) FA-M3 main unit
001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016
CPU module
105 106 107 108 109 110 111 112 113 114 115 116
Install fiber-optic FA-bus type 2 modules in both the main unit and a subunit and connect these modules with a fiber-optic cable. You can attach up to seven subunits to the main unit. Subunit numbers are determined by setting the rotary switch on the front panel of each fiber-optic FA-bus type 2 module.
IM 34M6P13-01E
1-19
1.3.3
001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016
Slot numbers
Y 08-
OUT
F3YC08-0N
F010304.EPS
The input and output terminal numbers of a mixed-I/O module or multifunctional module with 32 input and output points each are assigned as 1 to 32 and as 33 to 64, respectively.
IM 34M6P13-01E
Blank Page
2-1
2.
2.1
System Configuration
This chapter describes the FA-M3 system configuration and programming tools.
Figure 2.1 Example of Basic System Configuration (when a 13-slot base module is used)
2.2
2.2.1
TIP
A BASIC CPU module refers to a CPU module which is controlled by BASIC programs.
IM 34M6P13-01E
2-2
Main CPU module
Slot numbers
F020201.EPS
CAUTION
Be careful not to install any CPU module in the 5th or later slot and turn on the power. Otherwise, the memory is cleared and reverts to the factory settings.
IM 34M6P13-01E
2-3
SEE ALSO
For details on unused modules, see Section 4.1.4.
IM 34M6P13-01E
2-4
2.3
2.3.1
Main unit
Subunit
Fiber-optic cable
Subunit
F020302.EPS
IM 34M6P13-01E
2-5
2.3.2
2.3.3
FA Link System
The FA link system refers to a system that employs FA link communication to build a network system with programmable controllers. The types of communication covered by an FA link system are: - FA link H communication (FA link H module), and - Fiber-optic FA link H communication (fiber-optic FA link H module). Unless otherwise specified, the term FA link in this manual comprehensively refers to these two types of communication. For more information on the FA link, see the instruction manual (IM34M6H43-01E), FA Link H and Fiber-optic FA Link H Modules.
IM 34M6P13-01E
2-6
2.4
Programming Tool
The FA-M3 programming tool WideField2, or simply WideField2, is available as a programming tool for the F3SP28, F3SP38, F3SP53, F3SP58 and F3SP59 sequence CPU modules.
2.4.1
WideField2
Description Software Model Compatible Sequence CPU Modules F3SP05 F3SP38 F3SP08 F3SP53 F3SP21 F3SP58 F3SP25 F3SP59 F3SP28 F3FP36 F3SP35
SF620- JCW
Personal computer
F020401.EPS
I Object Ladder
WideField2 defines blocks and instruction macros that compose a ladder program as objects, a term commonly used in the computing world. The object-oriented ladder language assumes responsibility for a given function and features a high degree of independence. Consequently, the language offers higher productivity, better maintainability and more effective program reuse, as compared to a structured programming language.
IM 34M6P13-01E
2-7
G Index View
You can view the overall range of even a large-size program by hiding its unnecessary part. This makes debugging more efficient.
Material feed
I***** I***** I***** Y*****
Initialization Idling Material feed Preheating Flux coating Finish coat Fixation heating Cleaning Cooling Unloading Fault-diagnosis Power-off sequence
Initialization Idling
I***** MOVE
Preheating
I***** I***** I***** Y*****
I***** I*****
Y*****
I***** I*****
Y*****
Flux coating
I***** I***** I***** Y*****
Flux coating Finish coat Fixation heating Cleaning Cooling Unloading Fault-diagnosis Power-off sequence
I***** I*****
Y*****
Y*****
I*****
Y*****
F020402.EPS
MCN1 MCN1.SWICH MCN1.POMP MCN1.OUT MCN2.SWICH MCN2.POMP MCN3.OUT MCN3.SWICH MCN3.POMP MCN3.OUT MCN2 MCN3
F040403.EPS
IM 34M6P13-01E
Blank Page
3-1
3.
3.1
I Run Mode
The Run mode is a state in which the sequence CPU module is running a program, and is used for practical system operation. You can monitor the operating status of a sequence CPU module or devices. However, you can use none of the debug functions available from the WideField2 programming tool. In this mode, the RDY and RUN LED indicators come on.
I Debug Mode
The Debug mode is used to debug and tune programs. You can execute programs in the same way as with the Run mode. In the Debug mode, you can use debugging functions, such as forced SET/RESET instructions and online editing, through the WideField2. These functions affect the scan time, however. Disable the functions when debugging and tuning are complete, and set the CPU to the Run mode. In this mode, the RDY and RUN LED indicators turn on. The Debug mode includes a pause state in which the sequence CPU module suspends program execution during such debugging operation as scan operation. In this state, the RUN LED indicator turns off and all external outputs being generated by the program are latched.
I Stop Mode
The Stop mode is a state in which the sequence CPU module stops program execution. In the Stop mode, you can remove programs and clear devices, in addition to using forced SET/RESET instructions, online editing and debug operation. In this mode, the RUN LED indicator turns off. The external outputs being generated by the program are set to ON (hold) or OFF (reset), according to the Output When Stopped setting of the Setup DIO item in the configuration. All of the external outputs are set to OFF if the option has not been set up during configuration.
Figure 3.1 LED Indicator Combinations Based on the Operation Mode
Operation Mode LED Indicator RDY RUN ALM ERR
: ON, : OFF, : ON or OFF
Run
Debug
Stop
IM 34M6P13-01E
3-2
3.2
3.2.1
Operation at Power-on/off
This section describes the operations when power is turned off or turned on.
Operation at Power-on
When the power is turned on, the CPU performs an initialization process to make itself ready for program execution. In the initialization process, the CPU performs I/O collation and instruction analysis in order to check that its hardware and programs are normal. The CPU begins program execution from the first step of a program when no error is found. If equipped with a ROM pack, the CPU reads programs from the pack and begins system operation. If in the ROM Writer mode, however, the CPU does not read programs from the ROM pack. Alternatively, it enters a command-wait state (e.g., waits for a ROM transfer command from the WideField2 ) without executing a program.
Power-on
NO
Equipped with ROM pack? YES Read programs from ROM pack
Program diagnosis NO
No error? Wait for command YES Start program The RUN LED indicator turns on.
IM 34M6P13-01E
3-3
3.2.2
Operation at Power-off
When the power is turned off, the sequence CPU module records the date and time in its error log file and stops system operation.
TIP
Error log files allow you to save information such as time of occurrence and type of error when a system error occurs or when the power is turned on or turned off.
SEE ALSO
For details on error logs, see Chapter 18 of FA-M3 Programming Tool WideField2 Instruction Manual (IM34M6Q15-01E).
IM 34M6P13-01E
3-4
3.3
3.3.1
I Standard Mode
If a momentary power failure occurs, the sequence CPU module records the date and time in its error log file. The sequence CPU module suspends processing until it recovers from the power failure. This causes a delay in the scan time and timer update process. When the power has recovered, the sequence CPU module restarts at the point where it suspended processing. A program can cope with a momentary power failure since its occurrence is reflected on a special relay (M195).
AC voltage Power failure detection level Program execution Interruption
F030301.EPS
IM 34M6P13-01E
3-5
3.3.2
CAUTION
For a multi-CPU configuration, the immediate detection mode must be set for none or all CPU modules.
IM 34M6P13-01E
3-6
3.3.3
TIP
Latching devices at power failure stores device states immediately before a power failure so that a program can continue execution in the same state after power is restored.
3.3.4
Timer (T)
Counter (C) Data register (D) Shared and extended shared registers (R) Link register (W)
*1:
*2:
If the upper limit of the range of shared relays (E) to be used is smaller than E2049, the last of their numbers is followed by the first of the extended shared relay (E) numbers. Likewise, if the upper limit of shared registers (R) to be used is smaller than R1025, the last of their numbers is followed by the first of the extended shared register (R) numbers. The configuration ranges of link relays and registers to be latched in case of power failure are assigned numbers continuous from their starting numbers. However, the following exceptions apply. The number following L/W01024 is L/W10001. The number following L/W11024 is L/W20001. The number following L/W21024 is L/W30001. The number following L/W31024 is L/W40001. The number following L/W41024 is L/W50001. The number following L/W51024 is L/W60001. The number following L/W61024 is L/W70001. These rules are true when the number of link relays or registers to be used is defined as 1024 (default). If the number is 2048, the number following n2048 is n0001. If the number us 8192, the number following 08192 is 10001.
IM 34M6P13-01E
3-7
3.4
Computation Method
This section outlines data computation (scan processing) in the sequence CPU module. Details are explained in subsequent sections. The CPU employs a stored-program iterative computation method. In this method, a created program is pre-stored in the memory of the sequence CPU module. The sequence CPU executes instructions, one at a time, starting from the first step of the program. After executing the last step in the program, the CPU performs required processing, such as self-diagnosis. It then repeats the instructions from the first step. Each of these iterative cycles is called one scan and the time required for one scan is called a scan time. In the case of F3SP28, F3SP38, F3SP53, F3SP58 and F3SP59 CPU modules, the CPU executes instructions and peripheral processes concurrently to perform each scan in a shorter time. Common processing, instruction execution, input refreshing, output refreshing, and synchronization processing are classified as a system of control-related processes, while tool service, personal computer link service, CPU service, link refreshing, and shared refreshing are classified as a system of peripheral processes. The CPU performs these two kinds of processes concurrently to speed up the control-related processes.
Peripheral processes Common processing Input refreshing Output refreshing Instruction execution Execution interrupt Peripheral processes are performed within this time range.
Fixed interval
Input refreshing for sensor control block Program execution for sensor control block Output refreshing for sensor control block Input refreshing for sensor control block Program execution for sensor control block Output refreshing for sensor control block
Shared refreshing
Link refreshing Command processing Tool service Link service CPU service
One scan
Synchronization processing If synchronization processing begins, any peripheral process is interrupted temporarily and resumes at the next scan.
SEE ALSO
See Section 6.15, Sensor Control Function, for more information on the sensor control function.
TIP
Common processing includes self-diagnosis, updating of special relays (M) and special registers (Z), as well as updating of timers. The END processing is sometimes known as an END scan.
IM 34M6P13-01E
3-8
TIP
The input refreshing process reflects data from input contacts of, say a DI module, to input relays (X). The output refreshing process reflects data from output relays (Y) to output contacts of, say a DO module.
TIP
The synchronization process synchronizes the system of control processes with the system of peripheral processes. In particular, it reflects data to the link refresh and shared refresh (intra-PLC communication) devices.
CAUTION
If the ratio of the instruction execution time to the scan time is too small, you may fail to secure a time long enough to execute the system of peripheral processes. Consequently, the responses of link refreshing, shared refreshing, tool service, personal computer link service and CPU service will become extremely slow. If this happens, use a constant scan with an interval somewhat longer than the normal scan time, or define the peripheral processing time to secure a time long enough to execute the system of peripheral processes.
IM 34M6P13-01E
3-9
3.5
Synchronization processing
F030501.EPS
IM 34M6P13-01E
3-10
I Peripheral Processing (Minimum Operating) Time
You can configure the peripheral processing (minimum operating) time. Use this configuration item when the instruction execution time is so short that you cannot allocate enough time to peripheral processes. To secure enough time, the scan time is lengthened, or the delays of shared refreshing, link refreshing and command processing included in the peripheral processes are shortened. If at the end of instruction execution, any peripheral process proves to have not run as long as the preset time, the process is prolonged until the expiry of the preset time. In that case, the scan is also prolonged by as much as the extended portion of the preset time. Note that the CPU ignores the peripheral processing (minimum operating) time if a constant scan is predefined.
Common processing Input refreshing Output refreshing Instruction execution Peripheral processing Wait Synchronization processing
F030502.EPS
The configurable range is from 0.1 ms to 190 ms, on 0.1 ms basis. If you do not define a peripheral processing (minimum operating) time, the CPU operates with the peripheral processing time of 0.2 ms.
IM 34M6P13-01E
3-11
3.6
3.6.1
External input instrument Input refreshing CPU's data memory Input-relay (X) area
Execution of computations
IM 34M6P13-01E
3-12
3.6.2
Response Delay
The maximum response delay of the output module against a change in the input module is two scans. For more information, see Chapter 7, I/O Response Time Based on Scan Time.
External input instrument is turned on
X00502 "ON"
Y00602
"ON"
Instruction execution
Instruction execution
IM 34M6P13-01E
3-13
3.6.3
SEE ALSO
Subsection 2.2.2, Handling I/O Modules in Multi-CPU System, and subsection 4.1.4, I/O Module Setting, for information on the parameters set for I/O modules and their limitation of use.
Power supply module Slot numbers Add-on CPU modules (sequence CPU or BASIC CPU modules)
F030603.EPS
IM 34M6P13-01E
3-14
3.7
3.7.1
Tool Service
Tool services execute commands sent from the FA-M3 programming tool WideField2. Since the tool service runs concurrently to the execution of instructions, it does not affect the scan time. The CPU does not execute the tool services if there is no command to be processed.
Monitor display X00503 Personal computer X00501 X00502 X00503 Upload Download Y00601 X00504 Y00602
Power supply module Sequence CPU module Sequence CPU Peripheral processes Common processing Input refreshing Output refreshing Instruction execution Shared refreshing
Link refreshing Command processing Tool service Link service CPU service
Synchronization processing
F030701.EPS
IM 34M6P13-01E
3-15
3.8
3.8.1
Power supply module Personal computer link module Sequence CPU Peripheral processes Common processing Input refreshing Output refreshing Instruction execution Shared refreshing
Link refreshing Command processing Tool service Link service CPU service
Synchronization processing
F030801.EPS
IM 34M6P13-01E
3-16
3.9
3.9.1
F030901.EPS
IM 34M6P13-01E
3-17
Figure 3.12 shows an example of shared refreshing carried out between a sequence CPU module and an add-on CPU module. In this example, shared relays and registers are allocated as shown below. - Sequence CPU module: Shared relays (E)= E0001 to E0512 (Slot-1 CPU) Shared registers (R) = R0001 to R0256 - Add-on CPU module: Shared relays (E)= E0513 to E1024 (Slot-2 CPU) Shared registers (R) = R0257 to R0512
SLOT1 CPU
Shared refreshing
SLOT2 CPU
F030902.EPS
IM 34M6P13-01E
3-18
3.9.2
F030903.EPS
If data need not be shared among add-on CPU modules, the refreshing interval of CPU2, CPU3 or CPU4 is reduced if CPU3 and CPU4, CPU2 and CPU4 or CPU2 and CPU3 are excluded from shared refreshing.
TIP
If you exclude the local CPU module from shared refreshing, the scan time reduces because the local CPU modules data updating done by the synchronization process is disabled. This prohibits data in all areas of other CPU modules from being shared, however.
IM 34M6P13-01E
3-19
I Mode of Shared Refreshing (Change to Control-related Process)
You can change by configuration the mode of shared refreshing, which updates the data of relays (E) and registers (R) shared with other CPUs, so that it works as a controlrelated process. Include shared refreshing in peripheral processes if the scan time is important. Alternatively, include it in control-related processes if the speed of exchanging shared data is important.
Common processing Input refreshing Output refreshing Instruction execution One scan Shared refreshing
Link refreshing Command processing Tool service Link service CPU service
Synchronization processing
F030904.EPS
Common processing Input refreshing (including shared refreshing) Output refreshing Instruction execution One scan
Link refreshing Command processing Tool service Link service CPU service
Synchronization processing
F030905.EPS
If you execute shared refreshing as a control-related process, the scan time lengthens. This however enables you to execute shared refreshing without being affected by link refreshing or the command processing time.
IM 34M6P13-01E
3-20
TIP
- Sequence of Shared Refreshing For a main CPU, shared refreshing is executed in the order of CPU2s shared relays(E) /registers(R), CPU2s extended shared relays(E) /registers(R), CPU3s shared relays(E)/registers(R), CPU3s extended shared relays(E) /registers(R), CPU4s shared relays(E) /registers(R), and CPU4s extended shared relays(E) /registers(R). - When the configuration item Mode of Shared Refreshing is set to Peripheral Process Each single scan of peripheral processing refreshes the CPUns shared relays(E) /registers(R) or extended shared relays(E) /registers(R). The data that has been read is reflected in device areas during the synchronization process occurring after the completion of shared refreshing. Note however that in a case where the configuration item Simultaneity of Shared Refreshed Data is set to Yes, refreshing may be delayed by as much as three scans of peripheral processing due to the need for synchronization with the CPUn. - When the configuration item Mode of Shared Refreshing is set to Control-related Process Each single scan of control-related processing refreshes the CPUns shared relays(E) /registers(R) or extended shared relays(E) /registers(R). Note however that when the configuration item Simultaneity of Shared Refreshed Data is set to Yes, refreshing may be delayed by as much as three scans due to the need for synchronization with the CPUn. - Reference to Local CPUs Write Area You can read data in the local CPUs write area from other CPUs. That is, you can read the data alternately from shared relays(E) /registers(R) and from extended shared relays(E) /registers(R) in that area during the synchronization process of each scan. Note however that when the configuration item Simultaneity of Shared Refreshed Data is set to Yes for any of the other CPUs, refreshing may be delayed by as much as the slowest of those CPUs scans due to the need for synchronization with that CPU.
CPU2 Shared refreshing of shared relays/registers CPU2 Shared refreshing of extended shared relays/registers CPU3 Shared refreshing of shared relays/registers Refreshing may be delayed by three scans of peripheral processing due to the simultaneity of data
Instruction execution
Instruction execution
Instruction execution
Instruction execution
With this common processing, it becomes possible to alternately refer to the shared relays/registers and extended shared relays/registers of the local CPU from other CPUs. (Refreshing may be delayed by as much as the slowest of these CPUs' scans due to the simultaneity of data.) One scan One scan One scan One scan
F030906.EPS
Data updates are reflected by this common processing Instruction execution Instruction execution
Instruction execution
Instruction execution
One scan
With this common processing, it becomes possible to alternately refer to the shared relays/registers and extended shared relays/registers of the local CPU from other CPUs. (Refreshing may be delayed by as much as the slowest of these CPUs' scans due to the simultaneity of data.) One scan One scan One scan
F030907.EPS
IM 34M6P13-01E
3-21
SEE ALSO Tables 3.3 and 3.4 show examples of how shared refreshing affects the scan time. For more information, see Section 7.1, Information on Scan Time.
These examples assume that both CPU1 and CPU2 have 512 shared relays and 512 shared registers. Table 3.3 Durations of Interference by Shared Refreshing as a Peripheral Process with the Scan Time
Duration of Duration of Interference with Scan Synchronization Time (= Duration of Processing Synchronization Processing) 1.138ms 1.138ms 1.138ms 1.138ms Duration of Interference with Scan Time of Peripheral Processing (=Duration of Shared Refreshing) 0.916ms 3.908ms
Remote CPU
F3SP28/38/53/58/59 F3SP21/25/35
Table 3.4 Durations of Interference by Shared Refreshing as a Control-related Process with the Scan Time
Duration of Interference with Scan Time (= Duration of Extended Shared Refreshing plus Duration of Shared Refreshing) 1.782ms 4.774ms Duration of Interference with Scan Time of Peripheral Processing 0ms 0ms
Remote CPU
F3SP28/38/53/58/59 F3SP21/25/35
0.916ms 3.908ms
0.866ms 0.866ms
IM 34M6P13-01E
3-22
3.9.3
CPU Service
CPU services exchange data and process commands between the sequence CPU and a BASIC CPU. Since processed concurrently with the execution of instructions, the CPU services do not affect the scan time. The sequence CPU does not execute the CPU services unless it receives commands to be processed, such as ENTER or OUTPUT, from the BASIC CPU.
Sequence CPU Peripheral processes Common processing Input refreshing Output refreshing Instruction execution Shared refreshing
Link refreshing Command processing Tool service Link service CPU service
Synchronization processing
F030908.EPS
IM 34M6P13-01E
3-23
F3LP
F3LP
F3LP
Link relays
Link registers
F031001.EPS
SEE ALSO
See FA Link H Module F3LP02-0N, Fiber-optic FA Link H Modules F3LP12-0N (IM34M6H43-01E) for more information on link data updating and link refreshing.
IM 34M6P13-01E
3-24
Link refreshing
Station 1
Link refreshing
Link refreshing
Station n
L00003
F031002.EPS
IM 34M6P13-01E
Shared refreshing
Link refreshing
Synchronization processing
F031003.EPS
Link refreshing updates the link relays(L) /registers(W) of FA link 1 to FA link 8 in each cycle of peripheral processing.
Link relays/registers of FA link 1 Link relays/registers of FA link 2 Link relays/registers of FA link 3
Results of link refreshing are reflected by this common processing. Instruction execution Instruction execution Instruction execution Instruction execution
One scan
One scan
One scan
One scan
F031004.EPS
TIP
Tables 3.5 shows an example of how link refreshing affects the scan time. For more information, see Section 7.1, Information on Scan Time.
Table 3.5 Durations of Interference by Link Refreshing with the Scan Time
Number of Link Devices Example 1 Example 2 Link relay = 1024 units Link register = 1024 units Link relay = 2048 units Link register = 2048 units Duration of Interference with Scan Time 3.314ms 6.578ms Duration of Interference with Scan Time of Peripheral Processing 16.38ms 32.7ms
IM 34M6P13-01E
3-26
3.11
3.11.1
Interrupt Processing
The sequence CPU module detects the rising edge of an interrupt input from an input module and executes an input interrupt program. You can register a maximum of four interrupt programs with the sequence CPU module using an interrupt instruction (INTP instruction.) The module can accept a maximum of eight interrupts at the same time. Interrupt programs are executed in the order in which their interrupt factors occur. If any interrupt factor occurs during execution of an interrupt program, the factor is processed when the interrupt program finishes.
Interrupt factor 1
Interrupt factor 2
F031101.EPS
CAUTION
Do not register any interrupt program intended for a particular input module with two or more CPU modules. This is because the modules may fail to execute interrupt processing. Do not use a TIMER instruction in any interrupt program because the instruction may not work correctly.
IM 34M6P13-01E
3-27
Occurrence of interrupt X00503 X00501 No interrupt pro grams are executed in this interval. I0002 X00502 I0003
DI Y00603 I0004
EI
INTP
X00301
IRET
F031102.EPS
IM 34M6P13-01E
3-28
OUT LD
BMOV
Execution of input interrupt program (Part between INTP and IRET instructions) Next instruction
F031103.EPS
Figure 3.30 Execution of Interrupt Program after the Completion of Instruction Execution
IM 34M6P13-01E
3-29
Execution of normal programs LD OUT LD BMOV Execution on input interrupt programs
F031104.VSD
Does not include the response time of an input module. For information on the response time of each input module, see the instruction manual (IM34M6C11-01E), Range-free Multi-controller FA-M3 - Hardware. For information on the instruction processing time, see the explanation of the instruction processing time given in the appendix of the instruction manual (IM34M6P12-03E), Sequence CPU Modules - Instructions. 120 s for F3SP28 and F3SP38 modules and 100 s for F3SP53, F3SP58 and F3SP59 modules. See Section 7.1, Information on Scan Time.
IM 34M6P13-01E
3-30
CAUTION
G
Output of Data by Interrupt Programs, Which Are Executed Immediately during Instruction Execution, to Relays Be careful when outputting data to relays using such an instruction as OUT, SET or RST in a case where interrupt processing is applied along with the timing option Immediately during instruction execution. That is, do not output data in a normalscan program to any of the relays numbered 1 to 16 if you have already output data in an interrupt program to any of these relays (there is no limitation on inputting data, however). See the programming example given below. Example) Interrupt program: OUT I2 Normal-scan program: OUT I1 - Not allowed. OUT I17 - Allowed. The same rule applies to relays numbered 17 to 32, 33 to 48, 49 to 64, and so on. If you have included such an output instruction in both the interrupt program and normal-scan program, the CPU may not output data to the relay in question.
CAUTION
G
Simultaneity of Multiple Devices in Interrupt Programs Executed Immediately during Instruction Execution There is no simultaneity of data for multiple devices in the case of executing an interrupt program whose timing option is Immediately during instruction execution. The time the simultaneity of data is required is when multiple devices data is exchanged between a normal-scan program and an interrupt program using a block transfer instruction (BMOV), a long-word instruction containing a IEEE singleprecision floating point instruction, or two or more instructions. For example, consider the case shown in Figure 3.30 where an interrupt program is executed when a block transfer instruction (BMOV) in a normal-scan program is in progress; in which case, there is a risk that data under block transfer is rewritten before and after the execution of the interrupt program. If the simultaneity of data is required when executing an interrupt program whose timing option is Immediately during instruction execution, follow either of the two instructions given below. 1. Use DI (prohibition of interrupt) and EI (cancellation of interrupt prohibition) instructions to prevent any interrupt program from being executed when exchanging data of multiple devices. 2. Use an application program to carry out flag control using relays between a normal-scan program and an interrupt program.
IM 34M6P13-01E
3-31
CAUTION
G
Simultaneity of Refresh Data in Interrupt Programs Executed Immediately during Instruction Execution If you select the timing option Immediately during instruction execution for an interrupt program, the program is executed even during synchronization processing, input refreshing or common processing. If the program is executed during synchronization processing or input refreshing, it is possible for you to read devices (I/O relays (X/Y), shared and extended shared relays (E), shared and extended shared registers(R), and link relays and registers (L/W)) which are being refreshed. If you rewrite these devices by the interrupt program, the simultaneity of data is lost before and after the execution of the program. To prevent any interrupt program from being executed during synchronization processing, input refreshing and common processing, execute a DI instruction at the end of a normal-scan program. In combination with this instruction, execute an EI instruction at the start of the normal-scan program.
IM 34M6P13-01E
3-32
CAUTION
The sequence CPU follows the rules of execution timing (after completion of instruction execution or immediately during instruction execution) discussed above, even when the execution of the sensor control block or interrupt process is aborted due to the interrupt priority.
IM 34M6P13-01E
4-1
4.
Devices
This chapter describes the types and functions of devices available with the sequence CPU modules. Relay devices are accessed on a one-bit basis. Thus a relay device number corresponds to a bit. Register devices are accessed on a 16-bit basis. Thus a register device number corresponds to 16 bits.
4.1
4.1.1
= Slot number = Unit number (0 to 7) = Slot position (01 to 16) =Terminal number (1 to 64)
X00502 X00501 X00503 X00501 X00502 X00504 X00502 X00503
F040101.VSD
IM 34M6P13-01E
4-2
4.1.2
4.1.3
Relay numbers
X00201 to X00232 1
Empty slot 64 relays
X00301 to X00332 2 3
Empty
Y00401 to Y00432 4 5
Empty
5 Y32
CPU X64
64 relays
Relay numbers
X00201 to X00264
X00301 to X00332
Y00501 to Y00532
F040103.EPS
IM 34M6P13-01E
4-3
4.1.4
SEE ALSO
For details on Sensor Control CB (senor control block), see Section 6.15.
CAUTION
When using output modules or advanced modules with output modules or Y output relays(Y) in multi-CPU system configuration Cases where F3SP28, F3SP38, F3SP53, F3SP58 and F3SP59 CPU modules are combined You can output data from multiple sequence CPU modules separately to the output relays (Y) of the same output module in increments of 16 relays. To do this, set the unused output terminals to the option Do not Use in increments of 16 terminals. Cases where CPU modules other than those noted above are combined It is not possible to use the same output module with multiple CPUs. Configure the CPU that does not use the output module so that the output module is set to Do not Use.
CAUTION
- When using the sensor control block (CB) When using an input or output module in the sensor control block, configure: - the input module in units of long words (i.e., 32 relays and 32 terminals - terminals 1 to 32 or 33 to 64); and - the output module in units of words (i.e., 16 relays and 16 terminals). Now, lets consider a case where you have made a mistake configuring the input module in units of words (for example, you have set terminals 1 to 16 to the option Used [for normal scans] and terminals 17 to 32 to the option Use in Sensor CB). Since input refreshing is performed in units of long words, input (X) relays used under a normal scan are refreshed by the Refresh instruction of the sensor control block when the normal scan is in progress. Consequently, the simultaneity of data is not guaranteed before and after the refreshing. The simultaneity of data is also not guaranteed for input (X) relays used in the sensor control block.
IM 34M6P13-01E
4-4
CAUTION
When using a Direct Refresh (DREF) instruction
Set the output relays (Y) to be refreshed in a DREF instruction of a program to the option Do not Use. If you set them to the option Use or Use in Sensor CB, the values one scan earlier may be overwritten with the values output by the DREF instruction because of the timing of output refreshing that is executed concurrently with the instruction.
CAUTION
If a single input module (or advanced module with input relays X ) is used with two or more CPU modules in multi-CPU system configuration, configure the CPUs so that they share the same sampling interval for that input module. (Also re-configure any CPU whose input relays (X) were set to the option Do not Use, so that their settings become equal to those of other CPUs.) Otherwise, system operation may become unstable.
IM 34M6P13-01E
4-5
I Holding/Resetting Output Relays When a Program Stops
Determine whether the output relays (Y) of an output module (or multifunctional module with output relays Y ) should be placed in a Hold state or Reset state when a program stops (due to a moderate or major failure or a change to stop mode). The setting of this configuration for a stop of programs due to a major failure is not effective for some output modules, however. Refer to the data item output in case of stop of programs in the specifications section of each individual output module discussed in Hardware Manual (IM34M6C11-01E). For a multifunctional module, the setting for a stop of programs due to a major failure is always ineffective. By default, all output modules are set to the option Reset. You can perform this configuration in increments of 16 relays.
CAUTION
When using output modules or advanced modules with Y relays in multi-CPU system configuration output
Cases where F3SP28, F3SP38, F3SP53, F3SP58 and F3SP59 CPU modules are combined You can output data from multiple sequence CPU modules separately to the output relays of the same output module in increments of 16 relays. To do this, configure the sequence CPU modules so that all of them share the same output mode, either the Hold or Reset option. (Also re-configure any sequence CPU modules whose output relays were set to the option Do not Use, so that their settings become equal to those of local sequence CPU modules.) Cases where CPU modules other than those noted above are combined It is not possible to share the same output module with multiple CPUs.
IM 34M6P13-01E
4-6
4.2
Internal Relays (I), Shared Relays (E) and Extended Shared Relays (E)
This section describes internal relays (I), shared relays (E), and extended shared relays (E). Internal relays (I) are 1-bit variables that can be used without restriction in a program. Shared relays (E) and Extended Shared relays (E) are 1-bit variables that can be used to perform data communications between CPUs in a multi-CPU system.
4.2.1
With the configuration function, you can configure a range of internal relays to determine whether or not they retain computation results when the power is turned off. If you set the internal relays so as not to retain computation results, they are cleared to OFF (0) when you: - turn off the power once and turn it on again; - change the operation mode to Run or Debug with the WideField2; or - send a Clear Device command from WideField2. If you set the internal relays so as to retain computation results, they retain those until power-off. In this case, the relays are cleared to OFF (0) when you send a Clear Device command from the programming tool. - send a Clear Device command from WideField2.
IM 34M6P13-01E
4-7
4.2.2
CAUTION
If you write data to a device area other than that of the local CPU, information held by shared and extended shared relays (E) of remote CPUs are overwritten. This results in a failure for these shared relays to reflect the correct results of computation. By default, no shared relays are assigned as devices. When using add-on CPU modules, set the range of shared relays to be used. Assign the same range for all of the CPU modules. Otherwise, the shared relays (E) are not correctly refreshed.
IM 34M6P13-01E
4-8
Figure 4.5 shows an example of how specific shared relays are shared if you allocate shared relays E0001-0512 to CPU1 and E0513-1024 to CPU2.
CPU1 I0001 E0513 X00502 E0010 I0003
Y00603 E0513
With the configuration function, you can configure a range of shared relays (E) to determine whether or not they retain computation results when the power is turned off. By default, all shared relays are set so as not to retain computation results. If you set the internal relays to this option, they are cleared to OFF (0) when you: - turn off the power and turn it on again; - change the operation mode to Run or Debug with the WideField2; or - send a Clear Device command from WideField2. If you set the internal relays so as to retain computation results, the latest results are retained after power-off. In this case, the relays are cleared to OFF (0) when you send a Clear Device command from the programming tool. - send a Clear Device command from WideField2.
IM 34M6P13-01E
4-9
CAUTION
When using shared or extended shared relays (E), follow the precautions given below. (1) Index modification of shared or extended shared relays (E) When applying index modification to shared or extended shared relays (E) of the local CPU, be careful that a relay number resulting from index modification does not exceed the range specified by configuration for the local CPU. Otherwise, information held by shared or extended shared relays (E) of the sequence CPU modules is overwritten. This results in a failure for these shared relays to reflect the correct results of computation.
X00503 X00601 E0010 V01 X00602 I0003 Y00703 Y00702 Make sure the relay number does not exceed the range set for the local CPU. F040203.VSD
Figure 4.6 Precautions when Using Shared or Extended Shared Relays (E) (1 of 2)
(2) Block move and computation of multiple devices When using shared or extended shared relays (E) in an instruction for transferring or computing multiple devices, be careful that the specified range of these relays does not exceed the range specified by configuration for the local CPU. Otherwise, information held by shared or extended shared relays (E) of the sequence CPU modules is overwritten. This results in a failure for these shared relays (E) to reflect the correct results of computation.
X00601 X00604 BMOV D0001 E0001 D0100
X00601
Make sure the range does not exceed the range set for the local CPU.
Figure 4.7 Precautions when Using Shared or Extended Shared Relays (E) (2 of 2)
(3) Simultaneity of data With the configuration function, you can select either Yes or No for the simultaneity of data of shared devices. If you select the Yes option, the simultaneity of the data is guaranteed in units of devices (shared relays(E) /registers or extended shared relays(E) /registers) to be refreshed when one of the F3SP28, F3SP38, F3SP53, F3SP58 and F3SP59 sequence CPU modules is combined with add-on CPU modules. (The simultaneity of data held by the shared relays (E) /registers or extended shared relays(E) /registers is not guaranteed, however.) If any of the F3SP28, F3SP38, F3SP53, F3SP58 and F3SP59 CPUs is combined with any of the F3SP21, F3SP25, and F3SP35 sequence CPU modules, the simultaneity of the data is not guaranteed irrespective of the configuration settings. The No option of this configuration item is designed for the interchangeability with the F3SP21, F3SP25 and F3SP35 CPUs. Select this option when replacing these CPUs with the F3SP28, F3SP38, F3SP53, F3SP58 or F3SP59 sequence CPU modules.
IM 34M6P13-01E
4-10
I Configuring Shared and Extended Shared Relays (E) in Multi-CPU System
Set the range of shared and extended shared relays (E) to be used by each CPU when add-on CPU modules are installed. You can allocate a desired number of relays on 32 points basis. Extended shared relays (E) are only available if one of the F3SP25, F3SP28, F3SP35, F3SP38, F3SP53, F3SP58 and F3SP59 sequence CPU modules is combined with any one or more of the CPUs installed as add-on CPUs.
Table 4.1 Configuration of Shared Relays
F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 Configuration Range 2048 points max. on 32 points basis for all CPUs combined (E0001 to E2048) 2048 points max. on 32 points basis for all CPUs combined (E2049 to E4096)
CAUTION
The starting number of extended shared relays (E) is always E2049 even if the range of shared relays (E) to be used is less than 2048.
CAUTION
Apply the same allocation of shared/extended shared relays (E) to all CPUs. If the allocation differs from CPU to CPU, shared refreshing is not performed correctly. This results in a failure for these relays (E) to reflect the correct results of computation.
IM 34M6P13-01E
4-11
Shared relays E0001 E0257 1024 points 1024 points 1024 points CPU 1 256 points CPU 2 256 points CPU 4 256 points CPU-1 shared relays CPU-2 shared relays CPU-3 shared relays CPU-4 shared relays
E1281 512 points E1793 256 points 256 points 256 points 512 points 512 points
Extended shared relays CPU 1 E2079 1024 points E3073 256 points
CPU 4 1024 points CPU-1 extended shared relays CPU-2 extended shared relays CPU-3 extended shared relays CPU-4 extended shared relays
F040205.EPS
256 points
256 points
E3329 512 points E3841 256 points 256 points 256 points 512 points 512 points
Figure 4.8 Example of Allocating Shared/Extended Shared Relays (E) when Four Sequence CPU Modules Are Installed
IM 34M6P13-01E
4-12
4.3
IM 34M6P13-01E
4-13
4.3.1
Y00703 L0513
The relay number is coded as Lmnnnn, where: m = FA link module number 1 (0 to 7) nnnn = Link relay number
Table 4.2 Range of Link Relay Number
Module (Optic) FA Link H Module High Speed Normal Speed Configuration Range 1 to 1024 1 to 2048
IM 34M6P13-01E
4-14
4.3.2
MOV
W0001
D0001 Y00602
The register number is coded as Wmnnnn, where: m = FA link module number 1 (0 to 7) nnnn =Link register number
Table 4.3 Range of Link Register Number
Module (Optic) FA Link H module High speed configuration Normal configuration Configuration Range 1 to 1024 1 to 2048
IM 34M6P13-01E
4-15
4.3.3
System Numbers
In a FA link system, modules are automatically assigned system numbers based on their slot positions, where the module with the smallest slot number will be named system 1.
System 1 L (W) 10001 System 2 L (W) 10001 System 3 L (W) 20001 System 4 L (W) 30001 System 5 L (W) 40001 System 6 L (W) 50001 System 7 L (W) 50001 System 8 L (W) 70001 F040303.VSD
System numbers 1 2 3 4 5 6 7 8
To manually assign system numbers to modules independent of their slot positions, use configuration setup to assign fixed system numbers to slot positions.
Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9
Allocation change
System numbers 1 2 3 4 5 6 7 8
System numbers 8 7 6 5 4 3 2 1
F040304.VSD
F040305.VSD
IM 34M6P13-01E
4-16
4.3.4
Item
IM 34M6P13-01E
4-17
4.3.5
L00003
F040306.VSD
MOV
D00001
W00012
IM 34M6P13-01E
4-18
TIP
Link relays (L) and link registers (W) specified in a program are link-refreshed irrespective of whether or not the relevant instructions are executed. If you want to link-refresh all link relays (L) and link registers (W), include the following codes in the program:
M034 M034
BSET BSET
0 0
L00001 W00001
64 1024
F040308.VSD
Figure 4.16 Link-refreshing L00001 to L01024, and W00001 to W01024 If link relays (L) and link registers (W) are specified by index modification, define the index modification range as shown below so that they will be link-refreshed.
M034
BSET
W00021
10
F040309.VSD
CAUTION
(1) Index modification/indirect designation - Index modification/indirect designation must not be made across different systems. Refer to TIP to link-refresh link relays and registers with index modification or indirect designation. (2) Block move and computation involving multiple devices - Block move or computation for multiple devices must not be made across different systems. Be careful especially when specifying the number of bytes of data to be moved or the number of computations using devices. If you specify the number of bytes of data to be moved or the number of computations using devices, refer to TIP so that all relevant devices are linkrefreshed. (3) Multi-CPU configuration - Multiple CPU modules cannot share the same FA link module. Ensure that only one CPU module is accessing a FA link module.
IM 34M6P13-01E
4-19
4.4
4.4.1
Note: The start status relays assigned to blocks 1 to 32 are M0001 to M0032 and M2001 to M2032, where the values of M0001 to M0032 are the same as those of M2001 to M2032. Similarly, start status relays M2033 to M3024 are assigned to blocks 33 to 1024.
CAUTION
Do not write to a special relay (M), including those not listed in the table above (e.g., M067 to M128), unless otherwise stated. This is because they are used by the sequence CPU module for the system side. If you inadvertently write to these relays, a failure, such as a system shutdown, may result. (It is also prohibited to use a forced set/reset instruction in debug mode.)
CAUTION
You are not allowed to apply index modification to a special relay (M) in an attempt to specify them as the destination of data output. If you do so, an instruction processing error will result.
CAUTION
In a ladder instruction for continuous data transfer or table-format data output (see examples below), you are not allowed to specify a special relay as the output estination. If you do so, an instruction processing error will result. - Instructions for continuous data transfer: Block Move Instruction (BMOV Instruction), BSET, String Move Instruction (SMOV), etc. - Read User Log instruction (ULOGR), FIFO Write Instruction (FIFWR instruction), etc.
IM 34M6P13-01E
4-20
4.4.2
Utility Relays
Utility relays are used to provide timing in a program or give instructions to the sequence CPU module.
Table 4.6 Utility Relays (1 of 2)
Item No. M033 M034 M035 M036* M037* M038* M039* M040* M041* M042* M047* M048* Name Always ON Always OFF Turns on for one scan at the start of operation. 0.01-sec clock 0.02-sec clock 0.1-sec clock 0.2-sec clock 1-sec clock 2-sec clock 1-min clock 1-msec clock 2-msec clock Utility Relays Function Description Used for an initialization process or as a dummy contact in a program. Turns on for one scan only after the start of a program Generates a clock pulse with a 0.01-sec period. Generates a clock pulse with a 0.02-sec period. Generates a clock pulse with a 0.1-sec period. Generates a clock pulse with a 0.2-sec period. Generates a clock pulse with a 0.2-sec period. Generates a clock pulse with a 2sec period. Generates a clock pulse with a 1msec period. Generates a clock pulse with a 1msec period. Generates a clock pulse with a 2msec period.
ON OFF ON OFF
1 scan 0.005 s 0.01 s 0.005 s 0.01 s
*: The rising and falling clock timings are synchronized among M036 to M048. Updates are done at the end of a scan.
IM 34M6P13-01E
4-21
Table 4.6 Utility Relays (2 of 2)
Item No. M049 M050 M051 M052 M053 M054 M055 M056 M057 M058 M059 M060 M061 M062 M063 M064 M066 M067 Name 0 key-in from hand-held programming console 1 key-in from hand-held programming console 2 key-in from hand-held programming console 3 key-in from hand-held programming console 4 key-in from hand-held programming console 5 key-in from hand-held programming console 6 key-in from hand-held programming console 7 key-in from hand-held programming console 8 key-in from hand-held programming console 9 key-in from hand-held programming console A key-in from hand-held programming console B key-in from hand-held programming console C key-in from hand-held programming console D key-in from hand-held programming console E key-in from hand-held programming console F key-in from hand-held programming console Normal subunit transmission line On for one scan at CB startup Utility Relays Function Description
Turns on for one scan only at key-in from the hand-held programming console.
ON: Normal transmission line OFF: Unspecified or abnormal transmission line ON: When the block starts Turns on for one scan when OFF: In all other cases the sensor control block starts (at the first execution of the sensor control block).
SEE ALSO
See "Fiber-optic FA-bus Module F3LP02-0N Fiber-optic FA-bus Type 2 Module F3LP12-0N" (IM34M6H45-01E) for more information on the M066 utility relay (Normal Subunit Transmission Line).
IM 34M6P13-01E
4-22
4.4.3
SEE ALSO
Specifications of Z49 to Z54 special registers for clock data for more information on time setting.
IM 34M6P13-01E
4-23
4.4.4
Self-diagnosis Status Relays Function Description Error information is stored in special registers ON: An error is found. Z17 to Z19 for updating the results of OFF: No error is found. self-diagnosis. ON: Abnormal. Indicates a failure in backup batteries. OFF: Normal. ON: A momentary power failure is found. Indicates that a momentary failure has OFF: No momentary occurred. power failure is found. ON: Abnormal. OFF: Normal. ON: Exists. OFF: Does not exist. ON: Exists. OFF: Does not exist. ON: Exists. OFF: Does not exist. ON: Exists. OFF: Does not exist. ON: An error is found. OFF: No error is found. ON: Abnormal. OFF: Normal. ON: Abnormal. OFF: Normal. ON: Abnormal. OFF: Normal. ON: Abnormal transmission line. OFF: Unspecified or normal transmission line. ON: Abnormal transmission line. OFF: Unspecified or normal transmission line. ON: Abnormal. OFF: Normal. ON: Executes the program. OFF: Stops the program. ON: Executes the program. OFF: Stops the program. ON: Executes the program. OFF: Stops the program. ON: Executes the program. OFF: Stops the program. Indicates that a communication failure has occurred in shared relays/registers. Indicates whether or not a CPU module exists in slot 1. Indicates whether or not a CPU module exists in slot 2. Indicates whether or not a CPU module exists in slot 3. Indicates whether or not a CPU module exists in slot 4. Information on an error that may occur during instruction processing is stored in special registers Z22 to Z24. Indicates that the state of module installation is not consistent with the program. Indicates that no access is possible to I/O modules. The slot number of the module in question is stored in special registers Z33 to Z40. Indicates that the scan has exceeded the scan time monitoring time.
M196 M197 M198 M199 M200 M201 M202 M203 M204 M210
Existence of CPU1 Existence of CPU2 Existence of CPU3 Existence of CPU4 Instruction processing error I/O collation error I/O module failure Scan time-out Failure in subunit transmission line Switchover in subunit transmission line CB scan timeout CPU-1 sequence program execution CPU-2 sequence program execution CPU-3 sequence program execution CPU-14 sequence program execution
The slot number of the fiber-optic FA-bus module in question is stored in special registers Z89 to Z96 if a failure occurs in the module.
Indicates that it is not possible to maintain the execution interval of the sensor control block. Indicates whether the sequence program for the sequence CPU module in slot 1 is running or not running. Indicates whether the sequence program for the sequence CPU module in slot 2 is running or not running. Indicates whether the sequence program for the sequence CPU module in slot 3 is running or not running. Indicates whether the sequence program for the sequence CPU module in slot 4 is running or not running.
SEE ALSO
Fiber-optic FA-bus Module and Fiber-optic FA-bus Type 2 Module (IM34M6H45-01E) for more information on the M210 (Failure in Subunit Transmission Line) and M211 (Changeover in Subunit Transmission Line) self-diagnosis relays.
IM 34M6P13-01E
4-24
4.4.5
SEE ALSO
Special relays/registers sections of FA Link H Module F3LP02-0N Fiber-optic FA Link H Module (IM34M5H43-01E) F3LP12-0N for more information on these FA link module status relays.
IM 34M6P13-01E
4-25
4.5
Timers (T)
There are five types of timer (T): 100-s, 1-ms, 10-ms and 100-ms timers and a 100-ms continuous timer. For each type of timer (T), you can assign the number of timers using the configuration function. However, you are not allowed to assign more than 16 points of 100-s timers.
CAUTION
Do not use a timer instruction in the sensor control block or an interrupt program. The timer used will not operate correctly.
4.5.1
Each timer starts counting at the rising edge of the timer input, and expires when the current value reaches 0. When the timer (T) expires, its time-out relay turns on. The time-out relay is used for a contact a or b. The timer (T) is reset at the falling edge of the timer input and the current value returns to the timers setpoint.
Timer input X00502 X00501 I0001 X00301 T001 I0002
TIM
T001
1s Y00601 Y00603
ON OFF Setpoint
0 ON OFF 1s
F040501.EPS
IM 34M6P13-01E
4-26
TIP
The preset value of a timer refers to the duration from the time the timer starts running (starting time) until the timer stops. The preset value can be specified using the Timer instruction.
TIP
When a timer is running, its current value decrements as time passes. The current value is set to the preset value when the timer starts running, and becomes 0 when the timer timeouts.
IM 34M6P13-01E
4-27
4.5.2
The 100-ms continuous timer retains its current value and the state of its time-out relay even when the timer input is set to OFF. When the timer input is set to ON again, the timer starts counting from the value it retains. When the timer input is set to OFF after the continuous timer expires, the timer (T) is reset, the current value returns to the setpoint, and the time-out relay is set to OFF. If you want to reset the continuous timer before it expires, write 0 to the time using a MOV instruction (MOV 0 Tnnn) when the timer input is in an OFF state.
Timer input X00502 X00501 I0001 X00301 T241 I0002
TIM
T241
ON OFF Setpoint
0 ON OFF
1 1 2
=10 s
F040502.EPS
With the configuration function, you can configure a range of timers to determine whether or not they retain their current values when the power is turned off. By default, all timers are set so as not to retain their current values. If you set the timers to this option, their current values are reset to their setpoints when you: - turn off the power and turn it on again; - change the operation mode to Run or Debug with the WideField2; or - send a Clear Device command from WideField2. If you set the timers so as to retain their current values, the latest results are retained after power-off. In this case, the timers are reset to their setpoints when you send a Clear Device command from the programming tool. - send a Clear Device command from WideField2.
IM 34M6P13-01E
4-28
4.5.3
Selecting Timers
Select the range of 100-s, 1-ms, 10-ms, and 100-ms timers and 100-ms continuous timers to be used. To select the range, specify the number of timers you will use for each timer (T). The magnitudes of starting numbers assigned to these timers (T) are in the following relationship, as classified by the timer type. 100-s timer < 1-ms timer < 10-ms timer < 100-ms timer < 100-ms continuous timer Allocate 100-s, 1-ms, 10-ms and 100-ms timers and 100-ms continuous timers to the sequence CPU, in that order.
Table 4.11 Configuration of Timers
Item Configurat ion of Timer (T) and Counter 100-s timer 1-ms timer 10-ms timer 100-ms timer 100-ms continuous timer Default 0 0 512 448 64 F3SP28 F3SP53 Configuration Range 2048 on 1 point basis for timers and counters combined; 16 max. for 100-s timers; Timer numbers are continuous. Default 0 0 1024 896 128 F3SP38 F3SP58 F3SP59 Configuration Range 3072 on 1 point basis for timers and counters combined; 16 max. for 100-s timers; Timer numbers are continuous.
IM 34M6P13-01E
4-29
4.6
Counters (C)
This section describes the function and operation of counters, as well as selection of counters in the configuration. The counters are decremental counters (C) and have two types of input: count input and reset input. A counter detects the rising edge of a count input and updates the current value when a counter instruction is executed. The counter terminates when its current value reaches 0. When the counter (C) terminates, its end-of-count relay turns on. The count-up relay is used for a contact a or b. The counter (C) is reset at the rising edge of the reset input and the current value returns to the counters setpoint. Count input is not accepted when the reset input is on.
Count input X00502 X00501 Reset input C001 X00504 Y00602
CNT
C001
100
ON OFF
F040601.EPS
Setpoint: 1 to 32767
Figure 4.20 Counter (C)
With the configuration function, you can configure a range of counters to determine whether or not they retain their current values when the power is turned off. By default, all counters are set so as to retain their current values. If you set the counters otherwise, their current values are reset to their setpoints when you: - turn off the power and turn it on again; - change the operation mode to Run or Debug with the WideField2; or - send a Clear Device command from WideField2.
IM 34M6P13-01E
4-30
If you set the counters so as to retain their current values, the latest results are retained after power-off. In this case, the counters are reset to their setpoints when you send a Clear Device command from the programming tool. - send a Clear Device command from WideField2
TIP
A counter preset value refers to the value of the counter when it starts counting. The counter value can be set using a Counter (CNT) instruction.
TIP
When a counter is running, its current value decrements until it reaches 0.
4.6.1
Selecting Counters
Select the range of counters (C) to be used.
Table 4.12 Configuration of Counters
F3SP28 F3SP53 Default Timer (T) Device size T0001 to T1024
C0001 to C1024
Item
Counter (C)
Configuration Range Sum of timers and counters: 2048 points max., on 1 point basis Timer numbers: T0001 to T2048 Counter numbers: C0001 to C2048
F3SP38 F3SP58 F3SP59 Configuration Range Sum of timers and counters: 3072 points max., on 1 point basis Timer numbers: T0001 to T3072 Counter numbers: C0001 to C3072
IM 34M6P13-01E
4-31
4.7
Data Register (D), Shared Register (R) and Extended Shared Register (R)
This section describes data registers (D), shared registers (R), extended shared register (R), and how to set the initial data. Data registers (D) are 16-bit variables that can be used without restrictions in a program. Shared registers (R) are 16-bit variables that can be used for communications between CPUs in a multi-CPU system.
4.7.1
D0001 Y00601
D0002 Y00602
With the configuration function, you can configure a range of data registers to determine whether or not they retain computation results when the power is turned off. By default, all data registers are set so as to retain the results. If you set the registers otherwise, they are set to OFF (0) when you: - turn off the power and turn it on again; - change the operation mode to Run or Debug with the WideField2; or - send a Clear Device command from the Widefield2. If you set the registers so as to retain the computation results, the latest results are retained after power-off. In this case, the registers are set to OFF (0) when you send a Clear Device command from the programming tool. - send a Clear Device command from the Widefield2.
IM 34M6P13-01E
4-32
4.7.2
IM 34M6P13-01E
4-33
Figure 4.22 shows an example of how specific shared registers are shared if you allocate shared registers R0001 to R0256 for CPU 1 and shared registers R0257 to R0512 for CPU 2.
CPU1 X00502 MOV X00501 X00502 $100 R0001 Y00601
R0001
D0001 Y00702
With the configuration function, you can configure a range of shared registers to determine whether or not they retain computation results when the power is turned off. By default, all shared registers are set so as not to retain the results. If you set the registers otherwise, they are cleared when you: - turn off the power and turn it on again; - change the operation mode to Run or Debug with the WideField2; or - send a Clear Device command from WideField2. If you set the registers so as to retain the computation results, the latest results are retained after power-off. In this case, the registers are cleared when you send a Clear Device command from the programming tool. - send a Clear Device command from WideField2.
IM 34M6P13-01E
4-34
CAUTION
When using shared or extended shared registers (R), follow the precautions given below. (1) Index modification of shared or extended shared registers (R) - When applying index modification to shared or extended shared registers (R) of the local sequence CPU module, be careful that any register number, which is directly specified in an instruction and to which the content of an index register has been added, does not exceed the range specified by configuration for the local CPU. Otherwise, information held by shared or extended shared registers (R) of remote CPU modules is overwritten. This results in a failure for these shared registers (R) to reflect the correct results of computation.
X00501 MOV X00501 T001 I0003 V1 R0001 B0001 Y00602
Make sure the register number does not exceed the range set for the local CPU
F040703.VSD
Figure 4.23
(2) Block move and computation of multiple devices - When using shared or extended shared registers (R) in an instruction for transferring or computing data held by multiple devices, be careful that the range of registers, which is defined by the register number directly specified in the instruction and the number of registers included in the transfer and computation, does not exceed the range specified by configuration for the local CPU. Otherwise, information held by shared or extended shared registers (R) of remote CPUs is overwritten. This results in a failure for these shared registers (R) to reflect the correct results of computation.
X00501 X00504 BMOV R0001 D0001 D0100
X00501
Make sure the range does not exceed the range set for the local CPU.
Figure 4.24 Precautions when Using Shared or Extended Shared Registers (R) (2 of 2)
IM 34M6P13-01E
4-35
(3) Simultaneity of data - With the configuration function, you can select either Yes or No for the simultaneity of data of shared devices. If you select the Yes option, the simultaneity of the data is guaranteed in units of devices (shared relays/registers or extended shared relays/registers) to be refreshed when one of the F3SP28, F3SP38, F3SP53, F3SP58 and F3SP59 sequence CPUs is combined with add-on sequence CPUs. (The simultaneity of data held by the shared relays/registers or extended shared relays/registers is not guaranteed, however.) If any of the F3SP28, F3SP38, F3SP53, F3SP58 and F3SP59 CPUs is combined with any of the F3SP21, F3SP25, F3SP35 and F3BP CPUs, the simultaneity of the data is not guaranteed irrespective of the configuration settings. The No option of this configuration item is designed for the interchangeability of the F3SP21, F3SP25 and F3SP35 CPUs. Select this option when replacing these CPUs with the F3SP28, F3SP38, F3SP53, F3SP58 or F3SP59 CPUs.
SEE ALSO
For details on index modification, see Section 1.8 in Sequence CPU Instruction Manual Instructions (IM34M6P12-03E).
IM 34M6P13-01E
4-36
I Configuring Shared and Extended Shared Registers (R) for Multiple CPUs
Set the range of shared and extended shared registers (R) to be used by each CPU in multi-CPU system configuration where add-on CPU modules are installed. You can allocate a desired number of registers to each CPU in 2 unit increments.
Table 4.13 Configuration of Shared Registers (R)
Item Default
Device size
0 0
F3SP28/F3SP53 F3SP38/F3SP58/F3SP59 Configuration Range 1024 points max. on 2 points basis for all CPUs combined 3072 points max. on 2 points basis for all CPUs combined
The extended shared registers can only be used with the sequence CPU modules (F3SP25, F3SP28, F3SP35, F3SP38, F3SP53, F3SP58 and F3SP59).
CAUTION
Assign the same range of shared/ extended shared registers (R) for all CPU modules. No error will result, however, even if the range is not the same among the CPU modules. Rather, data in a remote CPU module may appear wrongly assigned to register numbers or data in the local CPU module may appear that way when referenced from the remote CPU.
- Shared registers
R0001 R0129 512 points 512 points 512 points CPU-2 shared registers CPU-3 shared registers CPU-4 shared registers CPU 1 128 points CPU 2 128 points CPU 4 128 points CPU-1 shared registers
R0641 256 points R0897 128 points 128 points 128 points 256 points 256 points
R2945 768 points R3713 384 points 384 points 384 points 768 points 768 points
Figure 4.25 Example of Allocating Shared/Extended Shared Registers (R) when Four Sequence CPU Modules are Installed
IM 34M6P13-01E
4-37
CAUTION
Even if the specified range includes less than 1024 shared registers (R), the extended shared registers (R) always begin with the number R1025.
IM 34M6P13-01E
4-38
4.7.3
D1024
D4096
F040706.EPS
IM 34M6P13-01E
4-39
4.8
4.8.1
Z007
Z008
Z009
CAUTION
Do not write to a special register (Z), including those not listed in the table above (e.g., Z010 to Z016), unless otherwise stated. This is because they are used by the CPU module for the system. If you inadvertently write to these registers, a failure, such as a system shutdown, may result. You are not allowed to apply index modification to special registers (Z) in an attempt to specify them as the destination of data output. If you do so, an instruction processing error will result. In a ladder instruction for continuous data transfer or table-format data output (see examples below), you are not allowed to specify a special register (Z) as the output destination. If you do so, an instruction processing error will result. - Instructions for continuous data transfer: Block Move Instruction (BMOV Instruction), Block Set Instruction (BSET Instruction), String Move Instruction (SMOV Instruction), etc. - Instructions for table-format data output: User Log Read Instruction (ULOGR Instruction), FIFO Write Instruction (FIFWR Instruction), etc.
IM 34M6P13-01E
4-40
4.8.2
Z033 to Z040
I/O failure
Z041 Z042 Z043 Z044 Z045 Z046 Z047 Z048 Z089 Z090 Z091 Z092 Z093 Z094 Z095 Z096 Abnormal slot in subunit transmission line Module recognition
Main unit Subunit 1 Subunit 2 Subunit 3 Subunit 4 Subunit 5 Subunit 6 Subunit 7 Main unit Subunit 1 Subunit 2 Subunit 3 Subunit 4 Subunit 5 Subunit 6 Subunit 7
Slot number 16 2 1 0 ..... 1 0 0: No modules are recognized. - Unable to read/write. 1: Modules are recognized.
Slot number 16 2 1 0 ..... 1 0 Fiber-optic FA-bus module 0: Normal transmission line; Unspecified transmission line; or Loaded with a wrong module 1: Abnormal transmission line (Failure or changeover in transmission line)
* For information on error numbers (codes) to be saved in these special registers, see Table 8.2, Details of Self-diagnosis.
SEE ALSO
Fiber-optic FA-bus Module, Fiber-optic FA-bus Type 2 Module (IM34M6H45-01E), for more information on the Z089 to Z096 special registers (Abnormal Slot in Subunit Transmission Line).
IM 34M6P13-01E
4-41
4.8.3
Utility Registers
Table 4.16 Utility Registers
Type No. Z049 (write-enabled) Z050 (write-enabled) Z051 (write-enabled) Z052 (write-enabled) Z053 (write-enabled) Z054 (write-enabled) Z055 Z056 Z057 Z058 Constant scan time Constant scan time Scan time monitoring time Clock data Name Utility Registers Stored Data Description Lower-order two digits Stores "year" as a BCD-coded value. of calendar year Example: 1999 as $0099 2000 as $0000 Stores "month" as a BCD-coded Month value. Example: January as $0001 Stores "day of month" as a Day BCD-coded value. Example: 28th as $0028 Stores "hour" as a BCD-coded value. Hour Example: 10 o'clock as $0010 Stores "minute" as a BCD-coded Minute value. Example: 15 minutes as $0015 Stores "second" as a BCD-coded Second value. Example: 30 seconds as $0030 Stores "day of week" as a Day of week BCD-coded value. ($0 to $6) Example: Wednesday as $0003 Value of constant scan 0.1 ms increments time Example: 10 ms = 100 Value of constant scan 1 ms increments time Example: 10 ms = 10 Value of scan time 1 ms increments Example: 200 ms = 200
- For CPU module F3SP - S, you can set clock data using the Set Date instruction (DATE), Set Time instruction (DATE), Set Date String instruction (SDATE), and Set Time String instruction (STIME). - For CPU module F3SP - N/- H, use the following procedure to set time data. (1) Write the clock data to special registers Z049 to Z054 (use a MOV P instruction). (2) Set special relay M172 to ON within the same scan as that in step 1 (use a DIFU instruction, for example). (3) Set special relay M172 to OFF in the scan subsequent to that in step 2. Also stop writing the clock data to special registers Z049 to Z054 in that scan. Note that no change is made to the clock data and the data reverts to its original values if the values being set are incorrect. - The accuracy of clock data is as follows. Maximum monthly error: 8 s (2 s, when actually measured) The clock accuracy is reset to the maximum daily error of -1.2 s/+2 s, however, when the power is turned off and on again. In addition, it is possible to input a corrective value from the programming tool. If you input a precise corrective value, the clock data is corrected during the power-off-and-on sequence, thus offsetting the cumulative amount of error.
IM 34M6P13-01E
4-42
4.8.4
Local station status Cyclic transmission time Local station status Cyclic transmission time Local station status Cyclic transmission time Local station status Cyclic transmission time Local station status Cyclic transmission time Local station status Cyclic transmission time Local station status Cyclic transmission time Local station status Cyclic transmission time
0: Under initialization 1: Offline 2: Online 0: Under initialization 1: Offline 2: Online 0: Under initialization 1: Offline 2: Online 0: Under initialization 1: Offline 2: Online 0: Under initialization 1: Offline 2: Online 0: Under initialization 1: Offline 2: Online 0: Under initialization 1: Offline 2: Online 0: Under initialization 1: Offline 2: Online
FA link 1 FA link 1 1ms increments FA link 2 FA link 2 1ms increments FA link 3 FA link 3 1ms increments FA link 4 FA link 4 1ms increments FA link 5 FA link 5 1ms increments FA link 6 FA link 6 1ms increments FA link 7 FA link 7 1ms increments FA link 8 FA link 8 1ms increments
SEE ALSO
For more details on the FA link module status registers (Z), see the Special relays (M)/registers (Z) sections in the instruction manual (IM34M5H43-01E), FA Link H Module, Fiber-optic FA Link H Module.
IM 34M6P13-01E
4-43
4.8.5
Z109
CB execution time
Z111
*:For example, the values for moduleF3SP58-6S, firmware Rev1 are as follows. Z121 F3 Z122 SP Z123 58 Z124 6S Z125 /R Z126 01 Z127 / Z128
IM 34M6P13-01E
4-44
4.9
SEE ALSO
Section 1.8.1, Index Modification, in the 3rd or later edition of the instruction manual (IM34M6P12-03E), Sequence CPU - Instructions, for more information on index registers.
X00502 MOV I0001 V01 X00502 X00504 MOV X00501 T001 X00503 I(0001+100)=I0101 D(0001+100)=D0101
F040901.VSD
100
V01 Y00601
X00503
V01 D0001
CAUTION
Examination of whether or not the device number specified using an index register exceeds the given configuration range, is not performed on the system side of the sequence CPU module. The configuration range may be exceeded depending on the content of the index register used, resulting in the selection of a wrong device. Be careful when specifying the device number.
CAUTION
You can set a value from -32768 to 32767 in index registers. For such devices as file registers (B) whose size is larger than 32768, however, it is not possible to specify any of them by index modification.
IM 34M6P13-01E
4-45
B00001 1
Unlike data registers (D), all file registers (B) retain computation results when the power is turned off. The file registers are cleared to OFF (0) when you write the data value OFF (0) to the file registers from the programming tool. Unlike data registers, the file registers are not cleared to OFF (0) even if you: - send a Clear Device command from WideField2; or - send a memory clearance command from the Widefield2.
IM 34M6P13-01E
Blank Page
5-1
5.
5.1
Programs
This chapter describes languages used for programming, program types and program memory.
Programming Language
Two types of programming language are available: structured ladder language and mnemonic language. In either case, the written program is read sequentially by the sequence CPU to perform computations according to the programs process details.
5.1.1
Function n X00502 CNT X00501 C001 X00501 I0016 X00504 T001 X00503
F050101.VSD
C001
100
Y00602 Y00601
IM 34M6P13-01E
5-2
5.1.2
Mnemonic Language
The mnemonic language is designed to describe a program by breaking its process details into instruction, input parameter, and output parameter. Like the structuredladder language, the mnemonic language allows the programmer to perform programming on a function-by-function basis.
Instruct6ion section LD OUT LD AND MOV Instruction section I0001 Y00602 X00501 X00502 D0001 D0002 Output parameter section
F050102.VSD
IM 34M6P13-01E
5-3
5.2
5.2.1
I Blocks
A block refers to a set of circuits entered through the WideField2. Parts of each program written on a function-by-function basis using the structured ladder language or mnemonic language are managed as blocks. Since the program can be maintained or reused block by block, program development becomes extremely easy. A single block can contain steps up to 10 K. For CPU modules F3SP - N and F3SP - H, one block has a maximum step of 10K steps. For CPU module F3SP - S, one block has a maximum step of 56K steps. (Module F3SP28-3S has a maximum step of 30K steps.)
CAUTION
It is not possible for the CPU to execute a separate block.
Block 1
X00503 X00504
Circuit
Y00602
X00501
X00502 X00503
Y00601
Block n
I0001 X00501 X00502 Y00602 I0003
F050201.VSD
IM 34M6P13-01E
5-4
I Executable Program
An executable program refers to a program with a format which can be executed by the CPU. The executable program is composed by combining multiple blocks created with the Widefield2. Each executable program can contain a maximum of 1024 blocks. Since you can execute only specific blocks of an executable program, it becomes easy for you to control and manage your programs.
Block 1
X00503 X00501 X00504 X00502 X00503
Circuit
Y00602 Y00601
Block 16
I0001 X00501 X00502 Y00602
Block 16
F050202.VSD
IM 34M6P13-01E
5-5
5.2.2
IM 34M6P13-01E
5-6
I Main Routine Programs
A main routine program is always executed in each scan. Since the main routine program is written in the structured ladder language, it is composed of multiple blocks. You can execute a main routine program by either executing all blocks of the program or executing only specific blocks.
Program execution Block 1 SUB This subroutine program is excluded from the execution.
RET
Block n-1
Block n
F050204.VSD
IM 34M6P13-01E
5-7
I Subroutine Programs
A subroutine program is executed when a CALL instruction is given by a main routine program. Use this program when you want to run a specific process two or more times within one scan. A subroutine program can be placed in any location in a block. In a case where the operation mode in which only specific blocks are executed is selected, a subroutine program is executed even if it is located in a yet-to-be-executed block and called from a block being executed. Subroutine programs can be nested to a maximum depth of eight layers (nesting means to call a subroutine from within another subroutine).
Program execution CALL Block 1 Program execution
Block n-1
SUB
F050205.VSD
IM 34M6P13-01E
5-8
I Interrupt Programs
An interrupt program is executed when any cause of interrupt occurs. A maximum of four interrupt programs can be included in a block. The relationship between a cause of interrupt and an interrupt program is described as a parameter of the Interrupt (INTP) Instruction.
INTP X00301
F050206.VSD
Program execution
Program execution
Block 1
Interrupt processing
Block n-1
INTP
F050207.VSD
IM 34M6P13-01E
5-9
I Sensor Control Block
The sensor control block (CB) is a bock that is executed separately from those for a normal scan, both at high speeds and at fixed intervals.
CBACT
Block 1
Fixed-interval timing
Block n-1
Block n
F050208.VSD
IM 34M6P13-01E
5-10
5.3
Program Memory
Program memory contains programs as well as information required for their operation and management. This section describes the configuration of the program memory and its initial condition when there are no programs in it.
Table 5.1 Configuration of Program Memory and Its Initial Condition
Description An area for storing information required to manage the entire range of programs, such as program names, the number of steps, and information on block management. An area for storing programs. An area for storing configuration information, such as device sizes and operation methods. An area for storing configuration information such as output settings, in case the sequence stops and for I/O module settings. An area for storing the information required to control the execution of program instructions, such as a JMP instruction and a subroutine instruction. An area for storing timer and counter setpoints. An area for storing such information as circuit comments and sub-comments.
Initial Condition Stays in the default state of program management, where the program name is "PROGRAM," block name is "PROGRAM," and the number of steps is "0". Contains a NOP instruction. Contains the defaults discussed in subsection 1.2.3, "Configuration." Contains the defaults discussed in subsection 1.2.3, "Configuration." Contains "0," indicating there are no such program control instructions as a JMP instruction or a subroutine instruction. Contains "0," indicating there are neither timers nor counters. Contains "0".
CAUTION
No programs can be executed when the program memory is in its initial condition.
Configuration of program memory Program management table Program Programs F3SP28: F3SP53: F3SP38/F3SP58: F3SP59:
30 K 56 K 120 K 254K
Configuration table RAM I/O configuration table Program control instructions table Timer/counter settings table Utility
Range of devices Error-mode operation Range of devices latched at power failure Setting as to whether or not data is retained Setting of sampling interval Setting of data codes Jump Interrupt definition Subroutine Label
IM 34M6P13-01E
6-1
6.
6.1
Functions
This chapter describes functions which can be executed by the sequence CPU module, such as the execution of specified blocks and debugging operation.
Function List
The following tables summarize the functions provided by the sequence CPU module and add-on CPU modules.
Table 6.1 Functions Provided by Sequence/Add-on Sequence CPUs
Function of Sequence CPU Module Function Overview Specifies the operation mode of the sequence CPU module and its actions. Executes a sequence program at certain time intervals. Specifies how an executable program is processed. Specified blocks are executed using ACT and INACT instructions. Supports debugging operations, such as forced set/reset. Protects programs by means of password. This function has two modes: executable program protection and block protection. Makes on-line modifications or changes to a program in the program memory of the sequence CPU module. Acquires and displays states of multiple devices for up to 1024 scans. Performs the same level of communication as that of a personal computer link module, when a personal computer or a monitor is connected to the programming tool connector. Allows the user to create and register new, customized instructions. Allows the user to keep a log, or record of, errors in the user's system, the way they occurred, the system's operating condition, and so on. Executes a single block separately from those for a normal scan, both at high speeds and at fixed intervals. Downloads only specified blocks/macros. Stores circuit comments and subcomments to a sequence CPU module. Stores tag name definitions to a sequence CPU module. Represents a group of data items under a unified name. Page 6-3 6-5 6-6 6-13 6-15 6-17 6-24 6-28 6-46 6-62 6-64 6-81 6-83 6-86 6-87
IM 34M6P13-01E
6-2
Table 6.3 Device Management Functions
Device Management Function Device upload function Device download function Device edit function Device comparison function Function Overview Reads device information (data) from the sequence CPU module and saves it to a WideField2 file. Reads device information (data) from a WideField2 file and writes it to the sequence CPU module. Edits device information saved in a file in the WideField2. Compares device information saved in the sequence CPU module with that saved in a WideField2 file. Page 6-45 6-45 6-45 6-45
IM 34M6P13-01E
6-3
6.2
I Run Mode
The CPU begins running a program from its first instruction, similar to when the power is turned on. When the power is turned on or the mode is changed from stop to run, the CPU sets all devices to 0, except for latching-type devices, before executing the program. When the CPU enters the Run mode, functions available only in the Debug or Stop mode are disabled.
I Debug Mode
The CPU begins running a program from its first instruction, similar to when the power is turned on. When the Stop mode is changed to the Debug mode, the CPU sets all devices to 0, except for latching-type devices, before executing the program. Be sure to disable the Debug mode and enter the Run mode when you have completed your debugging and tuning tasks.
I Stop Mode
The CPU stops running the program. External output data is retained (ON) or not retained (OFF), depending on the settings of the configuration item external output to be retained in case of sequence stop. This mode does not work when the CPU has already stopped running the program.
I Clear Memory
Stop
This function deletes a program or programs and sets all devices to 0. Stop running the program before using this function.
I Clear Devices
Stop
This function sets all latching-type devices, excluding file registers (B), to 0. Stop running the program before using this function. To clear file registers (B), use the device edit function of the device management function to set all the file register (B) data to 0 and write the data to the sequence CPU module using the device write function.
SEE ALSO
For details on the device management function, see Section 6.12, Device Management Function.
IM 34M6P13-01E
6-4
CAUTION
The following are precautions you should follow when using the functions described in this chapter: - Some functions are not available in all the operation modes. - Note that the following marks are used when explaining each function, in order to indicate that the function in question is available in the cited mode or modes.
Run Debug Stop
Unless otherwise specified, the function can be used in any operation mode. The scan time may become longer for some functions. When you finish using such a function, be sure to disable it before running the system. Be especially careful when using any function that works in Debug mode. When your debugging and tuning tasks are complete, always disable the function and enter Run mode. Be sure to use the ROM writer functions when you operate the ROM pack. Note that the following mark is used when explaining each ROM writer function to indicate that the function is available in ROM Writer mode.
ROM writer
IM 34M6P13-01E
6-5
6.3
Constant Scan
END instruction END instruction END instruction
Run
Debug
The constant scan function executes a program repeatedly at certain time intervals. You can set the constant scan time, i.e., constant-scan time interval, to a value from 1 ms to 190 ms in 0.1 ms increments. To do this, use the configuration function.
0 step 0 step 0 step
3ms 10ms
5ms 10ms
2ms 10ms
F060301.VSD
If the scan time of a sequence program is longer than the preset constant scan time, any constant scan is ignored and the program is executed with its own scan time.
0 step END instruction 0 step END instruction END 0 step instruction 0 step
1ms 2ms
1ms 2ms
F060302.VSD
6.3.1
CAUTION
The constant scan time must be shorter than the scan time monitoring time. If the constant scan time is longer than the scan time monitoring time, a scan timeout error occurs.
IM 34M6P13-01E
6-6
6.4
Select the method of program execution: executing all blocks or executing specified blocks. using the configuration item operation control of the WideField2.
6.4.1
F060401.VSD
IM 34M6P13-01E
6-7
6.4.2
F060402.VSD
IM 34M6P13-01E
6-8
6.4.3
ACT: Block 2 Next scan (n+1)th scan Block 1 Function 1 Next scan Block 2 Function 2 Special relay M2002=1 Special relay M2001=1
Executable program Block 1 Function 1 Block 2 Function 2 Block m Function m Block n Function n ACT
Block 2 Function 2
Block m Function m
F060403.VSD
IM 34M6P13-01E
6-9
Devices that are specified in the blocks enabled with an ACT instruction are placed in the following conditions by block initialization.
Table 6.4 Conditions when Blocks Are Enabled
Device Timer (T) Continuous timer Counter (C) Destination of OUT instruction All other devices Condition when Blocks Are Enabled Resets. Retains the value it held before the blocks are enabled. Retains the value it held before the blocks are enabled. Goes into an OFF state. Retain the states they held before the blocks are enabled.
Use a SET instruction for devices whose output values need to be retained when blocks are enabled.
This device is set to OFF. X00503 I0002 X00501 X00502 I0003 X00301 I0005 I0004 SET Y00601 Y00603 I0004
IM 34M6P13-01E
6-10
6.4.4
Block m Function m
Executable program Block 1 Function 1 Block 2 Function 2 Block m Function m Block n Function n Block 1 Function 1 Special relay M2001=1 INACT Next scan (n+1)th scan
F060405.VSD
IM 34M6P13-01E
6-11
Devices that are specified in the blocks disabled with an INACT instruction are placed in the following conditions by block initialization.
Table 6.5 Conditions when Blocks Are Disabled
Device Timer (T) Continuous timer Counter (C) Destination of OUT instruction All other devices Condition when Blocks Are Disabled Resets. Retains the value it held before the blocks are enabled. Retains the value it held before the blocks are enabled. Goes into an OFF state. Retain the states they held before the blocks are enabled.
Use a SET instruction for devices whose output values need to be retained when blocks are disabled.
This device is set to OFF. X00503 I0002 X00501 X00502 I0003 X00301 I0005 I0004 SET Y00601 Y00603 I0004
6.4.5
ACT
Block 2
INACT Block 1
Condition
Block 1
Block 2
Condition
ACT
Block m
Block 2
Condition
INACT
Block 2
Block m
Block m
Condition
ACT
Block 1
INACT
Block m
F060407.VSD
Figure 6.9 Example Where Each Block Controls the Block to Be Enabled Next Time
IM 34M6P13-01E
6-12
G Example Where Blocks to Be Enabled Are Controlled by Creating
Scheduler
Block 1
Condition
Block 2 Block n Block 3 Block 2 Block 1 Block m Block 3 Block n Block 1 Block m
ACT INACT
Condition
Block 1 Condition
Block m Condition
Block n Condition
F060408.VSD
Figure 6.10 Example Where Blocks to Be Enabled Are Controlled by Creating Scheduler
IM 34M6P13-01E
6-13
6.5
Debugging Functions
This section describes the following functions: forced set/reset function that forcibly changes the status of a relay, function that changes setpoints, current values and data values specified in a register, as well as the Stop Refreshing function that stops I/O refreshing, link refreshing, and shared refreshing.
6.5.1
Forced SET/RESET
Debug
Stop
A forced SET/RESET instruction forcibly sets a specified bit device to ON/OFF, regardless of program execution. You can use the instruction to a maximum of 32 bit devices at one time. The device type supported is bit devices only, i.e., X, Y, I, E, L, T and C devices. If a forced SET instruction is applied to a timer (T) or a counter (C), the timer expires or the counter terminates. A forced SET/RESET instruction remains valid until you: - Disable the instruction, - Change the operation mode to RUN, or - Turn off the power.
6.5.2
Changing Setpoints You can change the setpoints of timers (T) and counters (C). Changing Current Values You can change the current values of timers (T) and counters (C). If you set a current value of 0, a timer expires and a counter terminates. Changing Word or Long-word Data Values You can change the data values of word devices other than timers (T) and counters (C), such as data registers (D). If you select bit devices such as internal relays (I) instead, data values included in the change are those of 16 or 32 bits worth of devices, beginning with the first device address.
IM 34M6P13-01E
6-14
6.5.3
Stopping Refreshing
Stop
You can prevent relays (input relays (X) and output relays (Y)) for external devices, link relays/registers for FA links, and shared relays/registers for add-on CPU modules, from being refreshed by the results of program execution. This allows you to visually check I/O data on the monitor. In the case of relays (input relays (X) and output relays (Y)) for external devices, you can stop refreshing X input relays and Y output relays separately.
X00502 X00501 X00503 X00501 X00502 X00504 X00502 X00503 Y00602 Y00601 Y00603 Y00604
Arithmetic results
External devices
F060504.VSD
CAUTION
It is not possible to stop input relays (X) and output relays (Y) for external devices, specified in the sensor control block, from refreshing.
IM 34M6P13-01E
6-15
6.6
Protecting Programs
For security reasons, you can protect your programs from being referenced. There are two modes of protection: executable program protection and block protection. Protection is achieved by entering a password with the WideField2. A password must consist of eight alphanumeric characters, beginning with a letter. The protection information is saved in an executable program or block by the WideField2.
CAUTION
Program protection is designed to prevent unauthorized references only. It is not effective against deleting programs or changing CPU operations due to erroneous operations or writing.
6.6.1
Uploading
Downloading
F060601.VSD
When executable program protection is selected, the following functions are disabled. Downloading, uploading, monitoring (circuit diagram monitoring, debugging operation, changing timer (T)/ counter (C) setpoints, online editing), ROM writer functions, and printing.
IM 34M6P13-01E
6-16
6.6.2
Block Protection
Block protection protects programs on a block-by-block basis. This protection mode is designed to prevent unauthorized references only. In addition, only specified blocks are included in the protection. When block protection is selected for a block, its circuit diagrams and instructions are not displayed on the WideField2.
Block n Personal computer X00503 X00504 Y00602
F060602.VSD
When block protection is selected, the following functions are disabled. Monitoring (circuit diagram monitoring, debugging operation, changing timer (T) /counter (C) setpoints, and online edit) and printing
IM 34M6P13-01E
6-17
6.7
Online Editing
Debug
Stop
Online editing allows you to make modifications or additions to your program when the program is being executed. This function is useful when you make minor changes to the program during a debugging or tuning task. Modifications/changes made to the program are reflected in the program memory of the sequence CPU module at the end of a given scan.
Addition I0001 X00501 X00503 X00501 X00502 I0002 X00502 I0003 Y00602 I0003 Y00603 I0004
CPU program memory The addition is reflected at the end of a given scan.
F060701.VSD
WARNING
Do not perform online editing when machinery under control is in operation. The scan time may become excessively longer than when carried out under normal conditions, while data edited online is written to the sequence CPU module. The scan time lengthens by as much as 10 ms for every 10 K step increase in the program size. During scan time, it is not possible to perform external refreshing or communicate with any external device. If modifications/additions span two or more circuits, several scans will be required until the overall range of these modifications/additions is reflected in the sequence CPU module. Be careful with sequence CPU module operation during this process.
CAUTION
(1) You are not allowed to modify the following instructions and circuits. - Subroutine Entry instruction (SUB instruction) and Subroutine Return instruction (RET instruction) as well as circuits that contain any of these instructions. - Input module Interrupt instruction (INTP instruction) and Interrupt Return instruction (IRET instruction), as well as circuits that contain any of these instructions. - Structure Macro Call Instruction (SCALL), Structure Move instruction (STMOV), as well as circuits that contain any of these instructions. (2) Online editing affects peripheral processing. The peripheral processing time may lengthen by approximately 200 ms, though this depends on the program size or the location in the program where modifications are made. During the peripheral processing time, the CPU does not perform shared refreshing, link refreshing and command processing.
IM 34M6P13-01E
6-18
6.8
56K steps 120K steps 56K steps 120K steps 56K steps 120K steps 360K steps 56K steps 120K steps 360K steps
With the configuration function, you can make the following two types of data resident in ROM. These types of data are used to set initial values to be used by a program. - Setpoints of 1,024 data registers (D) worth of default data - Either 32768 data registers (D) or file registers (B) worth of current values within the sequence CPU module. See Section 6.8.2, Setting Devices Current Values to Be Made Resident in ROM. At power-on, data read from the ROM pack is stored in data registers (D) or file registers (B) specified with the configuration function. Data registers (D) and file registers (B) included in the data retention in case of power failure revert to their respective default values. If you edit both of the configuration items mentioned above for the same data register (D), only the setpoint of the second configuration item Setting Devices Current Values is effective.
IM 34M6P13-01E
6-19
TIP
Data retention in case of power failure is effective for devices not included in the configuration discussed above.
Program
Program
Configuration table RAM I/O configuration table Program control instruction table Timer/counter setpoint table Utility
Tag name definition table Configuration table I/O configuration table Program control instruction table Timer/counter setpoint table Utility
F060801.VSD
ROM area
CAUTION
Limitations on writing to the ROM pack - Debug and tune programs before making them resident in the ROM. There is a limit to the number of write operations that can be performed on a ROM pack. Furthermore, program and data resident in the ROM pack cannot be edited. Writing to the ROM pack of an installed CPU module - A resident program in a ROM pack can only be executed by the CPU module whose model name has been transferred to the ROM pack. Example: A program written in the ROM pack by a F3SP28-3S CPU module can only be executed by a F3SP28-3S CPU module. A program written in the ROM pack by a F3SP28-3N CPU module cannot be executed by a F3SP28-3S CPU module. Compatibility between the ROM pack and the CPU module - If a sequence CPU module is installed with an incompatible ROM pack, WideField2 may return an error message of "ROM cassette is not installed."
IM 34M6P13-01E
6-20
6.8.2
IM 34M6P13-01E
6-21
6.8.3
ROM writer
The sequence CPU module or an add-on CPU module can be operated by reading a program stored in the ROM pack. In the FA-M3 R series, you can achieve the same functions as those of a commercially available ROM writer, such as writing a program to the ROM pack, by using the sequence CPU module or add-on CPU module. These functions are called the ROM writer functions and include file-to-ROM transfer, CPU-toROM transfer, and file and ROM pack comparison. The ROM writer functions work in a dedicated mode different from the normal operation mode of the sequence CPU module. This dedicated mode is called the ROM Writer mode. The ROM Writer mode is maintained even when you turn on or off the power. At power-on, no programs are read from the ROM pack.
Sequence CPU
Program memory ROM pack Transfer Write Read ROM Writer mode
F060802.VSD
IM 34M6P13-01E
6-22
Using the ROM writer functions, you can save a debugged and/or tuned program to the ROM pack. To transfer the program to the ROM pack, use the ROM management function of the WideField2. The following details the ROM writer functions.
CAUTION
Change the CPU to the ROM Writer mode before using the ROM writer functions. You cannot use the ROM writer functions in other modes. Be sure to disable the ROM Writer mode when you finish using the ROM writer functions. The CPU does not execute any sequencing functions if the ROM Writer mode remains active.
IM 34M6P13-01E
6-23
6.9
G Get
This mode acquires the exclusive access right.
G Release
This mode releases the exclusive access right.
G Forced Release
This mode permits you to forcibly acquire the exclusive access right from the CPU holding the right through access from a tool or module having no access right.
Personal computer
F060901.VSD
Once the exclusive access control is acquired, the system prohibits the following acts from being performed by a tool or module having no access right. CPU operation, CPU stop, debugging, downloading, debugging operation, use of debugging functions, writing to devices, and change in timer (T)/counter (C) setpoints.
IM 34M6P13-01E
6-24
IM 34M6P13-01E
6-25
M00040
/C00001
Start of sampling trace Trigger condition Sampling method Sampling frequency Number of delays Devices to be sampled
: Instructed from the programming tool : Set from the programming tool - Rising/falling edge of signal at selected relay - Match between data values : TRC-instruction sampling End-of-scan sampling (every 1 to 1000 scans) Fixed-interval sampling (10 to 2000 ms) : 1024 cycles : Selection of a positive or negative number from (-1023 to +1023) : 16 points of X, Y, I, E, L, T, C or M relay devices 4 or 16 points of D, B, R, W, V, Z, T or C word devices or X, Y, I, E, L, T, C or M relay devices, beginning with the one with the specified first address
F061007.VSD
Figure 6.20
You can perform the sampling trace function in either the Run or Debug mode. The sampling trace function, if performed, deletes previous data. If you define sampling trace function settings using the configuration function, the CPU begins sampling at the moment of power-on. If you define sampling trace function settings using the configuration function and then permanently store them in ROM, the CPU reverts to the ROM data during a power-on-and-off sequence even if you redefine the settings later using the programming tool.
SEE ALSO
For details on how to define sampling trace function settings, see, "FA-M3 Programming Tool WideField2 Instruction Manual" (IM34M6Q15-01E).
IM 34M6P13-01E
6-26
Sampling is carried out as explained below.
Sampling
Sampling
Sampling
Sampling
F061002.VSD
G End-of-scan Sampling
The CPU samples the states and data of specified contacts at the end of a scan. It collects and stores the data each time the specified number of scans are completed.
END END END END
Sampling
Sampling
F061003.VSD
G Fixed-interval Sampling
The CPU samples the states and data of specified contacts at fixed time intervals. It collects and stores the data when the specified period expires and before the next scan begins.
Specified period END END END END
Sampling
Sampling
F061004.VSD
IM 34M6P13-01E
6-27
CAUTION
The sampling trace function monitors the trigger condition when an END instruction in a program is being processed. The function therefore cannot judge the condition as established if it is established once during program execution but becomes false again by the time the processing of the END instruction begins.
Results of 1024 cycles of tracing are stored in the sampling trace memory
F061005.VSD
Results of 1024 cycles of tracing are stored in the sampling trace memory
F061006.VSD
IM 34M6P13-01E
6-28
X00503
X00504
Y00602
X00501
X00502 X00503
Y00601
F061101.VSD
IM 34M6P13-01E
6-29
F061102.VSD
Figure 6.27 Examples of Connection between a Sequence CPU Module and External Equipment
Provide the programming tool cable with a ferrite core if you want to have the connected device compatible with the CE marking.
Kitagawa Industries K.K. Examples of ferrite cores TDK Corporation NEC TOKIN Corporation RFC series ZCAT series ESD-SR series
IM 34M6P13-01E
6-30
I Function
The transmission rate and data format of the CPUs personal computer link function differ from those of the personal computer link module. For more information, see subsection 6.11.4, Setting Up the Personal Computer Link Function.
Table 6.7 Transmission Rate and Data Format of CPUs Personal Computer Link Function
Transmission Rate (bps) 9600 9600 19200 19200 38400 38400 57600 57600 115200 115200 Data Length 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits Parity Even None Even None Even None Even None Even None No. of Stop Bits 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit
The dedicated programming tool cable is required to connect a personal computer or monitor to the CPU module. To set the transmission rate, data format, checksum, terminating character, and protection function, use the configuration item communication setting, or switches in the case of the personal computer link module. The event transfer function is not supported. An MDR module reset command resets only the communication port. The maximum number of personal computer link modules that can be installed remains the same even if the CPUs personal computer link function is used.
IM 34M6P13-01E
6-31
I Protocol
This section briefly describes the communications protocol of the personal computer link function of CPU.
Sending station Receiving station Communication protocol of personal computer link function STX Station No. CPU No. Response wait time Command Parameters Checksum ETX CR STX Station No. CPU No. OK Command response Checksum ETX CR
F061103.VSD
In personal computer link communication, the maximum size of text that can be transferred at the same time is 512 bytes.
IM 34M6P13-01E
6-32
Setup *1
Parity check Checksum: Yes/No Not used. Not used. Transmission rate, data format, checksum, terminal character, and protection function Dedicated protocol Yes/No Yes/No Access to all control data, uploading/downloading ladder programs, CPU operation (Run mode)/stop (Stop mode), and reading error logs 8m max. Dedicated cable
The check mark indicates that the user can configure the item by using the configuration function. However, there are restrictions on the way the transmission rate and parity check are combined. See subsection 6.11.4, Setting Up the Personal Computer Link Function, for more information. You can set the protection function to the Yes option to prevent inadvertent writing to the FA-M3.
CAUTION
The personal computer link function uses neither a control line nor Xon/Xoff characters. Be careful when using the function because a communication failure may occur at the higher-order equipment side, depending on the transmission rate.
IM 34M6P13-01E
6-33
The personal computer link function is set to communication mode 0 when the sequence CPU module is shipped from the factory, the CPU memory is cleared, or the function has not yet been configured.
CAUTION
Be careful when setting the transmission rate. The WideField2 supports all of the communication modes listed above. However, first refer to the instruction manual of the personal computer that runs the WideField2 to check available transmission rates and data formats. Then, temporarily change the transmission rate of the personal computer link function using WideField2 to make sure the Sequence CPU module can communicate with the personal computer in the communication mode you want to use. Finally, configure the personal computer link function according to that communication mode. Note that the personal computer link function automatically reverts to the previous transmission rate if communication is not established after a temporary change in the transmission rate. If you select a communication mode in which the personal computer cannot communicate, it is impossible to communicate with the Sequence CPU module through the computer. If this happens, first install the sequence CPU module in the fifth or later slot of the main unit. Next, turn on the power and make sure the RDY indicator has come on. Then, turn off the power to clear the sequence CPU module memory completely and allow the CPU module to revert to its factory-set defaults.
IM 34M6P13-01E
6-34
CAUTION
To use the personal computer link function, set the configuration item personal computer link function to the option Used. If you do not select this option, communications with higher-order instruments may fail.
SEE ALSO
For details on the configuration function, see, "FA-M3 Programming Tool WideField2 Instruction Manual" (IM34M6Q15-01E).
I Communication Procedure
The following outlines the procedure of communication using a BASIC program on a personal computer. For details on the statements and functions used in the program, refer to the BASIC reference manual that came with your personal computer. 1. Open the RS-232-C communication file. Enter a command in the following format: OPEN COM : AS# : Enter communication parameters, such as the parity, data length, and the number of stop bits. : File number. This number is used for subsequent inputs to and outputs from the file. 2. Send a command to the FA-M3 in the following format. PRINT#n, String variable name (or string) 3. Enter a command in the following format to receive a response from the FA-M3. LINE INPUT#n, String variable name INPUT#n, String variable name
IM 34M6P13-01E
6-35
I Overview of Communication
Communication control performed by the CPU module is based on the processing of commands and responses using a dedicated protocol. At first, the host computer (or monitor) has the transmission right. When the computer sends out a command, the transmission right transfers to the CPU module. The CPU module then sends a response to the host computer. If the configuration item personal computer link function is set to the option Used, the CPU module does not send any command to the host computer.
Personal computer (when running BASIC programs) Program Print# Line Input# or Input$ Command xxxxxx (ASCII string)
Power supply
CPU
F061104.VSD
To FA-M3 (FA-M3) Response STX code Station No. CPU No. Response wait time Command response Parameter Checksum ETX code Terminating character
F061105.VSD
IM 34M6P13-01E
6-36
For commands and responses, use the upper-case alphabetic letters of A to Z, which are the ASCII codes of $41 to $5A (hexadecimal numbers). The individual elements are detailed below.
G Station Number
The station number is fixed at 01 when the personal computer link function of the sequence CPU module is used.
G CPU Number
Use a number from 01 to 04 to define which of the sequence CPU module and add-on CPU modules is the one to communicate with. 01: Sequence CPU module 02: Add-on CPU module 1 03: Add-on CPU module 2 04: Add-on CPU module 3
IM 34M6P13-01E
6-37
G Response Wait Time
You can set a wait time, i.e., delay, which is an interval from when a command is sent to when a response is received. The wait time can be as long as 600 ms. Set a relatively long wait time if the communication software running on the host computer is such a program as a BASIC interpreter. To set a wait time, use characters 0 to F, as shown below.
Table 6.10 Setpoints of Response Wait Time
Character 0 1 2 3 4 5 6 7 Response Wait Time (ms) 0 10 20 30 40 50 60 70 Character 8 9 A B C D E F Response Wait Time (ma) 80 90 100 200 300 400 500 600
Note: Even if the response wait time is set at 0, there is a delay of as much as the internal processing time*.
Command
CPU module
Preprocessing Processing
Postprocessing
Response
One scan
One scan
F061107.VSD
G Command
Using three letters, specify the type of access, such as reading or writing, from the host computer or monitor to the sequence CPU module.
G Parameters
Set such data items as a device name, the number of devices and their data values. Available parameter types vary depending on the command you use. No parameter is required for some commands.
IM 34M6P13-01E
6-38
G Checksum
A checksum can be added to the transmission text to check data. Using the program configuration function, you can determine whether or not to add a checksum. If you set the item Checksum to Yes, you must add a checksum to a command which is sent from the host computer or monitor to the FA-M3. In this case, a checksum is automatically added to each response. If the item Checksum is set to No, this code is unnecessary. The calculation of the checksum is explained below. The ASCII codes of characters from the one following the STX code to the one immediately preceding the checksum code in the text are added together on a byte-bybyte basis. The lower-order one byte of the result of performing addition is taken and represented as a hexadecimal number. The 2-character, 2-byte string thus obtained is used as the checksum.
Transmission text (character string) Range of check-sum calculation STX 0 1 0 1 A B R D X 0 0 2 0 1 , 1 6 B 9 ETX CR
Checksum
02 30 31 30 31 41 42 52 44 58 30 30 32 30 31 2C 31 36 42 39 03 0D Hexadecimal ASII code The ASCII codes are added together as "30+31+30+31+41+42+52+44+58+30+30+32+30+31+30+31+2C+31+36=3B9 (hexadecimal)." The checksum is a hexadecimal representation of the lower-order one byte of the result of performing addition. In this case, it is B9.
F061108.VSD
IM 34M6P13-01E
When communication ends successfully, the string OK is returned along with a command response.
Also added to the response only if specified accordingly using the configuration.
F061110.VSD
When communication results in an abnormal end, the string ER is returned along with the codes EC1 and EC2, where: EC1 = Error code EC2 = Detailed error code If the communication failure is due to an error in the CPU number, the received 2-byte CPU number is returned. If the failure is due to an error in the station number, no response is returned. If an ETX code in a command is not received, no response may be returned. If this happens, be sure to perform a timeout process on the host computer or monitor.
IM 34M6P13-01E
04
05 06 08 41 42 43 51 52 F1
- The CPU number is outside the range of 1 to 4. - The command does not exist. Command error - The command is not executable. - The device name does not exist.* Device specification - Incorrectly specified the bit devices in an attempt to read/write error them in units of words. - Attempted to use characters other than 0 and 1 when setting bits.* - Attempted to use values other than 0000 to FFFF when setting w Value outside the ords. range - The starting point in the command, such as Load or Save, is outside the range of addresses. Number of data - The number of bits or words is outside the specified range.* items outside the - The specified number of data items does not match the number range of parameters including device names. - Attempted to execute monitoring without having specified a monitor Monitor error command (BRS or WRS). Parameter error - The parameter is incorrect for a reason other than noted above.* Communication error - An error has occurred during communication.* Checksum error - The check sum is wrong due to missing bits, garbled character, etc. Internal buffer - The amount of data received is larger than the specified. overflow - No end-of-process response is returned from the CPU for reasons Timeout such as a CPU power failure. CPU processing - The CPU has detected an error when processing the command. failure - A Cancel command (PLC) has been issued while neither a Load Internal error command (PLD) nor a Save command (PSV) is in process. - An internal error is found.
IM 34M6P13-01E
6-41
If a parameter error occurs, the detailed error code field indicates the number of the faulty parameter. If a communication error occurs, the detailed error code field indicates details on the error.
Table 6.12 Detailed Error Codes
Error Code (EC1) 03 04 05 Meaning Device specification error Value outside the range Number of data items outside the range Detailed Error Code (EC2) *
The EC2 field provides a hexadecimal representation of the number assigned to the faulty parameter. (The number is one, among the ordinal parameter numbers, at which an error has occurred first.) (Example:) 6 Parameter 1 2 4 5 3 S numbers T 0101ABRW 03 Y00501, 1, I0002, 0, A1234567 X Erroneous device number In this example, the respective error codes take the values shown below. - EC1 = 08 - EC2 = 06
08
Parameter error
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
MSB
LSB
41
Communication error
Each bit has the following meaning. b7: Reserved b6: Reserved b5: Framing error b4: Overrun error b3: Parity error b2: Reserved b1: Reserved b0: Reserved
1 2 4 8 9 A B C F : Self-diagnostic error : Program error (including parameter error) : CPU-to-CPU communication error : Device access error : Protocol error : Parameter error : Operation mode error, or state of protection or exclusive access : Device/block specification error : System's internal error
52
* The EC2 error code has no meaning for any value of EC1 other than those listed above.
IM 34M6P13-01E
Command Response wait time CPU number Station number, which is fixed at 01.
Parameters
F061111.VSD
IM 34M6P13-01E
6-43
Table 6.13 Specifiable Devices
Device Name Xnnnnn Input relay Ynnnnn Output relay Innnnn Internal relay Bit device Ennnnn Shared/extended shared relay Lnnnnn Link relay Mnnnnn Special relay Tnnnnn Timer Cnnnnn Counter Dnnnnn Data register Rnnnnn Shared register Word device Vnnnnn Index register Bnnnnnn File register *3 Wnnnnn Link register Znnnnn Speical Read Length 6 bytes 6 bytes 6 bytes 6 bytes 6 bytes 6 bytes 6 bytes 6 bytes 6 bytes 6 bytes 6 bytes 7 bytes 6 bytes 6 bytes Bit Yes Yes Yes Yes Yes Yes Yes*1 Yes*1 No No No No No No Word Yes Yes Yes Yes Yes Yes Yes*2 Yes*2 Yes Yes Yes Yes Yes Yes Bit No Yes Yes Yes Yes Yes*6 No No No No No No No No Write Word No Yes Yes Yes Yes Yes*6 Yes*2 Yes*2 Yes Yes Yes Yes Yes Yes*6
*1 Specify: a time-out relay as TUnnnn, and an end-of-count relay as CUnnnn, *2 Specify: - the current value of a countdown timer as TPnnnn, - the current value of a countdown counter as CPnnnn, - the current value of a count-up timer*4 as TInnnn, - the current value of a count-up counter*4 as CInnnn, - the setpoint of a timer*5 as TSnnnn, and - the setpoint of a counter*5 as CSnnnn. *3 Only available with the F3SP25, F3SP28, F3SP35, F3SP38, F3SP53, F3SP58, and F3SP59 sequence CPU modules. *4 The countdown type of timers and counters has been made available with the FA-M3 controller for such reasons as viewing them on a host computer. Current value of count-up type timer/counter =Setpoint-Current value of countdown type timer/counter *5 The timer setpoint TSnnnn and counter setpoint CSnnnn are not available for a word writing command. *6 In the case of F3SP28, F3SP38, F3SP53, F3SP58, and F3SP59 sequence CPU modules, writing to this device is not possible with any of BWR, BFL, WWR and WFL commands. Alternatively, use a BRW or WRW command.
IM 34M6P13-01E
IM 34M6P13-01E
6-45
IM 34M6P13-01E
6-46
F061301.VSD
In Figure 6.36, the ABC and EFG123 instructions are macro instructions. When the CPU encounters the ABC instruction, it executes the called-side ABC macro instruction entity like a subroutine, using operands D0001 and D0002 as its parameters. Macro instructions are created by ladder-macro editing separately from regular instructions created in ladder-diagram editing. The MRET (macro return) instruction represents the end of the macro instruction. For details on operands P01, P02, and U01 in the figure, see subsection 6.13.3, "Devices Dedicated to Macro Instructions.
IM 34M6P13-01E
6-47
SEE ALSO
For details on the Macro Return (MRET) instruction, see Section 3.13.4, "Macro Call (MCALL), Parameter (PARA), Macro Return (MRET), of "Sequence CPU Instruction Manual - Instructions" (IM34M6P12-03E, 3rd Edition).
IM 34M6P13-01E
6-48
I Purpose
Using macro instructions offers the following two advantages.
Reuse subroutines? Yes Search for subroutines Find I/O data Mention the devices used internally Copy subroutines (Note) Match I/O data with data of devices used internally End
No
Presence/absence of instructions
Absent
Present Create subroutines newly Check specifications Input of instructions End Create new instructions
Note: 1. Copy a block containing subroutines under a different name. 2. Delete components other than subroutines from a circuit diagram. 3. In ladder-diagram editing, read the copying-destination block.
F061303.VSD
G Accumulating Expertise
You can accumulate your control expertise in the form of macro instructions to customize your FA-M3 controller.
IM 34M6P13-01E
G Macro Call
The Macro Call instruction can pass up to 16 parameters.
INLET1 = =
F061304.VSD
Macro instruction
IM 34M6P13-01E
6-50
Types Macro Call (MCALL) Input Macro Instruction Call (NCALL) Structure Macro Instruction Call (SCALL)
Instruction
Mnemonic
Macro Call Parameter Macro Return Input Macro Instruction Call Output of Input Macro Structure Macro Instruction Call
IM 34M6P13-01E
6-51
Table 6.18 Relationship between Pointer Registers and Macro Instruction Operands
Operand No. Pointer Register No.
1 2 3 4
16
P16
F061306.VSD
Using a basic or Application Instruction, you can read from and write to pointer registers in a macro instruction just like devices passed as parameters. You can also apply a word/long word process, index modification process, and automatic BIN-to-BCD or BCD-to-BIN conversion process to these pointer registers. High speed processing of Application Instructions is not performed, however. More specifically, high speed processing does not apply to MOV, CAL, CMP, or logical operation instructions that use pointer registers as operands in a macro instruction.
TIP
When executing two or more instructions that use pointer registers(P), it is recommended that you first transfer the values of the pointer registers(P) to macro relays(H)/registers(A). Then, execute two or more instructions that use these macro relays(H)/registers(A). This strategy reduces the instruction execution time.
SEE ALSO
For details on basic and application instructions, see Sections 2.1 and 3.1 of the "Sequence CPU Instruction Manual - Instructions" instruction manual (IM34M6P12-03E).
IM 34M6P13-01E
6-52
X00502 MOV PARA 1 4 V01 V01 R0001 P04=R0002
M P01=D0001 D0001 EFG123 I0001 Y00301 P02=I0001 (Mnemonic: MCALLEFG123 D0001 I0001 Y00301) P03=Y00301 "EFG123" macro instruction entity (called side) M033 MOV MOV P04 = U01 P01 1 2 + A0001 U01 A0001
Pointer registers in a called-side macro instruction entity (Note) R0002 = U01 D0001
A0001 MRET
F061307.VSD
Note: This register can be used in the called-side macro instruction entity.
CAUTION
If you pass a device accompanied by an index modification device to a macro instruction as a parameter, the instruction receives an already index-modified device. In the example of Figure 6.39, the parameter R0001;V01 equals the device R0002 because V01 = 1. Any index modification in a pointer register (P) applies to a parameter that is passed. In the example of Figure 6.39, the parameter P01;U01 equals the device D0003 because P01 = D0001 and U01 = 2
I Macro Relays (H), Macro Registers (A) and Macro Index Registers (U)
These devices are dedicated to macro instructions. Using a basic or Application Instruction, you can read from and write to a macro relay, macro register and macro index register in a called-side macro instruction entity just like an internal relay (I), data register (D) and index register (V). These devices can be used for called-side macro instruction entities. You can use these devices in your macro instruction without having to be aware which devices are used in the instruction when applying the instruction. Needless to say, the values of these devices are retained.
IM 34M6P13-01E
The Structure Pointer Register is a special register used to pass structure data to structure macro instructions. It is used by structure macro instruction entities (called side). The relationship between the structure pointer register (Q) and structure macro instruction parameters is shown in the figure below.
S ROAD STR1 STR2 Parameter 2 Parameter 1
F061308.VSD
Table 6.19 Relationship between a Structure Pointer Register (Q) and Structure Macro Instruction Parameters
Operand 1 (parameter 1) 2 (parameter 2) Structure pointer register number Q01 Q02
Structure data In a structure macro instruction body (called side) can be read or written using basic and application instructions with the "<structure pointer register number>.<structure member name>" format. Word processing, long-word processing and automatic binary-BCD conversion can be used with structure pointer registers, index modification is not allowed. In addition, high-speed processing of application instructions is also not available. Thus, Move (MOV), Arithmetic Computation (CAL), or logical operation instructions that operates on parameters specified by a structure pointer register (Q) in a structure macro instruction are not processed at high-speed.
TIP
Instead of coding several instructions that use a structure pointer register (Q), you can first transfer the member data to macro relays (H) and macro registers (A) and then code instructions to use these relays and registers instead. In this way, you can shorten the execution time.
SEE ALSO
For details on basic and application instructions, see Sections 2.1 and 3.1 of the "Sequence CPU Instruction Manual - Instructions" instruction manual (IM34M6P12-03E).
SEE ALSO
For details on structures, see "FA-M3 Programming Tool WideField2 Instruction Manual" (IM 34M6Q15-01E).
IM 34M6P13-01E
6-54
6.13.4
Called Side Macro Input macro Structure macro Macro Input macro Structure macro Macro Input macro Structure macro Macro Input macro Structure macro
Availability
Call is allowed (PARA instruction can be used) Parameters passed using the PARA instruction are overwritten. Call is not allowed.
CAUTION
Parameters 1 to 3 passed to macro instructions are saved when macro instructions are nested. However, parameters 4 to 16 passed using PARA (parameter) instructions are not saved. If a Parameter (PARA) instruction is executed in a called macro instruction, the relevant parameters are overwritten.
CAUTION
Errors generated in nested macro instructions are reported as errors of the first macro instruction.
SEE ALSO
For details on the Parameter instruction, see Section 3.13.4, "Macro Call (MCALL), Parameter (PARA), Macro Return (MRET), of "Sequence CPU Instruction Manual - Instructions" (IM34M6P12-03E, 3rd Edition).
IM 34M6P13-01E
6-55
When nesting macro instructions, you may mistakenly overwrite macro devices, such as relays, registers and index registers, in a called macro instruction and thereby destroy their data. To avoid this problem, check the depth of macro instruction nesting stored in special register Z106 and use macro devices separately for each level of nesting depth (see the example below).
X00501 M NEST1 NEST1 macro instruction entity X00502 U01 0 U01 A01 = = Z106 0 P1 + 1 * 64 D0001 D0002 0
A01 (A001 to A064 can be used) M NEST2 U01 = U01 A01 Z106 P2 * 0 6 4
A65 (A065 to A128 can be used) M NEST3 U01 = U01 A01 Z106 P2 * 0 64
Figure 6.40 Example of Using Macro Devices Separately when Nesting Macro Instructions
IM 34M6P13-01E
6-56
6.13.5
An error also occurs and the special relay M201 for instruction processing errors is set to ON if: - an MRET ladder macro instruction return is executed before an MCALL macro instruction call (special register Z022 contains the error code $2501), or - the depth of macro instruction call nesting exceeds 7 levels (special register Z022 contains the error code $2502). An error encountered in a called-side macro instruction entity is viewed by the user as an error in a calling-side macro instruction. Thus, the user can know which parameters were passed to the macro instruction.
CAUTION
An error, except a check-sum memory error, found by self-diagnosis in a called-side macro instruction entity is also viewed by the user as an error that has occurred as the result of executing a calling-side a macro instruction.
It is not possible to determine in which downloaded-type macro instruction a check-sum memory error is found. Therefore, the error is recognized when it is detected, rather than when the macro instruction is executed.
Table 6.21 Error Codes for Macro Instructions
Error Type Instruction processing Error Name Macro instruction error Error Code $2502 $2501 Description Three is o return destination The upper limit of nesting depth, i.e., seven levels, has been exceeded.
IM 34M6P13-01E
6-57
6.13.6
Tip
Executable program protection and block protection are effective for user-created ladder programs that contain macro instructions. If for example, executable program protection is enabled, any act of working with executable programs, such as downloading, uploading, monitoring or online-editing, becomes impracticable.
6.13.7
Debugging Operation
I Forced-Set/Reset
You can also turn on and off bit devices forcibly in calling-side and called-side macro instructions.
I Partial Operation
Partial operation is not possible with called-side macro instructions.
IM 34M6P13-01E
6-58
6.13.8
F3SP
- S
An Input Macro Instruction is a type of macro instruction that can be used as an input condition, just like the Load or Compare instruction. It can represent complex, reusable input conditions as a single instruction. By calling the Output of Input Macro (NMOUT) instruction internally, an input macro instruction can also output the result of logical operation to its subsequent instruction.
INLET1 = =
F061309.VSD
Macro instruction
How to Use
Creating an Input Macro Instruction
Input macro instructions can be created like ordinary macro instructions. Macro instructions called by the Input Macro Instruction Call (NCALL) instruction are called input macro instructions. Therefore, the same macro instruction entity can be either an input macro instruction (if called by NCALL) or a macro instruction (if called by MCALL).
SEE ALSO
For details on the NCALL instruction, see "Sequence CPU Instruction Manual - Instructions" (IM34M6P12-03E, 3rd Edition).
SEE ALSO
For details on the pointer register (P), see Section 6.13.3, "Devices Dedicated to Macro Instructions."
IM 34M6P13-01E
6-59
Output of Logical Operation Result to the Power Rail
Specifies the logical operation result of an input macro instruction. The logical operation result to be output to the step following the Input Macro Instruction Call instruction depends on the status of the input parameter of the input macro instruction.
Input Parameter Constant Relay device Register device Logical Operation Output of Input Macro (device status = output) OFF if 0, ON if otherwise OFF if 0, ON If 1 OFF if 0, ON if otherwise
If NMOUT is executed more than once, the last instruction takes precedence. If no NMOUT instruction is executed, the logical operation result of an input macro is OFF.
SEE ALSO
For details on the NMOUT instruction, see "Sequence CPU Instruction Manual - Instructions" (IM34M6P12-03E, 3rd Edition).
CAUTION
NMOUT takes effect only if executed in a macro (input macro) instruction that has been called by NCALL. It is ignored if executed in a macro instruction that has been called by MCALL.
IM 34M6P13-01E
6-60
F3SP
- S
The Structure Macro Instruction passes a number of parameters collectively in a structure to a macro instruction. By using a structure, it simplifies data passing and improves representation when there are many related parameters.
Passing all data in a structure called MITAKA Ladder block S ROAD S ROAD MITAKA 0 Macro instruction (ROAD) STRCT Q1.Road_Val MOV FUCHUU 0
Q1.Road_Frm D0001 Q1 CITY
F061310.VSD
SEE ALSO
For details on structures, see "FA-M3 Programming Tool WideField2 Instruction Manual" (IM 34M6Q15-01E).
CAUTION
A structure macro instruction may not call another structure macro instruction. A structure macro instruction may be called only by a block.
CAUTION
If the type of a structure passed using a structure macro instruction is different from the structure type declared by a structure pointer declaration instruction in the called structure macro instruction, the latter structure type is used during execution with no error generated.
CAUTION
Structure macros use P4 to P8.
IM 34M6P13-01E
SEE ALSO
For details on the SCALL instruction, see "Sequence CPU Instruction Manual - Instructions" (IM34M6P12-03E, 3rd Edition).
SEE ALSO
For details on the structure pointer registers (Q), see Section 6.13.3, "Devices Dedicated to Macro Instructions."
IM 34M6P13-01E
6-62
User log information storage area Stored by means of overwriting in the order of occurrence Rotarybuffer format
95/09/26 95/09/26
14:10:52 14:21:12
12-05 17-04
F061401.VSD
CAUTION
In some cases, WideField2 may show two identical logs. This happens when you execute a user log instruction to store a new user log while reading a stored use log using WideField2. To prevent this from occurring, view user logs when you are not executing a user log instruction.
SEE ALSO
For details on the instructions related to user log, see "Sequence CPU Instruction Manual Instructions" (IM34M6P12-03E, 3rd Edition).
IM 34M6P13-01E
6-63
TIP
You may assign values in the range -32768 to +32767 to user log main codes. Messages for main codes 1 to 64 can be stored in a CPU module.
TIP
You may also assign values in the range -32768 to +32767 to user log sub codes.
IM 34M6P13-01E
6-64
6.15
6.15.1
Input refreshing Interruption of execution Program execution Output refreshing Common processing
200-s minimum fixed interval
Output refreshing
F061501.VSD
IM 34M6P13-01E
6-65
6.15.2 Features
I Features
The sensor control function has the following features.
G High Speed
The minimum interval of block execution is as short as 200 s. The sequence CPU module operates as if it contains another sequence CPU module with the minimum scan time of 200 s. The maximum I/O response delay is only 400 s, i.e., twice the minimum interval of block execution. It is possible to use a process requiring fast I/O responses by isolating it from a regular program. It is possible to use a wide choice of modules, including multifunctional modules, for the input/output of the function.
G Fixed Intervals
The sensor control block is executed at fixed intervals. The sensor control block function works even while instructions in a normal scan are being executed or refreshed, or common processing is in progress.
IM 34M6P13-01E
6-66
6.15.3
I Specifications
Table 6.23 Specifications of Sensor Control Block
Item Number of sensor control blocks Interval of execution Applicable module Unit of I/O-refreshed devices Maximum number of I/O-refreshed words Applicable instructions Applicable device Maximum program execution time Initial condition at the moment of normal program execution Interrupt timing Interrupt priority Others 1 200 s to 25.0 ms, in 100 s increments Specifications
All types of modules. See the cautionary notes on the next page.
One-word basis, i.e., in units of 16 relays or terminals. 4 to 512. See below. All instructions, except for the Timer, Special Module Highspeed Read (HRD), and Special Module High-speed Write (HWR) instructions
For details on writing to relay devices, see Section 6.15.7, "Programming Precautions."
Can be defined as "after completion of instruction execution" or "immediate, during instruction execution"-default Sensor control block has priority (default) or input interrupt has priority. See below. Start, stop or interrupt prohibition by means of instruction or tool.
I Applicable Modules
There is no restriction on the types of applicable module, however, observe the cautionary notes given on the next page.
CAUTION
Cautionary notes on setting the Terminal Usage in the in DIO setup Using the configuration function in WideField2, edit this item to determine whether I/O modules are refreshed by means of the sensor control block or a normal scan. The settings of all devices, including X input relays and Y output relays, are common to normal scans. Configure an input module on a long-word basis in units of 32 relays or terminals, from terminals 1 to 32 or 33 to 64, and an output module on a word basis in units of 16 relays or terminals. Avoid inadvertently configuring the input module on a word basis, such as using terminals 1 to 16 for a normal scan and terminals 17 to 32 for the sensor control block. Otherwise, refreshing based on the sensor control block takes place during the normal scan since input refreshing is performed on a long-word basis. This means X input relays used for the normal scan are refreshed and, therefore, the simultaneity of data before and after this refreshing is not guaranteed. The simultaneity of data is also not guaranteed for X input relays used in the sensor control block.
IM 34M6P13-01E
6-67
CAUTION
Relationship between shared refreshing and link refreshing In I/O refreshing based on the sensor control block, shared and extended shared relays (E), shared and extended shared registers (R), link relays (L) and link registers (W) are not refreshed. Instead, these devices are refreshed during common (synchronization) processing in a normal scan.
IM 34M6P13-01E
6-68
I Maximum Number of I/O-refreshed Words
The number of words defined using the configuration function as those to be refreshed, is limited by the type of unit-either main unit or subunit-where the module in question is installed, by the time interval of block execution, or by the number of CPU modules including a BASIC CPU module. See Table 6.24 below for details. Calculate the number of words according to the following equation. Number of I/O-refreshed words = (Number of words of I/O modules in main unit to be refreshed) + (Number of F3XH04 modules in main unit to be refreshed that use pulse catch function) + (Number of words of I/O modules in subunit to be refreshed) x 4 (Number of F3XH04 modules in subunit to be refreshed that use pulse catch function) x 4
Table 6.24 Maximum Number of I/O-refreshed Words Handled by Sensor Control Block for each CPU
Execution Interval 200s 300s 400s 500s 1 ms 2 ms 3 ms 4 ms 5 ms 10 ms 20 ms 25 ms Maximum Number of I/O-refreshed Words One CPUs Two CPUs Three CPUs Four CPUs 4 0 0 0 8 4 0 0 12 4 4 0 16 8 4 4 36 16 12 8 76 36 24 16 116 56 36 28 156 76 52 36 196 96 64 48 396 196 132 96 512 396 264 196 512 496 332 248
Example 1: Number of CPU modules installed: 2 Execution interval of sensor control block at CPU 1: 1 ms Sum of CPU-1 input-refreshed and output-refreshed words : Should be kept below 16. Execution interval of sensor control block at CPU 2: 500 s Sum of CPU-2 input-refreshed and output-refreshed words : Should be kept below 8. The maximum number of I/O-refreshed words is proportional to the execution interval. Calculate the maximum number for any execution interval not found in Table 6.24 by referring to the numbers for the execution intervals immediately above and below that maximum number. Example 2: Number of CPU modules installed:1 Execution interval of sensor control block: 600 s Maximum number of I/O-refreshed words: 20 It is not possible to sustain the execution interval of the sensor control block if the maximum number of I/O-refreshed words is exceeded. This may result in a sensor control block scan time-out error. See subsection 6.15.6, Error Handling, for details on operation in the case of this error.
IM 34M6P13-01E 2nd Edition : Oct 1, 2002
6-69
I Maximum Program Execution Time
In the case of the sensor control block, keep the program execution time as short as possible. Otherwise, a program being executed under a normal scan will be interrupted for a longer period of time. Consequently, the time interval of the normal scan becomes longer. Calculate the maximum time of this program execution according to the equation given below. If this maximum time is exceeded, a sensor control block scan time-out error may result because the CPU fails to sustain the execution time of the sensor control block. See subsection 6.15.6, Error Handling, for details on operation in case of this error. Maximum program execution time (s) = (Maximum number of I/O-refreshed words discussed earlier - Number of actually refreshed words) x Number of CPU modules installed x 25 s + 50 s Example 1: Execution interval: 200 s Number of CPU modules installed:1 Execution interval of sensor control block: 600 s Maximum number of I/O-refreshed words: 4 (from Table 6.19) Number of actually refreshed words: 2 Maximum program execution time = (4 - 2) x 1 x 25 + 50 = 100 s The sensor control block, if composed of basic instructions only, is equivalent to a program with the following number of steps. 100/0.09 = 1111 steps = Approximately 1.1 K steps (for F3SP28 and F3SP38 CPU modules) 100/0.035 = 2856 steps = Approximately 2.8 K steps (for F3SP53, F3SP58 and F3SP59 CPU modules) Example 2: Execution interval: 1 ms Number of CPU modules installed:1 Maximum number of I/O-refreshed words: 36 (from Table 6.19) Number of actually refreshed words: 6 Maximum program execution time = (36 - 6) x 1 x 25 + 50 = 800 s The sensor control block, if composed of basic instructions only, is equivalent to a program with the following number of steps. 800/0.09 = 8888 steps = Approximately 8.7 K steps (for F3SP28 and F3SP38 CPU modules) 800/0.035 = 42865 steps = Approximately 41.8 K steps (for F3SP53, F3SP58 and F3SP59 CPU modules)
IM 34M6P13-01E
6-70
6.15.4
I Interrupt Timing
Using the configuration function of WideField2, set the interrupt timing of the sensor control block for a case when a program is being executed. There are two options for the interrupt timing, as shown in Table 6.27.
Table 6.27 Interrupt Timings of Sensor Control Block
Interrupt Timing After completion of instruction execution Immediate, during ladder instruction execution (default) Description The CPU switches to the sensor control block after the completion of instruction execution. It does not, however, switch to the sensor control block during common processing or refreshing. The CPU switches to the sensor control block during ladder instruction execution. It also switches to the sensor control block during common processing or refreshing.
IM 34M6P13-01E
6-71
Program execution in normal scan LD OUT LD BMOV Input refreshing Sensor control block
Figure 6.45 Interrupt by Sensor Control Block after Completion of Instruction Execution
Figure 6.46 Immediate Interrupt by Sensor Control Block during Instruction Execution
IM 34M6P13-01E
6-72
Table 6.28 summarizes differences between these two interrupt timings.
Table 6.28 Differences between Two Interrupt Timings
Item Interrupt by Sensor Control Block after Completion of Instruction Execution Processing time of instruction being executed (Note 1) + Switchover processing time (Note 2), or Synchronization processing time (Note 3) + Common processing time (Note 3) + Input refreshing time (Note 3) + Switchover processing time (Note 2) Guaranteed for each instruction Immediate interrupt by Sensor Control Block during Instruction Execution
Note 1: See the table of commands in Appendix of the 2nd or later edition of, Sequence CPU Instruction Manual Instructions (IM34M6P12-03E), for details on the instruction processing time. Note 2: 9 to 30 s for F3SP28 and F3SP38 CPU modules and 3 to 10 s for F3SP53, F3SP58 and F3SP59 CPU modules Note 3: See Section 7.1, "Information on Scan Time."
CAUTION
Execution interval setting when the interrupt timing is after completion of instruction execution For interruption by the sensor control block after completion of instruction execution, set the execution interval at 1 ms or longer. In this type of interruption, the CPU does not switch to the sensor control block during common processing or refreshing. Although the common processing time or refreshing time varies depending on the time interval of synchronization processing, such as shared refreshing or link refreshing, it must be at least 1 ms. Otherwise, It is not possible to sustain the execution interval of the sensor control block. This may result in a sensor control block scan time-out error. Debug operation when interrupt is set to occur after completion of instruction execution: If the timing of interrupts is set to "After Instruction," the sensor scan time exceeded error may occur when switching from Run to Debug mode or from Debug to Run mode, or when canceling a forced set/reset in Debug mode.
IM 34M6P13-01E
6-73
CAUTION
Simultaneity of data when the interrupt timing is immediate, during instruction execution When interruption by the sensor control block is immediate, during instruction execution, there is no simultaneity of multiple devices data. For example, consider the case in Figure 6.46 where the sensor control block is executed when a BMOV block transfer instruction is being executed in a normal scan. The data in the source of block transfer is rewritten before and after the execution of the sensor control block or data being blocktransferred may be read in the sensor control block. The time the simultaneity of data is required is when multiple devices data is exchanged between a normal-scan program and an input interrupt program by using a BMOV block transfer instruction, a long-word instruction containing a floating point, or two or more instructions. If the simultaneity of data is required in the case of immediate interruption by the sensor control block during instruction execution, follow either of the two instructions given below. 1. Use CBD (Sensor Block Disable) and CBE (Sensor Block Enable) instructions to prevent the sensor control block from being executed when exchanging data of multiple devices. 2. Use an application program to carry out flag control using relays between a normal-scan program and the sensor control block.
IM 34M6P13-01E
6-74
I Interrupt Priority
Using the configuration function of WideField2, determine priority when the timing of interrupt from an input module coincides with the interrupt timing of the sensor control block. Table 6.29 shows the two options of interrupt priority.
Table 6.29 Options of Interrupt Priority and Their Functionality
Interrupt Priority Functionality When an interrupt from an input When the time of executing the module occurs during execution of sensor control block arrives during the sensor control block input interrupt processing Aborts the interrupt once and resumes Executes the interrupt process after the process after executing the sensor executing the sensor control block. control block. Aborts the execution of the sensor control block once and resumes the Executes the sensor control block after execution after executing the input executing the input interrupt process. interrupt process.
TIP
The sequence CPU follows the rules of execution timing (after completion of instruction execution or immediate, during instruction execution) discussed above, even when the execution of the sensor control block or input interrupt process is aborted due to the interrupt priority.
SEE ALSO
For details on the instructions, see "Sequence CPU Instruction Manual - Instructions" (IM34M6P12-03E), edition 3 or later.
TIP
When the sensor control block stops, the CPU holds or resets the data of Y output relays used or refreshed by the sensor control block, according to the setting of the configuration item Hold/reset output in case of program stop. When the sensor control block is enabled, the relays are always set to the Hold option.
TIP
The initialization processing of timers, counters and the destinations of OUT instructions does not apply to the sensor control block enabled or disabled by ACT/INACT instructions.
IM 34M6P13-01E
6-75
I Enabling/Disabling Sensor Control Block
You can temporarily disable the sensor control block using a CBD (Control Block Disable) instruction or enable the sensor control block using a CBE (Control Block Enable) instruction. The CPU does not execute the sensor control block if disabled, until it is enabled. The CPU immediately begins executing the block as soon as it is enabled.
Table 6.31 Instructions to Disable and Enable Execution of the Sensor Control Block
Instruction CBD Instruction CBE Instruction Description Disables execution of the sensor control block. Enables execution of the sensor control block.
SEE ALSO
For details on the instructions, see "Sequence CPU Instruction Manual - Instructions" (IM34M6P1203E, 3rd Edition).
CAUTION
If the interval of execution disable is too long for the CPU to be able to execute the sensor control block at fixed intervals, a sensor control block scan time-out error will result. Consequently, the CPU stops executing the sensor control block. See subsection 6.15.6, Error Handling, for more information.
I On-for-one-scan-at-CB-startup Function
This function causes a special relay (M) to remain turned on for one scan-during the first execution of the sensor control block, when the sensor control block is activated.
Table 6.32 Special Relay for One Scan at the Startup of Sensor Control Block
No. M097 Name Status Description Remains turned on for one scan during the first execution of the sensor control block when the sensor control block is activated. ON: When the sensor On-for-one-scancontrol block is at-CB-startup relay activated OFF: Other cases
TIP
The on-for-one-scan-at-CB-startup relay turns on when a CBACT (Control Block Activate) instruction is executed. It then turns off at the end of the first execution of the sensor control block.
IM 34M6P13-01E
6-76
I Execution Status
The CPU stores in a special relay (M), the status of whether the sensor control block is enabled or disabled.
Table 6.33 Special Relay for Execution Status of Sensor Control Block
No. M137 Name CB-execution-status relay Status ON: Enabled OFF: Disabled Description Indicates the operating status of the sensor control block.
TIP
The status of the sensor control block is updated when a CBACT (control block activate) instruction is executed, or during normal-scan input refreshing after error detection when a CBINA (control block deactivate) instruction is executed.
F061505.VSD
Figure 6.47 Schematic Diagram Showing Execution Time of Sensor Control Block
Table 6.34 Special Registers (Z) for Execution Time of Sensor Control Block
No. Z109 Z111 Name CB-execution-time register Maximum-CB-execution-time register Description Indicates the time (in units of 10 s) taken from when input refreshing for the sensor control block is started, followed by program execution, to when output refreshing is completed. Indicates the maximum time (in units of 10 s) taken to execute the sensor control block.
TIP
The execution time of the sensor control block is updated at each normal-scan input refreshing process.
IM 34M6P13-01E
6-77
TIP
You can use the sensor control block, irrespective of whether the setting of the option of the configuration item method of program execution, is Execution of all blocks or Execution of specified blocks.
IM 34M6P13-01E
6-78
CAUTION
If I/O module failures are found during I/O refreshing in the sensor control block, the CPU only informs the first-found failure by means of an alarm indicator.
Sensor control block scan timeout (Special relay M212 turns on.)
Other errors
Run or Stop status depending on the option of the configuration item "Operation Stops in case of sensor control block scan timeout error" For errors with a configuration item defining operation when there is an error, the sensor control block either runs or stops depending on the item's option. The block stops if there is no such configuration item.
TIP
If an error is encountered in the sensor control block, the block number for which the error is found and which is stored in a special register is the last block number of a regular program with an increment of 1. Table 6.39 Action of Sensor Control Block when an Error Is Found in Normal Scan
Type of Error All types of error Action For errors with a configuration item defining operation when there is an error, the sensor control block either runs or stops depending on the item's option. The block stops if there is no such configuration item.
IM 34M6P13-01E
6-79
6.15.7
Programming Precautions
Instruction TIM Corrective Actions Enable/disable timers in a regular block. Reference to timer relays is possible, however.
Special Module High-speed Use the Special Module Read (READ) instruction instead. Read (HRD) Special Module High-speed Use the Special Module Write (WRITE) instruction instead. Write (HWR)
Example: If a sensor control block controls I00032, the normal program steps may not control I00017 to I00031. Figure 6.48 When Outputting to Relays
F061506.VSD
IM 34M6P13-01E
6-80
G Data simultaneity of devices to be refreshed
It becomes impossible to sustain the simultaneity of data if, in the sensor control block, an access is made to I/O relays refreshed in a regular block among other I/O relays, or to shared/extended shared relays (E), shared/extended shared registers (R), link relays (L), or link registers (W). The sensor control block is executed during a normal-scan input and output refreshing even when the CPU is performing common processing. If you read any of the abovementioned devices in the sensor control block, a data value being refreshed may be read. Likewise, if you write to the device, the data value being refreshed may be rewritten. Consequently, the CPU may fail to sustain the simultaneity of data. To prevent the sensor control block from being executed during normal-scan input refreshing, output refreshing or common processing, execute a CBD instruction for disabling the block at the end of a regular program and execute a CBE instruction for enabling the block at the beginning of the program.
IM 34M6P13-01E
6-81
F3SP
- S
The partial download function allows only specified blocks/macros to be downloaded to a CPU overwriting the corresponding blocks/macros of a program that has been downloaded earlier. This reduces downloading time and improves debugging efficiency, especially in largescale program development by a group of developers. This function is available only in STOP mode. It allows multiple blocks or macro instructions to be specified. Addition or deletion of block/macro instructions that are downloaded using the partial download function are not allowed.
Personal computer Downloading only blocks 2 and 4 from personal computer to CPU and hence replacing only blocks 2 and 4 in the CPU. Block 1 Function 1 Block 2 Function 2' Block 3 Function 3 Block 4 Function 4'
F061601.VSD
Executable program Block 1 Function 1 Block 2 Function 2 Block 3 Function 3 Block 4 Function 4
Programmer A Programmer B
Programmer A partially downloads block 4 and debugs them. Programmer B partially downloads block 2 and debugs them. Block 1 Function 1 Block 2 Function 2 Block 3 Function 3 Block 4 Function 4
Executable program Block 1 Function 1 Block 2 Function 2 Block 3 Function 3 Block 4 Function 4
F061602.VSD
IM 34M6P13-01E
6-82
CAUTION
If an error occurs at the time of partial downloading, the step count of the error block becomes 0. If you then upload this defective program to a personal computer, the step count for the corresponding block on the personal computer will also be 0. If you have to upload such a program, save it under a different project name.
CAUTION
At the completion of partial downloading, program checking and optimization are performed and this may take some time.
IM 34M6P13-01E
6-83
F3SP
- S
You can store circuit comments and subcomments to the CPU module. Storing comments in the CPU module allows you to display them during circuit monitoring even if there is no project.
TIP
This function can only store circuit comments and subcomments. To store I/O comments, use the function for storing tag name definitions to CPU.
SEE ALSO
For details on block properties and program downloading, see "FA-M3 Programming Tool WideField2 Instruction Manual" (IM 34M6Q15-01E).
CAUTION
Note that if you turn off the checkbox for storing comments to the CPU when you execute the download program function, comments will not be downloaded to the CPU module regardless of the block properties setup.
IM 34M6P13-01E
6-84
TIP
- Example: Assume that a comment is a character string consisting of four single-byte character and five double-byte characters. Summing the step counts of individual characters yields: 4 0.25 (for single-byte characters) 5 0.5 (for double-byte characters) = 3.5 (steps) Rounding up to the nearest integer yields: Step count of the character string = 4 (steps) Adding 1 step for comment offset: Step count of the comment = 4 1 = 5 (steps)
CAUTION
One step of comment offset is added for each comment to the step count for a program even if the comments are not downloaded.
IM 34M6P13-01E
6-85
CAUTION
If you have added circuit comments or subcomments using offline program editing, you should download the circuit comments and subcomments to the CPU module again.
IM 34M6P13-01E
6-86
F3SP
- S
This function stores common, block, and macro tag name definitions along with a program to either the program memory of a sequence CPU module or the ROM pack. If tag name definitions are to be stored in the program memory of a sequence CPU module, the sum of the program and tag name definition step counts must be within the capacity of the program. If tag name definitions are to be stored in the ROM pack, the sum of the program and tag name definition step counts must be within the capacity of the ROM pack.
Table 6.40 Program Capacity for Storing Tag Name Definitions
CPU Module F3SP28-3S F3SP53-4S F3SP38-6S F3SP58-6S F3SP59-7S Where to Store CPU memory RK33-0N RK73-0N CPU memory RK33-0N RK73-0N CPU memory RK33-0N RK73-0N RK93-0N CPU memory RK33-0N RK73-0N RK93-0N Program Only 30K steps 56K steps 120K steps 56K steps 120K steps 120K steps 254K steps 56K steps 120K steps 254K steps Program plus Tag Name Definitions 30K steps 56K steps 120K steps 56K steps 56K steps 120K steps 120K steps 56K steps 120K steps 360K steps 360K steps 56K steps 120K steps 360K steps
For the step count of tag name definitions, check the project properties, the block tag name definition properties for each block, or the macro tag name definition properties for each macro instruction. You can separately specify whether to download common, block, and macro tag name definitions using the project properties, the block tag name definition properties for each block, or the macro tag name definition properties for each macro instruction. In addition, at the time you execute the download program function, you can choose to disable the downloading of tag name definitions, regardless of the properties setup. If you specify not to download tag name definitions when you execute the downloading program function, any tag name definitions previously downloaded will be erased after the download. If you edit tag name definitions online, the tag name definition files on the personal computer will be updated but not those in the program memory of the CPU module. If changes are made to the tag name definitions, download them to the CPU module again.
TIP
For better programming efficiency, we recommend that you maintain the tag name definitions on the personal computer without storing them in the CPU module during debugging and program development, and download the tag name definitions to the CPU module after the programs are debugged.
IM 34M6P13-01E
6-87
6.19 Structures
F3SP
- S
A structure represents a group of data under a unified name. It improves device representation and program readability. The instructions related to structures are:
- Structure Move (STMOV) - Structure Pointer Declaration (STRCT) - Structure Macro Instruction Call (SCALL)
SEE ALSO
For details on structures, see "FA-M3 Programming Tool WideField2 Instruction Manual" (IM 34M6Q15-01E).
SEE ALSO
For details on the instructions, see "Sequence CPU Instruction Manual - Instructions" (IM34M6P12-03E, 3rd Edition or later).
IM 34M6P13-01E
Blank Page
7-1
7.
7.1
IM 34M6P13-01E
7-2
Table 7.1 Scan Time of System of Control-related Processes
Item
Common processing Program execution Output refreshing
Processing Task
Self-diagnosis Executes ladder programs. The scan time is calculated sing the program execution time or output refreshing time, whichever is greater. Writes the contents of Y output relays to an output module. Updates the contents of shared/extended shared relays (E) and shared/extended shared registers (R) when an add-on CPU is installed and shared refreshing is set as a controlrelated process. In a single refreshing cycle, this task updates the contents of shared/extended shared relays (E) or shared/extended shared registers (R) included in the configuration setting, for each CPU. Not performed if no add-on CPU module is installed or shared refreshing is set as a peripheral process. Write the contents of input modules to a CPU input relays (X). Fixed at 0.2 ms
Processing Time
The scan time is the sum of the execution times of basic and advanced instructions. It varies depending on the execution time of each instruction word. See Section 7.5, "Instruction Execution Time," for more information. 12 s number of modules calculated on a 16-points basis*
Shared refreshing
When an add-on CPU module is installed and shared refreshing is set as a controlrelated process: 0.003T(number of relays set in the sequence CPU module for refreshing /32+number of registers set in the sequence CPU module for refreshing/2)+0.10 ms, if the sequence CPU module for which the devices are refreshed is F3SP28, F3SP38, F3SP53, F3SP58 or F3SP59. 0.014T(number of relays set in the sequence CPU module for refreshing/32+number of registers set in the sequence CPU module for refreshing/2)+0.10 ms, if the sequence CPU for which the devices are refreshed is other than F3SP28, F3SP38, F3SP53, F3SP58 and F3SP59.
0.00ms
Input refreshing
6 s number of modules calculated on a 16- points basis* - When output relays (Y) are used: 8 s number of modules calculated on a 16-points basis* - When FA link modules are used: 0.003T(number of relays used in FA link for refreshing/16+number of registers used in FA link for refreshing)+0.05 ms. - When an add-on CPU module is installed and shared refreshing is set as a control-related process: 0.002x (number of relays set in local CPU/32+number of registers set in local CPU/20)+0.05 ms. - When an add-on CPU module is installed and shared refreshing is set as a peripheral process: 0.002x (number of relays set in CPU for refreshing/32+number of relays set in local CPU/32+number of registers set in CPU for refreshing/2+number of registers set in local CPU/20)+0.05 ms. Minimum peripheral processing time (0.2 ms if not yet configured) or sum of program execution time + output refreshing time, whichever is greater.
Ensures synchronization and the simultaneity of data for operation- and control-related Synchronization processes between the processing system of control-related processes and the system of peripheral processes.
Peripheral processing
* Relationship between Types of I/O Module and Number of Modules Calculated on a 16-points Basis
Type of I/O Module 4-point I/O relay 8-point I/O relay 14-point I/O relay 16-point I/O relay 32-point I/O relay 64-point I/O relay Number of Modules Calculated on a 16-device Basis 1 1 1 1 2 4
IM 34M6P13-01E
7-3
G System of Peripheral Processes
The latest, maximum and minimum of scan times taken by the system of peripheral processes are stored in special registers Z007 to Z009 in that order.
Table 7.2 Scan Time of System of Peripheral Processes
Item Processing Task Processing Time
Updates the contents of shared/extended shared relays (E) and shared/extended shared registers (R) when an add-on CPU module is installed and shared refreshing is set as a peripheral process. In a single refreshing cycle, this task Shared updates the contents of refreshing shared/extended shared relays (E) or shared/extended shared registers (R) included in the configuration setting, for each CPU. Not performed if no add-on CPU module is installed or shared refreshing is set as a peripheral process. Updates the contents of link relays and registers when an FA link FA link module is installed. Link refreshing Not performed if no FA link module is installed. Processes commands input from the WideField2 connected Tool service to the sequence CPU module. Executes one command per service. Processes commands input from a personal computer link Link service module. Executes one command per service. Processes commands input from a remote CPU module. CPU service Executes one command per service.
When an add-on CPU module is installed and shared refreshing is set as a peripheral process: 0.003x (number of relays set in CPU for refreshing/32+number of registers set in CPU for refreshing/2)+0.10 ms, if the CPU modules for which the devices are refreshed is F3SP28, F3SP38, F3SP53, F3SP58 or F3SP59. 0.014x (number of relays set in CPU for refreshing/32+number of registers set in CPU for refreshing/2)+0.10 ms, if the CPU modules for which the devices are refreshed is other than F3SP28, F3SP38, F3SP53, F3SP58 and F3SP59..
0.00ms When an FA link module is installed: 0.015x (number of relays used in FA link for refreshing/16+number of registers used in FA link for refreshing)+0.06 ms 0.00ms
IM 34M6P13-01E
7-4
7.2
IM 34M6P13-01E
7-5
7.3
F 3 P U 2 0
F 3 S P 2 8
32-point input modules 32-point output modules F070301.VSD
Figure 7.1 Module Configuration of F3SP28 or F3SP38 Sequence CPU Table 7.3 Scan Time of F3SP28 or F3SP38 Sequence CPU
Item Common processing Program execution Calculation Fixed 0.2ms Processing Time 0.2ms 0.5ms 0.1ms* 0.00ms 0.05ms 0.06ms 0.2ms* 0.8ms
0.09s5120 = 461s Number of modules calculated on a Output refreshing 16-points basis: 24 = 8 12s8 = 96s When no add-on CPU module is Shared refreshing installed: 0.00 ms Number of modules calculated on a Input refreshing 16-points basis: 24 = 8 8s8 = 64s Number of modules calculated on a Synchronization 16-points basis: 24 = 8 Processing 8s8 = 64s Minimum peripheral processing Peripheral processing time, if not yet defined: 0.2 ms Scan time, which is the sum of all time spans listed above
* The output refreshing time and the minimum peripheral processing time are excluded from scan time calculation because the sum of these time spans is smaller than the program execution time.
IM 34M6P13-01E
7-6
G When the CPU Is F3SP53, F3SP58 or F3SP59
Module configuration User program : Four 32-point input modules : Four 32-point output modules : 20K steps consisting of LD and OUT instructions only, where the average execution time of these instructions is assumed to be 0.035 s
F 3 P U 2 0
F 3 S P 5 8
32-point input modules 32-point output modules F070302.VSD
Figure 7.2 Module Configuration of F3SP53, F3SP58 or F3SP59 Sequence CPUs Table 7.4 Scan Time of F3SP53, F3SP58 or F3SP59 Sequence CPU
Item Common processing Program execution Calculation Fixed at 0.2ms. Processing Time 0.2ms 0.5ms 0.1ms* 0.00ms 0.05ms 0.06ms 0.2ms* 1.0ms
0.035s20480 = 717s Number of modules calculated on a Output refreshing 16-points basis: 24 = 8 12s8 = 96s When no add-on CPU module is Shared refreshing installed: 0.00ms Number of modules calculated on a Input refreshing 16-points basis: 24 = 8 6s8 = 48s Number of modules calculated on a Synchronization 16-points basis: 24 = 8 processing 8s8 = 64s Minimum peripheral processing Peripheral processing time, if not yet defined: 0.2ms Scan time, which is the sum of all time spans listed above
* The output refreshing time and the minimum peripheral processing time are excluded from scan time calculation because the sum of these time spans is smaller than the program execution time.
IM 34M6P13-01E
7-7
7.4
Scan time: 2 ms Minimum I/O response time = Input response time + Scan time + Output response time = 16 ms + 2 ms + 1 ms = 19 ms
X00502 Y00602
Output
Y00602
F070401.VSD
Output
F070402.VSD
IM 34M6P13-01E
7-8
TIP
The I/O response time refers to the total time taken to execute instructions from the external input device and the time taken to turn on the eternal output equipment.
TIP
Input response time refers to the time taken to load external input tag name using the input refreshing process.
TIP
Output response time refers to the time taken to reflect the result of instruction execution in the external output device using the output refreshing process.
IM 34M6P13-01E
7-9
7.5
The instruction execution time varies slightly depending on the contents of the input parameter or output parameter devices or the number of devices included in data transfer. The execution time lengths listed in the Table of Instruction Words are typical. Use these values of the instruction execution time just for reference purposes only when calculating the scan time. The instruction execution time decreases or increases in length, as shown in Table 7.5 below, depending on the conditions under which an instruction is executed. Use values of T in the Table of Instruction Words to figure out guidelines of the scan time according to the formulas given in Table 7.5.
Table 7.5 Calculation of Instruction Execution Time
Instruction Execution Time (s) F3SP53 F3SP28 F3SP58 F3SP38 F3SP59 T+0.18 T+0.07 T+2.5N1 T+3.5N1 T+3.5N2 T+4.5N2 T+1.0N3 T+2.0N4 T+1.0N1 T+1.4N1 T+1.4N2 T+1.8N2 T+0.4N3 T+0.8N4
Execution Conditions
Differential type instruction Relay (BIN format) X and Y I/O relays defined in BCD format Index modification
T N1 N2 N3
When executed When not executed 16 bits 32 bits 16 bits 32 bits Basic instruction Advance instruction
: Instruction execution time in Table of Instruction Words. : Number of relay devices : Number of relay devices defined in BCD format : Number of index-modified relay devices
IM 34M6P13-01E
7-10
I Examples of Calculation
The following paragraphs give examples of calculating the instruction execution time. For information on the execution time of an MOV instruction, see Table of Instruction Words in Appendix of the 3rd or later editions of the Sequence CPU Instruction Manual Instructions (IM34M6P12-03E). (1) Differential Type Instructions
MOV
D0001
D0002
0.18+0.18=0.36 s (for F3SP28 and F3SP38 sequence CPUs) 0.07+0.07=0.146 ms (for F3SP53, F3SP58 and F3SP59 sequence CPUs)
F070501.VSD
(2) Relays (BIN Format) Use any execution time from the Table of Instruction Words in parentheses ( ).
MOV
I0002
D0001
3.2+2.5=5.7 s (for F3SP28 and F3SP38 sequence CPUs) 1.2+1.0=2.2 s (for F3SP53, F3SP58 and F3SP59 sequence CPUs)
F070502.VSD
(3) X and Y I/O Relays Defined in BCD Format Use any execution time from the Table of Instruction Words in parentheses ( ).
Number of relay device defined in BCD format: N2 = 1 3.2+3.5=6.7s (F3SP28 and F3SP38 sequence CPUs) 1.2+1.4=2.6s (F3SP53, F3SP58 and F3SP59 sequence CPUs)
MOV D0001 Y00301
F070503.VSD
0.09+1.0=1.09ms (F3SP28 and F3SP38 sequence CPUs) 0.035+0.4=0.435ms (F3SP53, F3SP58 and F3SP59 sequence CPUs)
F070504.VSD
2.
Application Instructions Use any execution time from the Table of Instruction Words in parentheses ( ).
V01 MOV D0001 V02 D0002
3.2+2.0 X 2=7.2s (F3SP28, F3SP38 sequence CPUs) 1.2+0.8 X 2=2.8s (F3SP53, F3SP58 and F3SP59 sequence CPUs)
F070505.VSD
IM 34M6P13-01E
8-1
8.
8.1
RAS Features
This chapter describes the RAS features of the sequence CPU module, such as the self-diagnosis and error logging functions that work if the module fails.
Self-diagnosis
The sequence CPU performs self-diagnosis on its device memory, instruction codes, and so on when the power is turned on or a program is being executed. The results of self-diagnosis are reflected in predetermined special relays (M) and registers (Z). If any failure is found during self-diagnosis, the CPU module updates the mode statuses of LED indicators and stops executing programs depending on the failure mode.
Table 8.1 Shows how the severity of failure is classified by type and mode.
Action of Output Module Output *2 F3YD64-1F modules and with 64 F3WD64- F Between Between output output FAIL1 points, FAIL2 modules and COM and COM except with 32 or F3YD64-1F less output and points F3WD64- F Default: Nullified RESET setpoint Shorted Open Can be set in The status is 16 points always increments. HOLD. FAIL Signal Contact Output
Severity of Failure
Failure Condition
Failure Mode
Major failure
Minor failure
- Program error - I/O collation failure*1 - I/O module failure*1 Memory failure - PU failure Instruction error*1 - Scan time-out*1 Startup failure The user - Detection of invalid program cannot Instruction be started or - Excess number of I/O run any further. points - ROM pack failure - Subroutine error*1 - Interrupt error*1 - Failure in subunit transmission line*1 - Sensor control scan time-out error*1 - Momentary power failure The program is - CPU-to-CPU abnormal, communication failure though it can - Switchover in subunit still be run. transmission line
Shorted
Open
Open
Shorted
Continued operation
Continued operation
* 1: Either the minor or moderate failure can be selected as the failure level for this item using the configuration function * 2: Include the F3WD64 module and advanced modules that contain output relays.
For some of the failure modes, you can select the Stop or Run option to determine whether to stop or continue program execution if any of these failures occur. This selection can be made using the configuration function. This configuration item defaults to the Stop option for a moderate failure and to the Continue option for a minor failure. Moderate failure modes set to the Continue option are treated as minor failure modes, while minor failure modes set to the Stop option are treated as moderate failure modes.
IM 34M6P13-01E
8-2
SEE ALSO
The fail signal contact indicates the error state to the external environment when an error occurs.
CAUTION
If you want the contacts of an output module to be held in case of a major or moderate failure in the sequence CPU module, set the Output to be latched in case of CPU stop option of the configuration function to HOLD. Note that there is no difference in the module action due to a difference in the type of output module.
IM 34M6P13-01E
8-3
Table 8.2 Details on Self-diagnosis (1 of 6)
Stored Error Code Special Special Registers Relay that Store that Error Turns ON Codes, Etc. Nonfatal Startup error M193 Z017 to Z019
Failure Mode
Failure Description
Corrective Actions
Severe
The CPU Hardware malfunctions due to failure noise or for other reasons. Hardware failure A failure has occurred during CPU initialization.
SPU error
$11nn
The CPU for sequence computing has failed. A program checksum error has occurred. Transient memory failure or hardware failure (See CAUTION at the end of tables for information on how to discriminate between these failures). Application
Memory error
$1201
1. Check the installation environment for possible problems, such as noise sources. If the failure recurs, replace the module. 1. It is likely that restrictions on module installation have been violated. Check the modules according to Section 1.2, "Restrictions on Installing Modules," in the instruction manual. Sequence CPUs-Hardware. 2. Check the installation environment for possible problems, such as noise sources. If the failure recurs, replace the module. 1. Check the installation environment for possible problems, such as noise sources. If the failure recurs, replace the module. 1. It is likely that the error is due to a transient memory failure caused by effects of noise. Check the installation environment. Clear the memory by referring to CAUTION at the end of tables and download the program once again. If the failure recurs, replace the module. (Note) 1.Check if there is any error in the values of index registers or in the parameters defining the number of devices in an instruction for globally rewriting multiple devices, such as a BMOV block transfer instruction. 1. It is likely that the error is due to a transient memory failure caused by effects of noise. Check the installation environment. Clear the memory by referring to CAUTION at the end of tables and download the program once again. If the failure recurs, replace the module. 1. Verify compatibility among the JMP, SUB and RET instructions. 2. It is likely that the error is due to a transient memory failure caused by effects of noise. Check the installation environment. Clear the memory by referring to CAUTION at the end of tables and download the program once again. If the failure recurs, replace the module.
$1202
Inadvertent writing has been done to the M129 to M131 special relays for handling Run, Debug and Stop mode flags. A device memory read/write check error has occurred. A system memory read/write check error has occurred. An invalid instruction has been encountered. There is no END instruction in the program. The JMP, SUB and RET instructions are not compatible with one another
Hardware failure
Hardware failure
Note: You may recover from this error by turning the power off and then on again.
IM 34M6P13-01E
8-4
Table 8.2 Details on Self-diagnosis (2 of 6)
Special Relay that Turns ON M193 Special Registers Stored that Store Error Failure Description Code Error Codes, Etc. $2002 The number of I/O Z017 to points has been Z019 exceeded.
Failure Mode
Corrective Actions
Nonfatal
$8203
$8204
It is not possible to Hardware read from or write to failure the ROM pack.
Battery error
M194
$1801
The backup batteries have failed. Application The subroutine error return (RET) instruction was not executed or there is no return destination. The maximum nesting depth of eight levels has been exceeded. The interrupt return (IRET) instruction was not executed or there is no return destination. There are more than eight interrupts waiting for execution.
Z022 to Z024
$2201
1. It is likely that restrictions on module installation have been violated. Check the modules according to Section 1.2, "Restrictions on Installing Modules," in the instruction manual Sequence CPUs-Hardware. 1. A ROM pack whose data has been erased is in no way defective. Use it as is. 2. It is likely that data has been written to the ROM pack under a wrong sequence CPU module name. Rewrite to the ROM pack and try using it again. The ROM pack or sequence CPU module may be defective if the same failure recurs. Replace the ROM pack or the sequence CPU module. 1. Rewrite to the ROM pack and try using it again. The ROM pack or CPU module may be defective if the same failure recurs. Replace the ROM pack or CPU module. 1. The power supply module may be defective if the same failure recurs. Replace the module. 1. Check if there is a jump out of or into the subroutine. 2. Check if a scan timeout has been detected within the subroutine. 1.Check the depth of nesting when calling another subroutine in a given subroutine. 1. Check if there is a jump out of or into the input module interrupt program. 2. Check if a scan timeout was detected within the input module interrupt program. 1. There are more than eight interrupts waiting for execution. Check the detailed process of each interrupt, the number of interrupts, their frequency, etc. When the power is turned on and before the program is executed, check if there is a possibility that more than eight interrupts will occur.
$2202
Moderate failure
$2301
$2302
Note: For this failure mode, you can determine whether to stop or continue program execution.
IM 34M6P13-01E
8-5
Table 8.2 Details on Self-diagnosis (3 of 6)
Special Special Registers Stored Relay that Store Error that Error Code Turns ON Codes, Etc. M201 Z022 to $2101 Z024 $2102
Failure Mode
Failure Description
Corrective Actions
Non-fatal
$2103
$2104
$2105
$2106
1. Check if any abnormal value is set in the instruction parameter in question. 1. Check if any abnormal value, such as one based on division by 0, is set in the instruction parameter. 1. It is likely that an impossible value has been set in BINto-BCD or BCD-to-BIN conversion. Check the parameter where the error has occurred. 1. Check if more data values have been written to the FIFO table than can be accepted by the table. 2. Check if an attempt has been made to read data values from the FIFO table when there is none. 3. Check if the default settings of the FIFO table are correct. Also check if the table has been destroyed in any other part of the program. 1. Check if there is any error in the values of index registers or in the parameters defining the number of devices in an instruction for globally rewriting multiple devices, such as a BMOV block transfer instruction. 1. Check if there is such an error as a jump out of the FOR-NEXT loop or a jump into the loop from outside it. 2. Check if a scan timeout has been detected within the FOR-NEXT loop.
Note: For this failure mode, you can determine whether to stop or continue program execution.
IM 34M6P13-01E
8-6
Table 8.2 Details on Self-diagnosis (4 of 6)
Special Relay that Turns ON M202 Special Registers Stored that Store Error Error Code Codes, Etc. Z027 to $2401 Z029
Failure Mode
Failure Description
Corrective Actions
Nonfatal error
M203
Z033 to Z040
- The condition of Application 1. It is likely that there is a module installation is failure mismatch between the X not consistent with and Y I/O relay devices the program. specified in the program and those contained in the - The number of installed I/O module. Special Module Check if the instruction High-Speed Read parameter in question is (HRD) instructions or consistent with the Special Module installed I/O module. High-Speed-Write 2. Check if the number of (HWR) instructions exceeded the limit Special Module High(error code: $2401). Speed-Read (HRD) instructions or the number of Special Module HighSpeed-Write (HWR) instructions exceeded 64. $2402 $2402 1. It is likely that there is a mismatch between the slot (READ/W (READ/WRITE) number in READ/WRITE RITE) instructions used in the program and that of the installed I/O module. Check if the instruction parameter in question is consistent with the installed I/O module. $2403 $2403 1. It is likely that there is a mismatch between the slot (READ/W Special module highnumber in a Special RITE) speed-read Module High Speed Read instruction (HRD (HDR) Instruction or a Instruction)/ special Special Module High module-high-SpeedSpeed Write (HWR) write instruction Instruction used in the (HWR Instruction) program and that of the installed I/O module. Check if the instruction parameter in question is consistent with the installed I/O module. -It is not possible to 1. Check if the subunit is read from or write turned off. to the I/O module. 2. Check if there is any -There is a problem with the cable of communication the fiber-optic FA-bus failure in the fibermodule. optic FA-bus 3. Do not reset the CPU module. modules individually. -An attempt has Rather, reset them all at been made to reset once from the main CPU. a remote sequence 4. The I/O module may be CPU module in a defective. multi-CPU system. Replace it.
Note: For this failure mode, you can determine whether to stop or continue program execution.
IM 34M6P13-01E
8-7
Table 8.2 Details on Self-diagnosis (5 of 6)
Special Special Registers Relay that Store that Error Turns ON Codes, Etc. M204 Stored Error Code
Failure Mode
Failure Description
Corrective Actions
Nonfatal error
M210
Z089 to Z096
M195
1. Check if the repetitioncounter values of the FORNEXT loop are correct. 2. Check if the FOR-NEXT loop has been mistakenly turned into an endless loop by JMP instructions. 3. Adjust the scan time monitoring time according to the execution time of the application program. It is not possible to Open1. Check if the subunit is read from or write to circuited turned off. the subunit. cable Loss of 2. Check if there is any power to problem with the cable of subunit the fiber-optic FA-bus Hardware module. failure 3. The fiber-optic FA-bus module may be defective. Replace it. The CPU fails to Application 1. For interruption by the sustain the failure sensor control block after execution interval completion of instruction because it is execution, set the exceeded by the execution interval at 1 ms or sum of the I/O longer, preferably at the refreshing time of largest possible value. the sensor control 2. Check the number of words and the execution in the sensor control block time of the block. and the block's execution time to reduce both of them as much as possible. 3. Check the CBD-CBE instruction section where executing the sensor control block is prohibited to shorten the section as much as possible. The CPU indicates 1. If this failure mode occurs that a momentary too frequently, check the power failure has power supply for possible occurred. problems. If a UPS is in use, check that it has captured peak values of its supply voltage waveform. If the failure still occurs frequently while there is no problem with the waveform, it is likely that the power supply module and/or sequence CPU module is defective. Replace it.
The scan time Application monitoring time has failure been exceeded.
Note: For this failure mode, you can determine whether to stop or continue program execution.
IM 34M6P13-01E
8-8
Table 8.2 Details on Self-diagnosis (6 of 6)
Special Special Registers Relay that Store that Error Turns ON Codes, Etc. M196 Stored Error Code
Failure Mode
Failure Description
Corrective Actions
Nonfatal error
M211
Z89 to Z96
There is a problem Openwith the twisted-pair circuited cables attached to cable remote I/O modules in a loop configuration.
1. It is likely that there is a failure in remote CPUs in a multi-CPU system. Do not reset the CPU modules individually. Rather, reset them all at once from the main CPU. If this failure mode recurs, replace the CPU modules. 1.Check if there is any problem with the cable of the fiber-optic FA-bus module 2.The fiber-optic FA-bus module may be defective. Replace it
CAUTION
You can clear the CPU memory and revert it back to the factory settings by installing the sequence CPU module in the 5th or later slot of the main unit and turning it on. If the failure is a transient memory failure due to effects of noise, download an application program once again so that you can reuse the memory. If the failure recurs, there may be a hardware failure. Replace the sequence CPU module.
SEE ALSO
Fiber-optic FA-bus Module and Fiber-optic FA-bus Type 2 Module (IM34M6H45-01E), for more information on the failure modes failure in subunit transmission line and switchover in subunit transmission line.
IM 34M6P13-01E
8-9
8.1.1
Setting Operation Mode in Case of Failure and External Output Mode in Case of Sequence Stop
See Also
Fiber-optic FA-bus Module and Fiber-optic FA-bus Type 2 Module (IM34M6H45-01E), for more information on the failure mode failure in subunit transmission line.
IM 34M6P13-01E
8-10
8.2
IM 34M6P13-01E
9-1
9.
9.1
Number of I/O points Number of internal relays (I) Number of link relays (L) Number of timers (T) Number of file registers (B) Number of link registers (W) Program size Number of program blocks Number of program macros Number of basis instructions Number of advanced instructions Other functions
8192 30K steps max 20K steps 100K steps (F3SP28) max. max. 56K steps max. (F3SP53) 128 max. 1024 max. 1024 max. 1024 max. 25 307 64 max. 33 312 256 max.
Specification Item Instruction execution time Basic instruction Advanced instruction F3SP25 0.12 to 0.24s/ instruction From 0.24s/ instruction F3SP35 0.0 9 to0.18s/ instruction From 0.18s/ instruction F3SP28 F3SP53 0.0 45 to 0.18s /instruction From 0.18 s / instruction F3SP38 F3SP58 F3SP59 0.0175 to 0.07s/ instruction From 0.07s /instruction
IM 34M6P13-01E
9-2
TIP
- To gain access to file register (B) using a personal computer link command, refer to the conventions given below.
Module Personal computer link (F3LC11-1N, F3LC11-2N) Personal computer link (F3LC11-1F, F3LC12-1F) Ethernet interface CPU (personal computer link function) Restriction Yes Convention Accessible file registers are B1 to B99999.
No
The device name of file registers (B) must be seven bytes long.
- To gain access to the sensor control block using personal computer link module, refer to the conventions given below.
Module Personal computer link Ethernet interface CPU (personal computer function) No A sensor control block number is determined by adding 1 to the end of a number assigned to regular blocks. Restriction Convention
IM 34M6P13-01E
9-3
9.2
Configuration
Specification Item F3SP28 F3SP38 F3SP53 F3SP58 F3SP59 No configuration is required for these types of relays. No configuration is required for these types of registers. 16 max F3SP28 and F3SP53: 2048 max. (for all timers combined) F3SP38, F3SP58, F3SP59: 3072 max. (for all timers combined) . Yes F3SP25 8912 units for both types of relays combined F3SP35 16384 units for both types of relays combined
Internal relay (I) Shared Relay (E) Data register (D) Device size Shared register(R) 100-s timer 1-ms timer Operation mode in case of failure Sensor control scan timeout Use /Do not Use
Configurable on 16 points basis, including Use/Do not Use/Use as Sensor CB (Note) . I/O module setting 16ms/1ms/250s/62.5s/ 16ms/1ms; configurable on a module Input sampling interval constant; configurable on 16 basis. points basis. Output mode in case Configurable on a module basis. Configurable on 16 points. of sequence stop Configurable from 200s to Execution interval No 25.0ms in 100s increment. Sensor control After completion of instruction block Interrupt timing No execution/Immediate, during instruction execution. Input module After completion of instruction No (always after completion of interrupt Interrupt timing execution/Immediate, during instruction execution) ) instruction execution processing Sensor control block has Priorities of sensor control block and input No priority module interrupt processes / input interrupt has priority Peripheral processing (minimum operating) Configurable from 100s to No time 190ms in 100s increments. Run/Stop; configurable for shared relays (E) , shared Range of shared registers (R) , extended refreshing (partial No shared relays (E) , and stop) extended shared registers (R) Shared refreshing of each CPU module. (inter-CPU-module communications Simultaneity of shared No Yes/No method) refreshing data Mode of shared refreshing (definition Peripheral process/ No (No simultaneity in all cases) Control-related process as control-related process)
Note: Denotes CB (Sensor control block)
CAUTION
For F3SP28, F3SP38, F3SP53, F3SP58 and F3SP59, you can determine by configuration (Yes/No options) whether there is simultaneity with the data of shared devices. The No option of this configuration item is designed for the interchangeability of the F3SP21, F3SP25 and F3SP35 modules. Select this option when replacing these modules with the F3SP28, F3SP38, F3SP53, F3SP58 or F3SP59 modules.
IM 34M6P13-01E
9-4
CAUTION
If your sequence CPU is F3SP28, F3SP38, F3SP53, F3SP58, or F3SP59, set the CPUs output relays (Y) to be refreshed to the option Unused, by a direct Refresh (DREF) instruction in a program. If you set them to the option Used or Used in CB (sensor control block) , the values one scan earlier may be overwritten with the values output by the DREF instruction because of the timing of output refreshing that is executed concurrently with the instruction.
IM 34M6P13-01E
9-5
9.3
0.5ms 1ms
0.5ms 1ms
Utility Function ON: Enabled OFF: Disabled Utility Name CB scan timeout Function ON: Abnormal OFF: Normal Description The CPU fails to sustain the execution interval of the sensor control block Description Indicates the status of a sensor control block
Item No M212
IM 34M6P13-01E
9-6
The following special registers (Z) have been added to the list of utility registers.
Item No. Z109 Z111 Name CB execution time Maximum CB execution time Utility Description Refers to the length of time from when input refreshing is started for the sensor control block to when the program is executed and output refreshing is completed. (Unit: 10s) Refers to the maximum time taken to execute the sensor control block.(Unit:10s)
IM 34M6P13-01E
9-7
9.4
Availability of Simultaneity of Data among CPU Modules F3SP25 F3SP35 F3SP28 F3SP38 F3SP53 F3SP58 F3SP59
C P U A
There is no simultaneity of data in CPU module to CPU module communication between shared relays (E) /registers and extended shared relays (E) /registers.
9.5
IM 34M6P13-01E
9-8
9.6
Instructions
The following instructions have been added to the list of instructions available with the F3SP28, F3SP38, F3SP53, F3SP58 and F3SP59 sequence CPU modules.
Instruction Name LDU LDD UP DWN UPX DWNX INV FF CBACT CBINA CBD CBE FTIMR Description Rising-edge differential load Rising-edge differential load Rising-edge differential computation Rising-edge differential computation Rising-edge differential computation with device specification Rising-edge differential computation with device specification Inverter Flip-flop Enablement of sensor control block Disablement of sensor control block Prohibition of sensor control block execution Cancellation of prohibition of sensor control block execution Reading of free-running timers
IM 34M6P13-01E
10-1
- S and
This chapter describes the difference in function and specifications between the F3SP28/38/53/58/59- N/ H (old models) and the F3SP28/38/53/58-S (new models) CPU modules.
SEE ALSO
For details on the partial download function, see Section 6.16, "Partial Download Function."
SEE ALSO
- For details on the download comments function, see Section 6.17, "Function for Storing Comments to CPU." - For details on the download tag name definitions function, see Section 6.18, "Function for Storing Tag Name Definitions to CPU." - For details on the ROM pack function, see Section 6.8.3, "ROM Writer Functions and ROM Writer Mode."
IM 34M6P13-01E
10-2
SEE ALSO
For details on structures, see "FA-M3 Programming Tool WideField2 Instruction Manual" (IM 34M6Q15-01E).
Indirect designation With the new models, indirect designation is available to address devices. Thus some instructions are added to handle this new function. Using indirect designation allows you to address all file registers (B), including those which cannot be accessed using index modification. You can also use indirect designation to address devices other than the file registers (B).
SEE ALSO
For details on indirect designation, see Section 1.8.2, "Indirect Designation," of "Sequence CPU Instruction Manual - Instructions" (IM 34M6P12-03E, 3rd Edition or later).
Index modification by constant With the new models, index modification by constant is available.
SEE ALSO
For details on index modification by constant, see Section 1.8.1, "Index Modification," of "Sequence CPU Instruction Manual - Instructions" (IM 34M6P12-03E, 3rd Edition or later).
Nesting of interlock areas (program steps between IL and ILC) Interlock areas may be nested up to 8 levels.
SEE ALSO
For details on interlock, see Section 2.18, "Interlock, Interlock Clear," of "Sequence CPU Instruction Manual - Instructions" (IM 34M6P12-03E, 3rd Edition or later).
IM 34M6P13-01E
10-3
New instructions The following instructions are added in the new models.
SEE ALSO
For details on these new instructions, see "Sequence CPU Instruction Manual - Instructions" (IM 34M6P12-03E, 3rd Edition or later).
Number of steps per block Number of macro instructions Number of circuits/subcomments Number of timer steps Compatible ROM pack
IM 34M6P13-01E
Blank Page
App.1
FA-M3
Sequence CPU Instruction Manual - Function
(For F3SP28-3N/3S, F3SP38-6N/6S, F3SP53-4H/4S, F3SP58-6H/6S, F3SP59-7S)
IM 34M6P13-01E 2nd Edition
These appendices provide lists of special devices, as well as formats of documentation which can be used when designing your system. These formatted sheets can be conveniently copied for use as standard forms in your system design. Four forms are provided, as shown below.
Contents
Appendix 1 Special Relays (M) ............................................................... App.1-1 Appendix 2 Special Registers (Z) .......................................................... App. 2-1 Appendix 3 Forms for system Design................................................... App. 3-1
Program Coding Sheet ............................................................ App 3-1 Relay Devices Assignment Table ............................................ App 3-2 Register Devices Assignment Table ........................................ App 3-3 Timer/Counter Setpoints Table ................................................ App 3-4
IM 34M6P13-01E
Blank Page
App.1-1
Block Start Status Module M0001 to M0032 M0001 to M0032 M2001 to M3024 Relay Block n start status relay Number ON: Run OFF: Stop Name Indicate whether block n is in progress or at a stop when blocks are selected and executed.
The start status relays assigned to blocks 1 to 32 are M0001 to M0032 and M2001 to M2032, where the values of M0001 to M0032 are the same as those of M2001 to M2032. Similarly, start status relays M2033 to M3024 are assigned to blocks 33 to 1024.
CAUTION
Do not write to a special relay, including those not listed in the table above (e.g., M067 to M96), unless otherwise stated. This is because they are used by the sequence CPU module for the system side. If you inadvertently write to these relays, a failure, such as a system shutdown, may result. (It is also prohibited to use a forced set/reset instruction in debug mode.)
CAUTION
You are not allowed to apply index modification to a special relay in an attempt to specify them as the destination of data output. If you do so, an instruction processing error will result.
CAUTION
In a ladder instruction for continuous data transfer or table-format data output (see examples below), you are not allowed to specify a special relay as the output destination. If you do so, an instruction processing error will result. - Instructions for continuous data transfer: BMOV, BSET, SMOV, etc. - Instructions for table-format data output: ULOGR, FIFWR, etc.
IM 34M6P13-01E
App.1-2
Utility Relays
Function Description Used for an initialization process or as a dummy contact in a program.
Utility Relays
ON OFF ON OFF
1 Scan
Turns on for one scan only after the start of a program Generates a clock pulse with a 0.010.005s 0.005s sec period. Generates a clock pulse with a 0.020.01s 0.01s sec period. Generates a clock pulse with a 0.1-sec 0.05s 0.05s period. Generates a clock pulse with a 0.2-sec 0.1s 0.1s period. Generates a clock pulse with a 1-sec 0.5s 0.5s period. Generates a clock pulse with a 2-sec 1s 1s period. Generates a clock pulse with a 1-min 30s 30s period. Generates a clock pulse with a 1-msec 0.5ms 0.5ms period. Generates a clock pulse with a 2-msec 1ms 1ms period. ON: Normal transmission line or no fiber-optic FA-bus installed OFF: Unspecified or abnormal transmission line ON: When the block Turns on for one scan when the sensor starts. control block starts (at the first OFF: In all other execution of the sensor control block). cases.
*: Blocks M036 to M048 have their rising and falling clock timing synchronized.
SEE ALSO
For details on the M066 Utility relay (Normal Subunit Transmission Line), see "Fiber-optic FA-bus Module and Fiber-optic FA-bus Type 2 Module" (IM34M6H45-01E).
IM 34M6P13-01E
App.1-3
SEE ALSO
Specifications of special registers (Z) for clock data, for more information on time setting.
IM 34M6P13-01E
App.1-4
M211
ON: Abnormal. OFF: Normal. ON: Abnormal transmission Subunit transmission line. line failure OFF: Unspecified or normal transmission line. ON: Abnormal transmission Switchover in line. subunit transmission OFF: Unspecified or normal line transmission line. ON: Abnormal. OFF: Normal. ON: Executes the program. OFF: Stops the program. ON: Executes the program. OFF: Stops the program. ON: Executes the program. OFF: Stops the program. ON: Executes the program. OFF: Stops the program.
CB scan timeout CPU-1 sequence program execution CPU-2 sequence program execution CPU-3 sequence program execution CPU-4 sequence program execution
SEE ALSO
Fiber-optic FA-bus Module and Fiber-optic FA-bus Type 2 Module (IM34M6H45-01E), for more information on the M210 (Subunit Transmission Line Failure) and M211 (Switchover in Subunit Transmission Line) self-diagnosis relays.
IM 34M6P13-01E
App.1-5
SEE ALSO
Special relays/registers sections of instruction manual (IM34M5H43-01E), FA Link H Module, Fiberoptic FA Link H Module, for more information on these FA link module status relays.
FA link error
IM 34M6P13-01E
Blank Page
App.2-1
Scan time (Run mode) Latest scan time Minimum scan time (Run mode) Maximum scan time (Run mode) Scan time (Debug mode) Minimum scan time (Debug mode) Maximum scan time (Debug mode) Peripheral-process scan time Minimum peripheralprocess scan time Maximum peripheralprocess scan time Minimum scan time Maximum scan time. Latest scan time Minimum scan time Maximum scan time. Latest scan time
Z008
Z009
CAUTION
Do not write to a special register (Z), including those not listed in the table above (e.g., Z010 to Z016), unless otherwise stated. This is because they are used by the sequence CPU module for the system. If you inadvertently write to these registers, a failure, such as a system shutdown, may result. You are not allowed to apply index modification to special registers (Z) in an attempt to specify them as the destination of data output. If you do so, an instruction processing error will result. In a ladder instruction for continuous data transfer or table-format data output (see examples below), you are not allowed to specify a special register (Z) as the output destination. If you do so, an instruction processing error will result. Instructions for continuous data transfer: Block Move instruction (BMOV instruction), Block Set instruction (BSET instruction), String Move instruction (SMOV instruction), etc. Instructions for table-format data output: User Log Read instruction (ULOGR instruction), FIFO Write instruction (FIFWR instruction), etc.
IM 34M6P13-01E
App.2-2
Z033 to 040
I/O error
I/O error 16 0
2 1
1 0
Z041 Z042 Z043 Z044 Z045 Z046 Z047 Z048 Z089 Z090 Z091 Z092 Z093 Z094 Z095 Z096 Abnormal slot in subunit transmission line Module recognition
Main unit Subunit 1 Subunit 2 Subunit 3 Subunit 4 Subunit 5 Subunit 6 Subunit 7 Main unit Subunit 1 Subunit 2 Subunit 3 Subunit 4 Subunit 5 Subunit 6 Subunit 7
Slot number 16 0 1 1 0
1 0
Fiber-optic FA-bus module 0: Normal transmission line; Unspecified transmission line; or Loaded with a wrong module 1: Abnormal transmission line (Failure or changeover in transmission line)
* For information on error numbers (codes) to be saved in these special registers, see Table 8.2, "Details of Self-diagnosis."
SEE ALSO
Fiber-optic FA-bus Module and Fiber-optic FA-bus Type 2 Module (IM34M6H45-01E), for more information on the Z089 to Z096 special registers (Abnormal Slot in Subunit Transmission Line).
IM 34M6P13-01E
App.2-3
Note: Available with the F3SP28, F3SP38, F3SP58 and F3SP59 only.
App.2-4
SEE ALSO
Special relays/registers sections in, FA Link H Module F3LP02-0N Fiber-optic FA Link H Module F3LP12-0N (IM34M5H43-01E), for more information on the FA link module status registers.
Z257 (Note) Local station status Z258 (Note) Cyclic transmission time
Z262 (Note) Local station status Z263 (Note) Cyclic transmission time
Z267 (Note) Local station status Z268 (Note) Cyclic transmission time
Z272 (Note) Local station status Z273 (Note) Cyclic transmission time
Z277 (Note) Local station status Z278 (Note) Cyclic transmission time
Z282 (Note) Local station status Z283 (Note) Cyclic transmission time
Note: Available with the F3SP25, F3SP28, F3SP35, F3SP38, F3SP53, F3SP58 and F3SP59 only.
TIP
Units that make up a system are known as stations.
IM 34M6P13-01E
App.2-5
Z109 (Note 1)
CB execution time
Z111 (Note 1)
Note 1: Only for F3SP28, F3SP38, F3SP53, F3SP58, and F3SP59 Note 2: F3SP28, F3SP38, F3SP53, F3SP58 and F3SP59 For example, module F3SP58-6S with firmware Rev1, Z121 F3 Z122 SP Z123 58 Z124 6S Z125 /R Z126 01 Z127 / Z128 F3SP05, F3SP08, F3SP21, F3SP25, F3SP35 For example, module F3SP21-0N with firmware Rev 14 Z121 F3 Z122 SP Z123 21 Z124 -0 Z125 *A Z126 14 Z127 Z128
IM 34M6P13-01E
Blank Page
App.3-1
Operand
Remarks
IM 34M6P13-01E
App.3-2
I Relay Devices Assignment Table
System Name Model Drawing No.
Approved Checked Prepared Sheet No. by by by
Device No. 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2
Signal Name
Description
Device No. 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4
Signal Name
Description
IM 34M6P13-01E
App.3-3
I Register Devices Assignment Table
System Name Model Drawing No.
Approved Checked Prepared Sheet No. by by by
Device No. 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
Signal Name
Description
Device No. 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
Signal Name
Description
IM 34M6P13-01E
App.3-4
I Timer/Counter Setpoints Table
System Name Model Drawing No.
Approved Checked Prepared Sheet No. by by by
Device No 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2
Setpoint
Signal Name
Description
IM 34M6P13-01E
Index-1
FA-M3
Sequence CPU Instruction Manual - Function
(For F3SP28-3N/3S, F3SP38-6N/6S, F3SP53-4H/4S, F3SP58-6H/6S, F3SP59-7S)
IM 34M6P13-01E 2nd Edition
Index
Number
100ms Continuous Timer ................................... 4-27 100ms Timer ...................................................... 4-25 100ms Timer ...................................................... 4-25 10ms Timer ........................................................ 4-25 1ms Timer .......................................................... 4-25
F
FA Link Module Status.........................4-24, App. 1-5 FA Link System .................................................... 2-5 File Registers (B) ............................................... 4-45 Forced Reset...................................................... 6-13 Forced Set.......................................................... 6-13
A
ACTIVE State ....................................................... 6-7 Allocation of I/O Addresses .................................. 4-2
H
High-speed Processing of Application Instructions9-7
B
Basic System Configuration................................. 2-1 Block Protection ................................................. 6-16 Block Start Status ............................................... 4-19 Blocks................................................................... 5-3
I
I/O Relay Number .............................................. 1-19 Immediate Detection Mode .................................. 3-4 INACTIVE Status.................................................. 6-7 Index Registers V) ........................................... 4-44 Input Relays (X) ................................................... 4-1 Internal Relays (I)................................................. 4-6 Interrupt Processing Control .............................. 3-27 Interrupt Processing ........................................... 3-26 Interrupt Programs ............................................... 5-8
C
Changing Data Values ....................................... 6-13 Clear Device......................................................... 6-3 Clear Memory....................................................... 6-3 Commands......................................................... 6-36 Communication Procedure ................................ 6-34 Computation Method............................................ 3-7 Configuration................................................. 1-9, 9-3 Configuring Link Relays (L) and Registers (W) Constant Scan...................................................... 6-5 Counter (C) ........................................................ 4-29 CPU Service....................................................... 3-22 Current Values ................................................... 6-13
L
Link Data Updating............................................. 3-23 Link Refreshing .................................................. 3-24 Link Registers (W)............................4-12, 4-14, 4-16 Link Relay (L) ...................................4-12, 4-13, 4-16
M
Macro Instructions.............................................. 6-46 Main Routine Programs ....................................... 5-6 Main Unit ............................................................ 1-16 Making Programs Resident in ROM .................. 6-18 Making Programs Resident................................ 6-18 Method of I/O Processing................................... 3-11 Minor Errors ....................................................... 8-10 Mnemonic Language............................................ 5-2 Mode Status ................................................ 4-22, 1-4 Multi-CPU System Configuration ......................... 2-1
D
Data Registers (D) ............................................. 4-31 Debug Mode......................................................... 6-3 Debugging Operation ......................................... 6-57 Device List............................................................ 1-7 Device Management Function ........................... 6-45 Differences from F3SP25 and F3SP35................ 9-1 Differences from Personal Computer Link Module............................. 6-30
N
Non-fatal Errors .................................................. 8-10
E
Exclusive Access Control ................................... 6-23 Executable Program Protection ......................... 6-15 Executable Program............................................. 5-4 Executing All Blocks ............................................. 6-6 Executing Specified Blocks .................................. 6-7 Extended Shared Registers (R) ......................... 4-32 Extended Shared Relays (E) ............................... 4-7 Extended System Configuration .......................... 2-4
O
Online Editing..................................................... 6-17 Operation in case of Complete Power Failure ..... 3-6 Operation in case of Momentary Power Failure... 3-6 Output Relays (Y)................................................. 4-2
IM 34M6P13-01E
Index-2
P
Peripheral Processes ........................................... 3-9 Personal Computer Link Function...................... 6-28 Personal Computer Link Service ....................... 3-15 Personal Computer Link System ......................... 2-5 Power Failure ...................................................... 3-6 Program Memory ............................................... 5-10 Programming Language ...................................... 5-1 Protecting Programs .......................................... 6-15 Ranges of Devices To Be Latched in case of Complete Power Failure............ 3-6
U
Unit ..................................................................... 1-16 User Log Management Function........................ 6-62 Utility ............................ 4-20, 4-41, App.1-2, App.2-3
W
WideField2 ........................................................... 2-6
R
Remote I/O System.............................................. 2-4 Response Delay................................................. 3-12 Responses ......................................................... 6-36 ROM Clear Function .......................................... 6-22 ROM Compare Function .................................... 6-22 ROM Copy Function........................................... 6-22 ROM Transfer function ....................................... 6-22 ROM Write Functions......................................... 6-21 Run Mode............................................................. 6-3
S
Sampling Trace .................................................. 6-24 Selecting Timers................................................. 4-28 Self-diagnosis .............. 4-23, 4-40, App.1-4, App.2-2 Self-diagnosis Status Registers ...........4-40, App.2-2 Self-diagnosis Status...................4-23, 4-40, App.1-5 Sensor Control Block ........................................... 5-9 Sensor Control Function .................................... 6-64 Sequence CPU Module Operation Modes........... 3-1 Sequence CPU Module Status .......................... 4-43 Sequence Operation Status .................4-39, App.2-1 Sequence Operation ............................4-22, App.1-3 Setpoints ............................................................ 6-15 Setting Scan Time Monitoring Time ..................... 7-4 Shared Refreshing ............................................. 3-18 Shared Registers (R) ......................................... 4-32 Shared Relays (E)................................................ 4-7 Slot Number ....................................................... 1-17 Special Registers (Z)............................................ 9-5 Special Relays (M) ............................................... 9-5 Specifying Input Sampling Interval....................... 4-4 Specifying Input Sampling Interval....................... 4-4 Standard Mode..................................................... 3-4 Stop Mode ............................................................ 6-3 Stop Refreshing.................................................. 6-14 Structured Ladder Language ............................... 5-1 Subroutine Programs ........................................... 5-7 Subunit ............................................................... 1-16
T
Timer (T)............................................................. 4-25 Tool Service........................................................ 3-14
IM 34M6P13-01E
Revision Information
Document Name : Sequence CPU Instruction Manual - Function (For F3SP28-3N/3S, F3SP38-6N/6S, F3SP53-4H/4S, F3SP58-6H/6S, F3SP59-7S) Document No.
Edition 1st 2nd
: IM 34M6P13-01E
Revised Item New publication Included F3SP59, for - S Incorporated addendum, errata
Written by
Product Marketing Department, IT Controller Center. Yokogawa Electric Corporation Published by Yokogawa Electric Corporation 2-9-32 Nakacho, Musashino-shi, Tokyo, 180-8750, JAPAN Printed by Yokogawa Graphic Arts Co., Ltd.
IM 34M6P13-01E
Blank Page