Combinational-circuit synthesis

Problem (in word description) Design circuit (circuit description) Circuit minimization Circuit realization (logic circuit, simulation, function and timing analysis, implementation)

Circuit description and design

Circuit description:
A list of input combinations for which a signal should be on or off (design a 4-bit prime number detector) Verbal equivalent of a truth table (given N=N0N1N2N3, produce a 1 if N=1,2,3,5,11,13, and 0 otherwise) A or notation

Circuit description and design

Circuit description:

Circuit Manipulations
Translate logic function into an equivalent sum-ofproduct expression (by simply multiplying out)

Convert into sum-of-product

Circuit Implementation
Insert a pair of inverters between each AND-gate output and corresponding OR-gate input in a twolevel AND-OR circuit

NAND

Circuit Implementation
If any product terms in the sum-of-products expression contain just one literal, we may lose or gain inverters in the transformation from AND-OR to NAND-NAND.

gain

lose
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Circuit Manipulations
Any sum-of-products expression can be realized as AND-OR circuit or as NAND-NAND circuit. Any product-of-sum expression can be realized as OR-AND circuit or as NOR-NOR circuit.

Circuit Minimization
Reducing the number and size of gates needed to build the circuit. Reducing the cost of a two-level AND-OR, OR-AND, NAND-NAND, NOR-NOR
Minimize the number of first-level gate Minimize the number of inputs on each first-level gate Minimize the number of inputs on the second-level gate

Based on T10 and T10.

( (

Karnaugh maps
Graphical representation of a logic functions truth table.

Copy 1s and 0s from the truth table to the corresponding cells of the map.

Karnaugh maps
Examples.

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Karnaugh maps
Example

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Karnaugh maps
Example

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Karnaugh maps
Example: prime number detector

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Karnaugh maps
Example: prime number detector
Karnaugh map minimization

Canonical-sum design

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Karnaugh maps
More examples

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Timing hazards
Static hazards:
Static-1 hazard is a pair of input combinations that: (a) differ in only one input variable and (b) both give a 1 output; such that it is possible for a momentary 0 output to occur during a transition in the different input variable.

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Timing hazards
Finding static hazards using maps:
The existence or non-existence of hazard depends on circuit design for a logic function.

Original design

Static-1 hazard eliminated

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Timing hazards
Static hazards:
Static-0 hazard is a pair of input combinations that: (a) differ in only one input variable and (b) both give a 1 output; such that it is possible for a momentary 1 output to occur during a transition in the different input variable.

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Timing hazards
Dynamic hazards:
Is a possible of an output changing more than once as the result of a single input transition. Multiple output transitions can occur if there are multiple paths with different delays from the changing input to the changing output.

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