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University of Toronto
slide 1 of 34
D.A. Johns, K. Martin, 1997
Silicon Wafer
Create 8 diameter cylinder (1m long) of single-crystaline silicon with light doping (usually p-) Ingot cut into wafers about 1mm thick Photolithography Portions of silicon wafer are masked out so processing can be applied to remaining areas First create glass mask with dark areas using e-beam (cost of mask set often >$50k) Thermally grow SiO2 on wafer, apply negative photoresist, align glass mask and expose to UV light Photoresist hardens (after baking) where exposed to light, remaining region removed (including SiO2) Negative since SiO2 removed where mask is light
University of Toronto slide 2 of 34
D.A. Johns, K. Martin, 1997
Photolithography
Ultraviolet light
Opaque region
p substrate
SiO2
University of Toronto
slide 3 of 34
D.A. Johns, K. Martin, 1997
Diffusion
Gas containing phosphorus
2PH3 + 4O2
n well
SiO2
p substrate
Introduce dopants where well will be located Phosphorus gas used in furnace (1000 C)
University of Toronto
slide 4 of 34
D.A. Johns, K. Martin, 1997
Ion Implantation
Vertical and horizontal deflection plates
Ion
Separating slit Focusing lens Focusing lens Acceleration plates beam Target
Ion source
More control as can set concentration and thickness Acceleration sets depth, current and time set dosage However, lattice damage and narrow doping profile requires annealing
University of Toronto slide 5 of 34
D.A. Johns, K. Martin, 1997
Annealing
Ion dopant
concentration Before annealing
After annealing
Field-implants
Si3N4 PR3 PR2 Boron ions PR2
Ensures silicon under field-oxide will not invert (will remain p-) although conductors above
University of Toronto
slide 7 of 34
D.A. Johns, K. Martin, 1997
Field-oxide
Si3N4 SiO2 Field-oxide
n well p+ field-implants
p substrate
Thick SiO2 where no transistors Wet process (H2O) fast but more defects Dry process (O2) slower but denser and higher quality (high temp so called thermal oxide)
University of Toronto slide 8 of 34
D.A. Johns, K. Martin, 1997
Thin oxide grown using dry process (0.01 m ) If n-well more heavily doped then single boron implant will adjust Vtn from -0.1V to 0.8V and Vtp from -1.6V to -0.8V
University of Toronto slide 9 of 34
D.A. Johns, K. Martin, 1997
Polysilicon Gates
PR4 SiO2 Polysilicon gate
n well p+ p substrate
Apply gate but only heat to 650 C polysilicon (rather than single crystal) 10 to 30 and thickness of 0.25 m
University of Toronto
slide 10 of 34
D.A. Johns, K. Martin, 1997
P+ Junctions
PR5 PR4 Polysilicon Polysilicon PR5 PR4
p+ n well p
+
p+ p+ p substrate
p+ p+ p+
Substrate connection
Gates and drains formed for p-channel Use ion implantation Self-aligned as gate determines edges Substrate connection also shown
University of Toronto
slide 11 of 34
D.A. Johns, K. Martin, 1997
N+ Junctions
PR6 Polysilicon gates PR6
n+
p+
p+
n+ p+
p+ p+
n+
n+ p+
n
p-channel junctions Well tie p substrate
Substrate tie
n-channel junctions
p+ regions protected and n+ implanted Requires annealing after since ion implantation used Would melt gate if it were metal
University of Toronto
slide 12 of 34
D.A. Johns, K. Martin, 1997
n+ n
p+
p+
n+ p+ Well tie
n+
n+ p+ Field-oxide
n-channel transistor
University of Toronto
slide 13 of 34
D.A. Johns, K. Martin, 1997
n+ p+ n+
n p+
p substrate p+ p
n+
SiO2
University of Toronto
slide 14 of 34
D.A. Johns, K. Martin, 1997
Transistor Layout
W L Active region
Field-oxide region Polysilicon mask
Active-region mask W 2
Contact mask
4 2
2 2 L
University of Toronto
slide 15 of 34
D.A. Johns, K. Martin, 1997
Mask misalignment
Gate poly Source junction Drain junction Noncatastrophic misalignment
University of Toronto
slide 16 of 34
D.A. Johns, K. Martin, 1997
Less capacitance at node J3 since less area AND not beside field implants
J1
Q1 Q
1
10
Q2 Q
2
J2
2 2
University of Toronto
2
slide 17 of 34
D.A. Johns, K. Martin, 1997
CMOS Inverter
n+ well tie p+ junction n well
Q2 Vin
VDD
Vout
Poly interconnect
Q1
Gnd
Vin
Q1
n+ junctions
p+ substrate tie
University of Toronto
slide 18 of 34
D.A. Johns, K. Martin, 1997
Active region
J1 Q1
J2 Q2
J3 Q3
J4 Q4
J5
Gates Node 2 VG
University of Toronto
slide 19 of 34
D.A. Johns, K. Martin, 1997
Node 2
VG
Node 1
Q 1 J2 VG J1
Q 2 J2 J3
Q3 J4 J3
Q 4 J4 J5 Node 2
University of Toronto
slide 20 of 34
D.A. Johns, K. Martin, 1997
Polysilicon gate
Transistor channel
p+ field implants
University of Toronto
slide 21 of 34
D.A. Johns, K. Martin, 1997
GM2
M2
M2
M1
M1
M2
M2
M1
M1
GM1
DM2
M2
slide 22 of 34
D.A. Johns, K. Martin, 1997
M1
University of Toronto
y1
Use unit sized capacitors as much as possible If not unit sized, keep the same perimeter-to-area ratio to minimize errors
University of Toronto slide 23 of 34
D.A. Johns, K. Martin, 1997
Capacitor Layout
10 m 10 m 10 m 19.6 m 6.72 m 4 units 2.314 units 10 m
Want to maintain ratio of 4 to 2.314 Rectangular capacitor of size 1.314 units used has same perimeter-to-area ratio as square also has same number of corners
University of Toronto
slide 24 of 34
D.A. Johns, K. Martin, 1997
(1)
(2)
(3)
slide 25 of 34
D.A. Johns, K. Martin, 1997
C1
C2
C2
C1
Well region
University of Toronto
slide 26 of 34
D.A. Johns, K. Martin, 1997
10
2.11
University of Toronto
slide 27 of 34
D.A. Johns, K. Martin, 1997
Dummy resistor
Dummy resistor
R1
R2
R1
R2
University of Toronto
slide 28 of 34
D.A. Johns, K. Martin, 1997
Analog region
p+ psubstrate
n+ n well
p+
Digital region
Depth of well causes higher impedance since doping usually higher near surface of p- substrate (perhaps 10 times higher resistance!)
slide 30 of 34
D.A. Johns, K. Martin, 1997
University of Toronto
Sheilding Signals
Ground line used for shielding Analog interconnect Digital interconnect
n+ n well
n+
n+
p substrate
Shields keep noise from being capacitively coupled into or out of substrate
University of Toronto
slide 31 of 34
D.A. Johns, K. Martin, 1997
V SS
Gnd
Contact to substrate
Capacitors
Region for n-channel switches Switches n well under p-channel switch region
V DD Gnd 1 1 2 2
Clock lines
University of Toronto
slide 32 of 34
D.A. Johns, K. Martin, 1997
Latch-Up
Vin VDD VDD
p+
n+
Q1
n+
p+ n well
Q2
p+ n+ Rn
Rp
p substrate
Occurs when large substrate or well currents Creates an SCR that might turn on and not off until harm done (or power turned off)
University of Toronto
slide 33 of 34
D.A. Johns, K. Martin, 1997
Latch-Up
VDD = 5 V Rn Q2 0V Vinv Rp 5V Q1 Rp Q1 Q2 VDD = 0.9 V Rn
Capacitive coupling due to junction depletion caps of MOS drains Have many substrate contacts and guard rings
University of Toronto slide 34 of 34
D.A. Johns, K. Martin, 1997