I2C Protocol

I2C(Inter-Integrated Circuit) generally referred as a Two Wire Interface. It is a multi-master serial single-ended computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, or cell phone or other electronics. Introduction I2C bus = Inter-IC Bus Simple Bi-directional 2-wire bus- serial data(SDA) & serial clock(SCL) Originally to interact within small num. of devs(radio/TV tuning....) Speeds

-100 kbps (standard mode) -400 kbps (fast mode) -3.4 Mbps (high-speed mode)

Has become a worldwide industry standard and used by all major IC manufacturers. Data transfer: serial, 8-bit oriented, bi-directional. Addressing: 7bit or 10bit address. Multi-master capable bus with arbitration feature. Master-Slave communication. Master can operate as transmitter or receiver Each IC on the bus is identified by its own address code. The slave can be a: Receiver-only device transmitter with the capability to both receive and send data.

Design IC uses only two bidirectional open-drain lines, Serial Data Line (SDA) and Serial Clock (SCL), pulled up with resistors. Typical voltages used are +5 V or +3.3 V although systems with other voltages are permitted. The bus wires are named SDA (serial data) and SCL (serial clock). These two bus wires have the same configuration. They are pulled-up to the logic high level by resistors connected to a single positive supply, usually +3.3 V or +5 V but designers are now moving to +2.5 V and towards 1.8 V in the near future. All the connected devices have open-collector (open-drain for CMOS - both terms mean only the lower transistor is included) driver stages that can transmit data by pulling the bus low, and high impedance sense amplifiers that monitor the bus voltage to receive data. Unless devices are communicating by turning on the lower transistor to pull the bus low, both bus lines remain high. To initiate
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communication a chip pulls the SDA line low. It then has the responsibility to drive the SCL line with clock pulses, until it has finished, and is called the bus master.

The I2C Physical Protocol When the master wishes to talk to a it begins by issuing a start sequence on the I2C bus. A start sequence is one of two special sequences defined for the I2C bus, the other being the stop sequence. The start sequence and stop sequence are special in that these are the only places where the SDA (data line) is allowed to change while the SCL (clock line) is high. When data is being transferred, SDA must remain stable and not change whilst SCL is high. The start and stop sequences mark the beginning and end of a transaction with the slave device.

Data is transferred in sequences of 8 bits. The bits are placed on the SDA line starting with the MSB (Most Significant Bit). The SCL line is then pulsed high, then low. Remember that the chip cannot really drive the line high, it simply "lets go" of it and the resistor actually pulls it high. For every 8 bits transferred, the device receiving the data sends back an acknowledge bit, so there are actually 9 SCL clock pulses to transfer each 8 bit byte of data. If the receiving device sends back a low ACK bit, then it has received the data and is ready to accept another byte. If it sends back a high then it is indicating it cannot accept any further data and the master should terminate the transfer by sending a stop sequence. The I2C Software Protocol Send a start sequence Send the I2C address of the slave with the R/W bit low (even address) Send the internal register number you want to write to Send the data byte Send the stop sequence.

Masters and Slaves

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The devices on the I2C bus are either masters or slaves. The master is always the device that drives the SCL clock line. The slaves are the devices that respond to the master. A slave cannot initiate a transfer over the I2C bus, only a master can do that. There can be, and usually are, multiple slaves on the I2C bus, however there is normally only one master. It is possible to have multiple masters, but it is unusual and not covered here. Slaves will never initiate a transfer. Both master and slave can transfer data over the I2C bus, but that transfer is always controlled by the master. Reading from the Slave Send a start sequence Send 0xC0 ( I2C address of the CMPS03 with the R/W bit low (even address) Send 0x01 (Internal address of the bearing register) Send a start sequence again (repeated start) Send 0xC1 ( I2C address of the CMPS03 with the R/W bit high (odd address) Read data byte from CMPS03 Send the stop sequence. The bit sequence will look like this:

SPI PROTOCOL
The SPI (Serial Peripheral Interface Bus) bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master4

slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select lines. Sometimes SPI is called a "four-wire" serial bus. Introduction
SPI Serial Peripheral Interface. Full Duplex Communication. Higher Throughput then I2C. Complete protocol flexibility for the bits transferred. Slaves use the master's clock, and don't need precision oscillators. Uses only four pins on IC packages, and wires in board layouts or connectors,

much less than parallel interfaces. At most one "unique" bus signal per device (chip select); all others are shared. Clock speed is in MHz (1-70MHz). SPI is a Master-Slave protocol. l The Master device controls the clock (SCK) l No data is transferred unless a clock signal is present l All slaves are controlled by the master clock l The slave devices may not manipulate the clock Communication between the two processors is handled via the serial peripheral interface (SPI). Every SPI system consists of one master and one or more slaves, where a master is defined as the microcomputer that provides the SPI clock, and a slave is any integrated circuit that receives the SPI clock from the master. It is possible to have a system where more than one IC can be master, but there can only be one master at any given time.

The SPI bus specifies four logic signals: SCLK: Serial Clock (output from master) MOSI; SIMO: Master Output, Slave Input (output from master) MISO; SOMI: Master Input, Slave Output (output from slave) SS: Slave Select (Active low output from master).
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Timing Diagrams-

Master-Slave Communication-

Applications Sensors: temperature, pressure, ADC, touchscreens, video game controllers Control devices: Audio Codec, digital potentiometers, DAC Camera lenses: Canon EF lens mount Communications: Ethernet, USB, USART, CAN,IEEE 802.15.4,IEEE 802.11, handheld video games Memory: Flash and EEPROM Real-time clocks LCD displays, sometimes even for managing image data Any MMC or SD card.

Disadvantages SPI doesnt have acknowledge mechanism to confirm receipt of data. Requires more pins on IC packages than IC, even in the "3-Wire" variant No in-band addressing; out-of-band chip select signals are required on shared buses No hardware flow control by the slave (but the master can delay the next clock edge to slow the transfer rate) No hardware slave acknowledgment (the master could be "talking" to nothing and not know it) Supports only one master device No error-checking protocol is defined
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 Generally prone to noise spikes causing faulty communication Without a formal standard, validating conformance is not possible Only handles short distances compared to RS-232, RS-485, or CAN-bus Many existing variations, making it difficult to find development tools like host

adapters that support those variations