####################################################################### # Resume ####################################################################### # Name Email Contact Nationality : : : : Ramu B. ramu_bku@hotmail.com. 9396582398. Indian.

Bachelor of Engineering(Electronics & Communications) from Jawaharlal Nehru Technological University, Andra Pradesh, India, in 1998 Jun. Total of 7 Years.

Qualification :

Experience

Worked in Qualcomm Private Limited from October-2003 to Feb-2005. At the time of leaving, held position is Senior Member of Technical Staff. Worked in Motorola(Both in India,U.S.A(2 years in U.S.A)) from April-2000 to October-2003. Help Senior Design Engineer position at the time of leaving the company. Worked in Qualcore Logic Private Limited, India from April-1998 to Jan-2000. Held Asic Design Engineer position as the time of leaving the company.

Technical summary : Had experienced many projects, which are from specification development to tape out, post silicon debug. Many products worked on went to production. Had experienced projects with wide variety of methodologies. Ex : MuxD, LSSD, ASICs, SOCs with Analog designs(Like PLL, DLL etc) etc... Expertise in state machine design, verilog coding skills for efficient synthesis, static timing analysis and DFT. Experience in generating the timing requirements(speed paths, multi cycle paths, false paths, clock enable and tristate enable timings etc...). Expertise in placing the design to achieve heavily critical skew requirements. Tools

:
Design compiler, Physical Compiler, Test Compiler, DFT Compiler, Prime Time, Tetramax., Fastscan.

Company :

Qualcomm.

Phoenix A SOC, cell phone(Qualcomms project). Role: Static timing analysis methodology development for Logic bist. Scan insertion methodology. Logic bist analysis with Encounter Test bench. Tools Used: Prime time For timing analysis. DFT compiler For scan insertion. Encounter testbench For Lbist analysis. Modelsim For simulations. Project duration From July2004 to Ongoing. JLO AN ASIC. Description: A power amplifier with analog and digital logic. Role: Responsible for tapeout of the chip digital logic. Synthesis of digital portion of the design. Scan insertion of the digital portion of the design. Static timing analysis of the digital portion of the design. ATPG at the chip level. Tools Used: Design compiler For synthesis. DFT advisor For scan insertion. Prime time For timing analysis. Fastscan For DFT analysis. Modelsim For simulations. Project duration From Jan2004 to July2004. Carmen AN ASIC. Description: A power amplifier with analog and digital logic. Role: Responsible for tapeout of the chip digital logic. Synthesis of digital portion of the design. Scan insertion of the digital portion of the design. Static timing analysis of the digital portion of the design. ATPG at the chip level. Tools Used: Design compiler For synthesis. DFT advisor For scan insertion. Prime time For timing analysis. Fastscan For DFT analysis.

Modelsim Project duration

For simulations. From Oct2003 to Mar2004.

Company:

Motorola.

P2002 A SOC DSP platform Role: Physical synthesis of some of the sub-modules. Scan insertion of some of the blocks. DFT analysis for the platform. Tools Used: Physical Compiler Test compiler Tetramax Verilog-XL Project duration For synthesis. For scan insertion. For ATPG analysis. For simulations. From Sep2002 To Aug2003.

P2001 A DSP Platform Role: DFT analysis for the platform. Creating ATPG patterns at platform level. Tools Used: Tetramax Verilog-XL Project duration For ATPG analysis. For simulations. From july2001 To Sep2002.

Patriot A SOC, cell phone

Role: DFT analysis at module level. DFT analysis at chip level. Tools Used: Fastscan Verilog-XL Project duration -

For ATPG analysis. For simulations. From April2000 To July2001.

Company:

Qualcore.

I2C(Inter IC) serial communication protocol

Role: Developing the micro architecture.

Developing the RTL code. Writing stand alone verilog test benches. Synthesis and scan insertion. Static timing analysis. Tools Used: Design Compiler Test compiler Verilog-XL For Synthesis. For scan insertion. For RTL and Gate simulations.

UART

Role: Developing the micro architecture. Developing the RTL code. Writing stand alone verilog test benches. Synthesis and scan insertion. Static timing analysis. Tools Used: Design Compiler Test compiler Verilog-XL For Synthesis. For scan insertion. For RTL and Gate simulations.

Framer

Description: The design does de-multiplexing of number of voice channels that are time division multiplexed and enclosed in a protocol. Role: Developing the micro architecture. Developing the RTL code. Writing stand alone verilog test benches.

Circular buffer

Description: This design is basically buffer, a synchronizer between two different clock domains. At one end, it will take the data from a clock domain. At the other end, data is taken out of the buffer from another clock domain. This design involves synchronization and hand shaking required for transferring the data from one clock domain to another. Also, provides a way to rotate the data in the buffer. Role: Developing the micro architecture. Developing the RTL code.

Writing stand alone verilog test benches. Doing static timing analysis.