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EE231 Solid State Devices

Professor: Vivek Subramanian viveks@eecs.berkeley.edu 571 Cory Hall (510) 643-4535 Alejandro de la Fuente Vornbrock, adelafv@eecs.berkeley.edu


Web Page: http://www-inst.eecs.berkeley.edu/~ee231/ http://organics.eecs.berkeley.edu/~viveks/ee231 Newsgroup: ucb.class.ee231

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An Important Note Professor Subramanian is in Japan today, and will return tomorrow. He apologizes for not being here. Regular lectures will begin on Thursday

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Lectures: 299 Cory, Tue/Thu, 2pm-3:30pm Discussion:
Section 101 Monday, 5pm-6pm 299 Cory


Office Hours:
Vivek Subramanian (571 Cory):
Tue 9:30am-10:30am (EE231 Priority) Tue 1pm-2pm (EE143 Priority) Th 9:30am-10:30am (EE143 + EE231)

Alejandro de la Fuente, Wed 10:30am-11:30am (197 Cory)

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Reading Material
Primary Text:
Silicon Processing for the VLSI Era, Vol. 3 - The submicron MOSFET S.Wolf Lattice Press, 1995

Reference Texts:
Fundamental of Modern VLSI devices Y. Taur, T. Ning Cambridge University Press, 1998 Device Electronics for Integrated Circuits R. S. Muller and T. I. Kamins Wiley
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Midterm design project
MOSFET design, assigned in Mar/April (~2 week duration) You must work alone
20% Letter grades will be assigned based approximately on the following scale: A+: 95-100 A: 88-95 A-: 85-88 B+: 80-85 B: 73-80 B-: 68-73 C+: 65-68 C: 60-65 C-: 55-60 D: 40-55 F: <40

Tests (~3-4)
~45 minutes each given periodically per schedule Open book and notes No makeups


Final Paper
Will be assigned approx. 3 weeks before end of class Due on last day of class

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Text Coverage
The text will serve primarily as a reference (i.e., notes supercede text)
Chapter 3. MOS Capacitor
3.2 Qualitative description 3.3 Quantitative analysis of Qs(Vs) 3.4 VT 3.5 Charge Traps 3.6 VT 3.7 Optional reading

Chapter 6. Isolation Technology (Assigned Reading)

6.1 Introduction. Do read p. 324 6.2 LOCOS, the basic isolation technology 6.4 Modified (advanced) LOCOS 6.5 Shallow Trench ---beyond LOCOS 6.6 (pp.405--413 only) CMOS isolation

EE231 Vivek Subramanian

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Text Coverage
Chapter 4. Long Channel MOSFET
4.1 Introduction 4.2-4.5.2 Omit pages 137-169. 4.5.3-4.5.6 IV models of decreasing accuracy and complexity. 4.6 VT Control by Ion Implantation. Omit 4.6.4 4.7 Subthreshold Current

Chapter 1 & Chapter 2. Device Simulators (assigned reading)

1.2.2 Equations to be solved 2.8- Omit p.66 Procedure of Device Simulation 2.12 Device Simulators

Chapter 5. Advanced MOSFET

5.2 VT Roll-off (DIBL or Short-Channel effect) 5.3 Punchthrough 5.4 IV of Short Channel MOSFET 5.5 SPICE Model 5.6-5.7 MOSFET Design. Omit pp. 279-284 5.8 PMOSFET
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Text Coverage
Chapter 8. CMOS Well Technology (assigned reading)
8.1 N-well, P-well and Twin-well 8.4 High-energy implant

Chapter 9. Hot carrier Effect and LDD

9.1-9.2 Models of maximum Channel Field and Substrate Current 9.3 Hot-Carrier Induced MOSFET Degradation 9.4 MOSFET Lifetime 9.6 Light Doped Drain(LDD) 9.12 (pp.630-636 only) More LDD Structures 9.13 PMOS Hot-Carrier Effect 9.14 (Omit pp.648-653) Improving the oxide

Chapter 7. Gate Oxide

7.1 Introduction 7.2 (Assigned Reading) Microscopic Structure of Si/SiO2 Interface 7.3-7.8 Will be replaced by Reliability of Thin SiO2, Schuefrag et al 7.9 (Assigned Reading) Thin Oxide Growth Technology 7.10 (Assigned Reading) Plasma-Processing Charging Damage
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Introduction to Process and Device Simulation: Using TSUPREM4 and Medici In this class, you will make extensive use of process and device simulation in your projects and term papers. Therefore, it is imperative that you learn to make use of these tools ASAP

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Logistics You will need an account on either the instructional machines (cory, mingus, etc., open to all students in EE231) or the device cluster (open only to device group students) If you need an instructional account, go to: http://www-inst.eecs.berkeley.edu and follow the instructions to obtain an account
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Why Simulation? Process (TSuprem4) and device (Medici) simulators are indispensable tools in the device community Simulators provide insight on processing steps, device physics, feedback in device design, and are important areas of research Simulation does not replace design!!!
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Design Flow
Feedback Feedback Device design NA, tox, W, L, Vt, etc. Device Physics Feedback

TSUPREM4 Process simulation Process Technology

MEDICI Device simulation Final Device

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Simulates all major process steps in 2-D Deposition Implant Oxidation Diffusion Lithography Etc. Analytical and empirical models are used to predict device cross-sections and doping profiles
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Simulates electrical characteristics of a given 2-D device structure Takes voltage bias at each electrode Program solves Poissons equation to determine the potential distribution in a device Applies various models for carrier transport to determine the current at each terminal
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Getting started
TSUPREM4 and MEDICI both take a text file as input Outputs text that is piped to the terminal Output includes simulation information and user-specified data (plots, cross-sections, values, etc.) bcpmoss4.out


plots and/or profiles TSUPREM

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Getting started
Use text editor to create decks (vi, emacs, pico) Simulators are run off UNIX workstation or PC with Hummingbird

/share/b/bin/tsuprem4 Set path = ( $path /share/b/bin) For device group computers: /project/eecs/device-apps/synopsys/Y_2006.06/bin LM_LICENSE_FILE=27000@cory Pop up windows: setenv DISPLAY [ip_address_or_computer_name] % tsuprem4 [input_file_name]
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Anatomy of a TSUPREM Deck

Grid Definition Initialize Structure Process Flow Electrode Definition Save Structure Plot Cross-Section
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Anatomy of a Medici Deck

Load Structure

Choose Models Initial Solution Plot Structure

Curve simulation

Plot generation
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Simulator Manuals
TSuprem and Medici Manuals are valuable resource for Input Statements and Examples
/project/eecs/device-apps/synopsys/Y_2006.06/taurus-[medici or tsuprem4]/manuals_pdf

Can find Input Statement Fields and Capabilities

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Example: Basic CMOS Process

Lets design a NMOSFET (L=0.65 um)

Gate Source Substrate Drain

(From example deck s4ex4*.inp) /share/instsww/synopsys/tcad/tcad-suprem-4_v2002.4/ tsuprem4_2002.4.0/examples/

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Example: TSUPREM Input

Start with ptype wafer


Define active region

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Example: TSUPREM Input

Ion implantation

Field Oxide

Plot initial structure

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Example: TSUPREM Output

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Grid Structure
Divides the device cross-section into a 2-D array of discrete grid points Necessary for SUPREM and MEDICI to calculate solutions A finer grid is more accurate but also increases simulation time
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Defining the Grid

grid.fac is the most straightforward way to vary grid density

Grid spacing can be varied spatially: Line Eliminate Boundary Region Grids can also be defined with saved structure files
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Simulation as used in EE231

You will be designing MOSFETs as part of your mid-term design project Your designs will likely involve use of TSUPREM and MEDICI to create some advanced MOSFET structure You will use need to be very familiar will TSUPREM and/or MEDICI to successfully complete the project in the time allotted; therefore, you should take the time now to learn how to use these tools The online examples are an excellent starting point for self-paced learning
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