FPGA registers All the control registers implemented in FPGA are placed in 8051 XRAM memory area and

are accessible using 51 MOVX instruction PCI master state machine control registers Registers are Read/Write type, if not stated otherwise
Address 0x8000 Description PCI master state machine control Bits: D7 D6 D5 D4 D3 D2 D1 D0 D7...D4 PCI BE3...BE0 byte enables signals in full access mode. In decode mode D5..D4 indicate transfer size: 00 32bit,8bit address (ADR0), data in DAT3..DAT0 01 16bit,8 bit address, data in DAT1..DAT0 10 8bit, 8 bit address, data in DAT0 D3: 0 = full access mode (non-decode), BE3..BE0 are controlled by D7..D4, Address is 32bit, AD32 reflect data registers 1 = address/data decoding, BE3..0 are controlled automatically and data/address lines are switched to simplify PCI master access. Address is 8bit: ADR0 D2: 1 = READ, 0=WRITE D1: 1= BUSMASTER ENABLE D0: 1= configuration mode, 0= transfer mode PCI master state machine & camera status Bits: D7..D6 RFU D5 SHT11 READY humidity and temperature sensor status measurement is completed D4 Bus-master pending PCI BUSMASTER transfer is not completed D3 BUSY PCI state machine is busy D2 transfer done PCI transfer is finished D1,D0 RFU ADR3 Read/Write address 31..24 ADR2 Read/Write address 23..16 ADR1 Read/Write address 15..8 ADR0 Read/Write address 7..0 Writing any value to this register starts PCI master transaction, write this register as the last one DAT3 Read/Write data 31..24, Data can be read after finishing PCI transfer DAT2 Read/Write data 23..16, Data can be read after finishing PCI transfer DAT1 Read/Write data 15..18, Data can be read after finishing PCI transfer DAT0 Read/Write data 7..0, Data can be read after finishing PCI transfer, all data registers must be written before ADR0 Ethernet buffer address pointer 0 ( 15..8) auto increment after R/W operation Ethernet buffer address pointer 0 ( 7..0) auto increment after R/W operation Pointer 0 Data Read operations return result in the same cycle Ethernet buffer address pointer 1 ( 15..8) auto increment after R/W operation Ethernet buffer address pointer 1 ( 7..0) auto increment after R/W operation Pointer 1 Data Read operations return result in the same cycle

0x8001 Read only

0x8002 0x8003 0x8004 0x8005 0x8006 0x8007 0x8008 0x8009 0x800A 0x800B 0x800C 0x800D 0x800E 0x800F

SDRAM & CCD control registers

Address 0x8100 Description SDRAM controller control register Bits: D7: allow address counter loading if this bit is set, address counter of DRAM controller is auto loaded at the beginning of every transfer. This option is useful during single transfers, when each transfer corresponds to sequent address D6: terminate SDRAM setting this bit will terminate SDRAM transfers D5: USB/ETH mode, 1 = USB mode, 0 ethernet mode D4: start generate data, 1 = start of test data generation sequence D3: Single transfer mode. 1 = single read/write transfer, set this bit during CCD readout D2: SRAM init . Setting this bit will write value 0x27 to SDRAM control register. Bit must be cleared during next register access cycle D1: Write/Read. 1 = write mode, 0 = read mode D0: Start write/read (DMA or single transfer mode). This bit must be cleared in next register access cycle DMA start address D23..16 data block start address in 2B boundary DMA start address D15..8 DMA start address D7..0 DMA length D23..16. Data block length in 16bit words DMA length D15..8 DMA length D7..0 Frequency select. Bits D5..0 select CCD H&V clock frequencies CCD control Bits: D7..D4 RFU D4: start CCD readout. Clear this bit in next register access cycle D2: test mode. 1= DRAM address counter value instead of CCD data, 0=normal operation D1: 1 = MPP mode on, 0 = normal operation D0: 1 = binning on (CCD clear mode) Camera peripherals control Bits: D7...D4 RFU D3: SHT11 start, clear this bit in next register access cycle D2: Shutter control. 1 = on, 0=off D1: AMPLI. 1 = 0n, 0 = 0ff D0: Heating. 1 = OFF, 0 = ON (negative logic) RFU Version: YEAR Version: MONTH Version: DAY Version: VHDL code version CAMERA ID the position of the address switches (4 or 8 bits), the LSB of IP address In current prototype there are 4 switches used, in next ones there are to be used 8 switches.

0x8001 0x8002 0x8003 0x8004 0x8005 0x8006 0x8007 0x8008

0x8009

0x800A 0x800B 0x800C 0x800D 0x800E 0x800F

RFU reserved for future use FX2 flags assignments: FLAGA empty FLAGB full/programmable level flag

Buffers addresses: All the PA FPGA bus addresses are to be modified in future Currently these areas are accessible only by direct addressing via Ethernet buffer pointers (0x800A..0x800F). In future versions of firmware and hardware there will be implemented indirect buffer access. Currently it was not possible because of limited address space of FPGA mapped into FX2. Buffer name Descriptors: TX H priority TL L priority Rx descriptor Buffers: RX TX0-Header TX0-Data FIFO TX TX1-Header TX1-Data FIFO FPGA PA address R/W Length (8051 Xram address) [B] 0x8200 0x821F 0x8220 0x822F 0x8230 0x823F 0x0000 0x007F 0x8100 0x813F No access 0x8000 0x80BF 0x80BF-0x80FF No access R/W R/W R/W R W W W 2x16 16 16 128 64 1024 192 64 1024 PCI address range 0x0002C0000x002C01F 0x0002C1000x002C10F 0x0002C2000x002C20F 0x000100000x0001007F 0x000200000x0002003F 0x00020040-0x0002043F 0x00028000-0x000280BF 0x000280C0-0x000280FF 0x00028100-0x000281FF R/W R/W R/W R/W W R R R R R Length [W32] 2x4 4 4 32 16 256 48 16 256

Debug commands This commands are used by PCI control panel (Windows) which communicates with debugpci.asm module 1-st 2-nd 3-rd Next Byte Byte Byte Bytes 0xEE 0x01 0x01 aaaad 0x02 aaaadd 0x03 aaaadddd 0x04 aaaadddd 0x02 0x01 aaaa 0x02 aaaa 0x03 aaaa 0x04 aaaa 0x03 0x01 aad 0x02 aa 0x04 0x01 ad 0x02 a 0x05 0x01 aad 0x02 aa Transfer 8bit Read 16bit Read 32bit Read config Read Xram Read SFR Read Buffer Read All Writes Len. 6 6 6 6 6 6 6 6 data ccdxxx ccddxx ccdddd ccdddd ccdxxx ccdxxx ccdxxx ccxxxx Command description PCI 8bit write, aaaa 32b address, MSB first, d 8 bit data PCI 16bit write, aaaa 32b address, dd 16 bit data, MSB first PCI 32bit write, aaaa 32b address, dddd 32 bit data, MSB first PCI CONFIG write aaaa 32b address, dddd 8 bit data, MSB first PCI 8bit read, aaaa - 32b address, MSB first PCI 16bit read, aaaa - 32b address, MSB first PCI 32bit read, aaaa - 32b address, MSB first PCI CONFIG read, aaaa -32b address, MSB first XRAM write, aa 16b address, d-data XRAM read, aa 16b address SFR(indirect) write, a - 8b address, d - 8b data SFR(indirect) read, a-8bit address Buffer memories write, a - 16b address, d - 8b data Buffer memories read, a-16b address Debug command responses cc=OK,d 8b data, x-dont care cc=OK,dd 16b data, x-dont care cc=OK,dddd 32b data, x-dont care cc=OK,dddd 32b data, x-dont care cc=OK,d 8b data, x-dont care cc=OK,d 8b data, x-dont care cc=OK,d 8b data, x-dont care cc =OK,xxxx dont care