Microelectronic Circuits

FOURTH EDITION

SEDRA / SMITH
Chapter. 9 Output Stages and Power Amplifiers

Output Stage Amplifier

Voltage transfer to a very low impedance load
Output stage amplifier should have very low output impedance

Large signal operation

Small signal approximations are not applicable Linearity is very important Total Harmonic Distortion(THD)
THD =

V
i=2

2 i , rms

V1,rms

100, Vi ,rms rms voltage of i th harmonic component

V1,rms rms voltage of fundamental component

Efficiency
Power dissipation in the transistors must be as low as possible

Power amplifier
the output power is greater than 1 W.

Classification of Output Stages

according the conduction angle Class A =360 =360 Class B =180 =180

Class AB 180<<360 180<<360

Class C <180 <180

9.2 Class A Output Stage

vo =v I -v BE1 vomax =VCC -VCE1sat -IR L (when Q1 turn off) vomin =the larger of -VCC +VCE2sat

Maximum Signal Waveform of Class A Amplifier

When RL = VCC / I : I bias current (VCEsat is neglected!) VCC < vo < VCC vCE1 = VCC vo 0 < vCE1 < 2VCC 0 < iC1 < 2 I Power dissipation in Q1 instantaneous power dissipation pD1 =vCE1iCE1 maximum power dissipation pD1max = VCC I quiescent power dissipation = VCC I Need short circuit(R L =0) current protection Power dissipation in Q2 pD 2 max = 2VCC I , pD 2 average = VCC I
Efficiency ! load power PL 1 VO2 = = supply power PS 4 IRLVCC ! 1 VO2 ! ( PL = , PS = 2VCC I , VO peak value of vO ) 2 RL ! = 25% when V = V
max O CC

Class A amplifier is rare in power applications more than 1W

9.3 Class B Output Stage(Push Pull)

QN and QP cannot conduct simultaneously Biased at zero current Transistor conducts only when vI 0
Push-pull amplifier QN pushes current into the load and QP pulls current from the load
Complementary pair of npn, pnp

Crossover distortion is severe when the input signal is small

Dead zone 0.5V<vI<0.5V See Fig. 9.7
QN, QP cut-off

Efficiency of Class B Amplifiers

Effiency " V peak amplitude of output sinusoid
o

Power Dissipation quiescent power dissipation=0 average power dissipation " "2 2 VO 1VO PD = PS PL = VCC RL 2 RL PD max " 2V CC 2 " = 2 when V O = VCC RL
2

"2 1 Vo average load power PL = 2 RL " Vo maximum collector current RL average current from a power supply " " 1 T / 2 Vo Vo sin tdt = T 0 RL RL average power from two power supplies " Vo Ps = 2VCC RL effiency " Vo " = ,max = = 78.5%(when Vo = VCC ) 4 VCC 4 PL max
2 1 VCC = 2 RL

PDN max = PDP max = PD max / 2, =50%

Efficiency increases, but nonlinear distortion also increases approaching the saturation region of QN and QP

Solve Example 9.1

Class AB Output Stage

Class AB Biasing Push-Pull amplifier at small nonzero current. maintain VBEN and VEBP just above the cut-in voltage of 0.5V Both transistors conduct for small vI, which eliminates crossover distortion. For large vI, class AB operates in the same manner as the class B. Bias Current iN = iP = I Q = I S eVBB / 2VT , For vI = 0, vO = 0. For positive vI , vO = vI + VBB / 2 vBEN As vI increases, vBEN also increases but slightly. Therefore most of vI deliveres to vO vO casues a current iL : iN = iP + iL Because vBEN +vEBP =VBB , vEBP decreases. VT ln( IQ iN i 2 ) + VT ln( P ) = 2VT ln( ) iN iP = I Q IS IS IS

For positive vI ,iN increases, iP decreases and QN supplies load current iL For large vI , iP is negligible. Both transistors conduct for small vI . For negative vI , vice versa. Output resistance R out = reN || reP = (VT / iN ) || (VT / iP ) = VT /(iN + iP ) not abrutply changes around small vI

Biasing the Class AB Circuits

Practical method to generate the voltage VBB Biasing using diodes I Q = nI bias n the ratio of the emitter junction area of Q N and QP to the junction area of the diodes iB supplied by I bias . Therefore I bias > iB max (= iL max / N ) Ex 9.2 " (Conditions) VCC =15V, R L =100, V O =10V, Q N and Q P IS =10-13 A, =50, area ratio 3:1 (Questions) (a) the value of Ibias guarateeing idiode min 1mA? (b) Quiescent output current and quiescent power dissipation in the output transistors? (c) VBB ? for vO =0V, 10V, -10V (Ans) " (a) i Lmax =V O /R L =100mA iBNmax =i Lmax / =2mA Ibias =3mA for i diode min 1mA (b)IQ =9mA(IQ =3I bias ) PDQ =2? 5V? mA=270mA (c)VBB =? For v O =0, i BN =9mA/51 # 0.18mA idiode =2.82mA 10-13 A reverse saturation current of diode IS = 3 VBB =2VT ln(2.82mA/IS )=1.26V For vo =10V, Idiode =1mA VBB # 1.21V For v o =-10V, I BN 0mA, Idiode =3mA VBB # 1.26V

Effects of diode Biasing on Thermal Runaway

BJT temperature dependence : -2mV/C
For constant VBE, iC increases by e2mV/VT as 1 C increases

Thermal runaway
Increase of iCincrease of transistor power dissipation increase of junction temperature increase of iC: positive feedback process

Using diode biasing

If diodes are in close thermal contact with the output transistors, the junction temperature of diodes increase by the same amount of the output transistors. Since Ibias is constant, VBB decreases at the same rate as VBEN+VEBP

Biasing Using the VBE multiplier

I R = VBE1 / R1 neglecting base current of Q1 VBB = I R ( R1 + R2 ) = VBE1 (1 + R2 / R1 ) VBE multiplier Determination of VBE1 neglecting base current of Q N I C1 = I bias - I R VBE1 = VT ln( I C1 / I S 1 ) For large positive vo , i BN is not negligible. However, the increase of i BN is compensated by the decrease of iC1 , which leaves I R , and hence VBB almost contant
Example 9.3 redesign of Ex 9.2 using VBE multiplier I bias =3mA: dividing ratio of I bias between IC1 and I R ? Let I R = 0.5mA and I C1 =2.5mA to avoid Q1 cut-off at maximum vO IQ =2mA VBB =1.19V R1 +R 2 =VBB /I R = 2.38k VBE1 =VT ln[2.5mA/(Is of Q1)]=0.66V=R1I R R 1 =1.32k, R 2 =1.06k

In IC, ratio of R 2 /R1 is easily contolled. But, in discrete circuit design, a potentiometer can be used for manual setting of IQ .

Power BJTs
Currents in the ampere range Power dissipation in the watts and tens of watts range Differ from small signal transistors in structure, package, spec. Maximum Junction temperature Tjmax in the range of 150-200C Thermal resistance JA between junction to ambient
TJ(Junction temperature)-TA(ambient temperature)= JA PD(transistor dissipating power) JA is required to be as small as possible Thermal resistances are serially added along temperature gradients path JA =JC(between junction and transistor package)+ CA(between transistor package and ambience) The device manufacturer specifies JC Electrical equivalence of thermal conduction process CS thermal resistance between transistor package to heat sink heat sink is used to reduce CA TJ TA =PD(JC+ CS+ SA)

Derating curve for PDmax

Maximum allowable power dissipation versus the transistor case temperature If the transistor case temperature increases, PDmax decreases.

TJmax -TC PDmax = JC

[Case temperature]

Example 9.5 40W at TC =25o C JC = 3.12o C/W TJmax =150 C , PDmax = o o 2W at TA =25 C JA = 62.5 C/W T TA (a) PDmax when operated in free air TA =50o C PDmax = Jmax = 1.6W
o

JA

(b) PDmax when operated in free air TA =50o C with a heat sink having CS = 0.5o C/W and SA = 4o C/W

JA = JC + CS + SA = 7.62o C/W PDmax = (150 50) / 7.62 = 13.1W

(c) TA =50o C with an infinite heat sink JA = JC + CS + SA = JC PDmax = (150 50) / 3.12 = 32W

The BJT Safe Operating Area

Bonding wire melted if continuous current exceeds the boundary.

Locus of vCEiC=PDmax at TCO(usually 25C) For TC>TCO PDmax decreases. PDmax is average power dissipation. Instantaneous operating point may move above the hyperbola.

Due to current crowding near the periphery of the junction

Even the instantaneous value of vCE should not exceed BVCEO

Variations of Class AB Configuration

Class AB output stage with an input buffer (emitter follower) Darlington configuration

Increase the current gain Equivalent to a single npn transistor Compound configuration

High input impedance Q1 and Q2 biasing the Q3 and Q4 R3, R4 : very small and compensating the mismatch between Q3 and Q4 and preventing the thermal runaway

In IC, lack of good quality pnp Equivalent to a single pnp transistor Q1 :lateral pnp having a low Poor frequency response due to using pnp

Short Circuit Protection/Thermal Shut Down

In the event of an output short circuit while vo is positive Short circuit large current flows through Q1 a voltage drop across RE1 Q5 turn-on most of Ibias flow through Q5 decrease of base current of Q1 Disadvantage: reduction of output voltage by the amount of 0.5V drop Sense the temperature of the chip and turn on a transistor above the preset temperature and absorb the bias current of the circuit Zener diode: positive TC VBE1:negative TC As T increases, the emitter voltage of Q1 rises which in turn raises the base voltage of Q2 Q2 turn-on

Short circuit protection

Thermal shutdown circuit

Homework
1,4,14,15,16,19,24,30,37,38