Outline

Modeling of Spatially Distributed „ Why is it so difficult to design and model

Microwave Circuits circuits with spatially distributed elements
„ Revisit circuit and network theory
Michael Steer1 „ Revisit the concept of ground
Circuit Theory for Spatially Distributed Systems
Andreas Cangellaris2 „
„

Research tools that address spatially

1 2 distributed circuits
Department of Electrical and Department of Electrical and
„ Examples (throughout)
Computer Engineering Computer Engineering „ Opto Electronic Modeling
North Carolina State University University of Illinois, Urbana „ On-Chip Supply/Ground Modeling
Raleigh, North Carolina Champaign
USA, 27695 Urbana Champaign, Illinois
m.b.steer@ieee.org USA, 61801
cangella@uiuc.edu
IMS2005
Workshop WFG: REDISCOVERING CIRCUIT DESIGN TECHNIQUES FOR MICROWAVE COMPONENTS,
CIRCUITS AND SUBSYSTEMS: THE EFFICIENCY AND POWER OF EM/CIRCUIT CODESIGN

Mixed Signal System Motivation

Many HARD
Only really have good EDA MICROWAVE Reflector

solutions for digital.

(distributed)
modeling VCSEL

problems: Lens

DIGITAL ANALOG
RF
PACKAGE Is there a common VCSEL Modeling with Optical Feedback
(feedback) (distributed)
(no feedback)
solution strategy?
YES! = Local Reference Terminals

RF design is difficult as EDA cannot

S G D
be used EDA to determine the OPTICAL
MECHANICAL

system performance measures..

To streamline design we must

revolutionize our ability to predict Delay Active Antennas
system performance.
 Courtesy
Rockwell
Background Reading
Science Center

Where is ground?

A fundamental
consideration in
handling spatially
distributed circuits.

Circuits (conventionally) have a single ground.

Background Reading Microstrip Model

„ In a Field Simulator Voltages Are Determined By
Integrating The Electric Field Along a Path
„ In Microstrip Problems the Field is Integrated Over
The Paths Shown to Obtain V
„ The Path of Integration Matters
The Dashed Path Yields a Different Value of V2

V
1

V
2

Not the same

point electrically.
 Local reference terminal concept
Microstrip Model „ This avoids non-physical connections and therefore is
fundamental for the analysis of spatially distributed
circuits as well as for simultaneous thermal-electrical
simulations.
V1 V2
REF REF V1 V2
REF REF

V1 V2 LOCAL REFERENCE
REF REF TERMINAL

Network Model:
⎡ S11 S12 ⎤ But a (SPICE) Circuit How to extend this beyond two terminal ports?
⎢S ⎥ does not have two
⎣ 21 S 22 ⎦ reference terminals.

Modeling a Transformer Modeling Transformer Network

IN SPICE
IDEAL IDEAL Or your
TRANSFORMER TRANSFORMERS Favorite simulator
NO BETTER
TWO LOCAL
REFERENCE
NODES

1 MΩ
IN SPICE =
Or your
Favorite simulator
OR

= 1 MΩ
Modeling Transformer Network Local reference node concept
„ This avoids non-physical connections and therefore is
Local Reference Group Concept fundamental for the analysis of spatially distributed
circuits as well as for simultaneous thermal-electrical
simulations.

Really need simulator

support for multiple
‘grounds’
V1 V2
i.e. local reference REF REF
terminals

LOCAL REFERENCE
TERMINAL i1 i2

Our common view of a port

1 2
is that it has two terminals i1 i2

How to extend this beyond two terminal ports?

= Local Reference Terminal

Spatially Distributed Modeling KEY CONCEPT:

LOCAL
Quasi-Optical Amplifier
REFERENCE
TERMINAL

Kunisch and Wolff

(preliminary concept)
Khalil and Steer
(full concept)

KCL applies to
this local
reference group
This is a multi terminal port!
 Nodal Admittance Matrix
Determination
Nodal Admittance Description Required in Microwave Circuit Simulators
Process: Guess a node voltage and calculate node current.
LOCAL
Locally REFERENCE
NODE
Reference
Group
(Single Local
Reference
Terminal)

Using MOM model to develop model of spatially distributed system.

Grid Amplifier (Spatial Power Combiner) Things learnt when it is done right.
It is important to do circuit/field co-simulation Role of Symmetry
More accurate.
Uncover unexpected physics.

Comparison of measured and simulated results.

BEAM
CENTER
BEAM
CENTER

Symmetry
Broken
BEAM
Full linear + CENTER
nonlinear
simulation with
integrated
field solution
Things learnt when it is done right. Symmetry Lessons Learnt
Role of Symmetry

GRID SYMMETRY CIRCUIT SYMMETRY

BEAM CENTER

HORIZONTAL AXIS VERTICAL AXIS NORMAL AXIS OF

OF LINEAR OF LINEAR CIRCULAR
SYMMETRY SYMMETRY SYMMETRY

The grid symmetry and circuit symmetry are fundamentally incompatible.

Symmetry Effects
Modeling Concept

SPATIALLY
NO PLANE OF LINEAR NONLINEAR
DISTRIBUTED
SYMMETRY CIRCUIT NETWORK
CIRCUIT

NO POINT OF
SYMMETRY

LINEAR
LINEAR
CIRCUIT NETWORK THERMAL
NETWORK

+ Optoelectronic + Any other physics

Incorporate using locally referenced groups.
 EM-PDK (Em-Aware Process Design Kit) ELECTRIC
LAYOUT
EM-PDK G2M

Layout Parasitic MESH Commercial

GENERATION
Extractor MESHER
Mixed
Layout
ElectricTM
DC2LIGHT UIUC2D
EM – Aware MACROMODEL
Technology file
NETLIST
SIMULATION S2IBIS
fREEDA® R,L,C,G

SCHEMATIC
Integrating Electric & EM-PDK
PRIME
EM-PDK (Java) is both a stand alone program and integrated into Electric.
⎛ a ai ⎞
STAND ALONE MODE: Y( s) = G 0 + sC 0 + ∑ ⎜⎜ i + ⎟G i
i ⎝ s − pi s − pi ⎟⎠
PARSES A LAYOUT FILE AND EXTRACTS EM FEATURES, EM_Aware,
CREATES CIF OUTPUT. (METALS, DIELECTRICS THICKNESSES AND
PROPERTIES ONLY). PASS TO EM SIMULATOR. +
ELECTRIC MODE - f REEDA
IDENTIFIES LOCAL REFERENCE GROUPS AND ASSIGNS LOCAL CIRCUIT
L L SIMULATION
REFERENCE TERMINALS. ASSIGNS TERMINAL NUMBERS.
CREATES SPICE FILE + EM-Aware LAYOUT FILE

Electric (Editor) EM-fREEDA-Spice Interface

ƒ Handles MOS-Bipolar Step 1. Foster’s model fit to simulated or measured frequency data.
Coupled Inductors
ƒ Handles MOS-Bipolar
ƒ Schematics, HDLs GO TO fREEDA directly
ƒ Common Layout-Schematic Interface Step 2. Synthesize R, L, C, K subcircuit (many elements)
ƒ Supports CIF, GDS II, GO TO Spice
Why Foster’s model ?
ƒ VHDL, Verilog etc..
ƒ Custom IC layout tool. ¾ It is a convenient method that facilitates the direct
synthesis of an equivalent circuit representation of
the power distribution network.
NCSU MILESTONE
¾ Further this method is guaranteed to be causal and
Modifications made to include circumvents the problem of implementing reduced
naming of nodes at points of order models with problems concerning stability (AWE
method), aliasing (Convolution based on Impulse
connection between schematic and response) and series approximations problem (Numeri-
layout. cal Inversion of Laplace Transform Technique).
Support for materials properties • Layer Thickness. Foster’s canonical representation :
added. m m
• Loss Tangent.
Modifications to be included in next H(s) = ∑ kj + ∑ aj + aj* Indicates
release of Electric Editor. • Dielectric Constant. j =1 s – pj j =1 s – pj s – pj*
LRT
where kj /(s-pj) represents the real pole and
aj/(s-pj) and aj*/(s-pj*) together represents the complex conjugate pair
EM-fREEDA Interface Multigrid-Enhanced EM Modeling of the
N-Port Foster Model Power Grid On Chip
„ Maxwell equation’s-based modeling
PORT 1 o
LRG 1
o „ Finite Volume model
PORT2

LRG 2
o „ Key Attributes
o Foster N – Terminal „ Model developed directly from physical structure
The transfer function is
Network
given as, „ Cumbersome and error-prone extraction of [L] and [C]
avoided
I(s) = H(s)V(s) „ Rigorous modeling of electromagnetic effects
„ In addition to power switching noise analysis it
PORT N
LRG N
o
enables prediction of power grid-induced EMI
o
between different blocks on the chip

FV-Based Modeling Methodology Implementation of Variable-Size Grid

Finite-volume discretization of Maxwell’s equations
K K d K K Ez

v∫ C
E ⋅ dl = − ∫∫ µ H ⋅ dS
Ex Hz

F dt SF Ey
K K d K K K K z

v∫ C A ⋅ =
dt ∫∫ S A
ε ⋅ + ∫∫S A ⋅ dS
σ Hy
H dl E dS E
Fine Grid
y
Coarse
(a) Grid
„ Micron-size cross-sectional dimensions and regular
layout of the grid exploited to contain model complexity „ The choice of grid coarseness is
„ Grid size of the order of grid feature size
„ Assignment of unknown electric & magnetic fields in space dependent on the simulation objective and
dictated by the electromagnetic effects that must be captured
for accurate simulation the desired accuracy.
„ Ohmic loss in the wires
„ Inductive effects during switching
„ Switching noise simulation only: Coarse grid
„ Capacitive coupling and common impedance coupling for „ Power grid-induced interference: Finer grid
grid-induced interference calculation
Compatibility with SPICE “Cartoon” of the On-Chip Grid
The state-space form of the discrete model,

⎡G Dh ⎤ ⎡ e ⎤ ⎡ C 0 ⎤ d ⎡ e ⎤ ⎡ i S ⎤
⎢D +
R ⎥⎦ ⎢⎣h ⎥⎦ ⎢⎣ 0 L ⎥⎦ dt ⎢⎣ h ⎥⎦ ⎢⎣ v S ⎥⎦
=
⎣ e

is of the same form with the MNA formalism used in SPICE

Hence, it facilitates direct incorporation of lumped circuits
and behavioral models for drivers and receivers
„ e , h : the discrete unknown fields
„ G, R, L, C, Dh, De : sparse matrices (dependent on material and
geometric properties of the structure)
„ iS, vS : voltage & current sources connected to the grid

Top view of Metal-1 Layer Additional Features of Solver

„ Convenient interface to models for the off-
Inverter Model
chip power grid
„ Can be incorporated either in terms of SPICE
net lists or in terms of a matrix rational
function representation of their multi-port form
„ Modeling of the semiconductor substrate
Si Substrate
„ Effected through position- and frequency-
dependent surface impedance relationships
cast in terms of rational functions
Impact of semiconductor substrate Impact of semiconductor substrate…
on power grid switching response 1.6
Case0
1.4 Case1
Case2
z 1.2 Gate Input
t3 SiO2 ε3 , µ3=µ 0 , σ3= 0
y 1
x
t2 p- epitaxy ε2 , µ2=µ 0 , σ2≠ 0
0.8

Voltage (V)
ε1 , µ1=µ 0 , σ1≠ 0 0.6 Suppressed overshoot and
t1 p+ bulk
oscillation
0.4

0.2

Case 0: Semiconductor substrate modeled as PEC 0

Case 1: t1 = 198 µm, σ1 = 104 S/m, t2 = 2 µm, and σ2 = 10 S/m
Case 2: t1 = 200 µm, σ1 = 104 S/m, t2 = 0 (no epi) -0.2

-0.4
0 50 100 150 200 250 300
Time (ps)

Transient EM Modeling of Transient EM Modeling of

Power Switching Power Switching
Visualization of on-chip supply voltage disturbance Visualization of on-chip supply voltage disturbance
during simultaneous switching at all nodes during switching of drivers in central region only
 Modeling of Substrate Noise Summary
Volts Simulation Experiment
Volts
0 0
Buffer -0.5 „ On-Chip Power Grid Transient Simulator
Output
-1 „ Electromagnetic rigor
-1.5
-1.8 „ Comprehensive modeling
Millivolts -2
Millivolts „ Includes impact of semiconductor substrate
-20 20
0
-40 Sensor -20
„ SPICE Compatible
Output -40 „ Direct implementation of SPICE models for non-linear
-60 -60
-80 drivers, decoupling caps, etc…
-100 „ Supports convenient interfacing with models for the off-chip
1 1.4 1.8 2.2 2.6 3 1 1.4 1.8 2.2 2.6 3
Time (µs) Time (µs) power distribution network

Long interconnect „ Supports both simultaneous switching noise and

Distributed
from buffer output to
Noise Injector power grid-induced interference prediction
pad: Its coupling to Noise
substrate critical for
injector Noise
accurate prediction of sensor
substrate-induced
noise

Optoelectronic Modeling P-contact

VCSEL
VCSEL

GaAs
VCSEL Feedback Results:
Feedback Modeling: AlA
„ Power and Wavelength degradation due to two components
s
AlAs
Oxide

Optical Component Feedback: In0.2Ga0.8As

f1=12mm, R=0.04 f2=12mm, R=0.04

„ Optical systems have reflective surfaces GaAs

„ Small feedback can effect laser dynamics

„ Optical component reflection study is important Al0.8Ga0.2As
Detector
„ fREEDA enables component reflection modeling Vcsel
Lens1 Lens2

Modeling Approach: N-contact z=12mm z=12mm

Optical Power Wavelength
„ Calculate resultant field at each component Output power
degradation due
„ Back propagate the resultant field to laser to single and
Laser No feedback No feedback
output double lens feedback
sensitive to
feedback
phase L1 feedback L1 feedback

Output wavelength
VCSEL Detector degradation due
L1+L2 feedback
to single and
double lens feedback L1+L2 feedback
Nonlinear Electro-Thermal Element
Nonlinear Electro-Thermal Element
NONLINEAR ELECTRO-THERMAL
i LINEAR ELEMENT
ELECTRICAL i = f(x1,x2) ELECTRICAL
v i
COMPONENT v= g(x1,x2) NETWORK LINEAR
ELECTRICAL i = f(x1,x2) ELECTRICAL
v
T= x2 v,i COMPONENT v= g(x1,x2) NETWORK
h
THERMAL THERMAL T= x2 v,i
COMPONENT h(t)=h(v(t),i(t)) T NETWORK h
THERMAL THERMAL
COMPONENT h(t)=h(v(t),i(t)) T NETWORK
THERMAL GROUND (0 K)

THERMAL GROUND (0 K)

Time Delays fREEDA Multiphysics Simulator

Spice handles only short (< 3 time step) time delays.

TWTA used to validated fREEDA’s

10
4

„ Product: fREEDA REQUIREMENTS FOR FIRST PASS DESIGNS:

A Rapid development of models
ability to handle models with long 10
3 B 140 dB dynamic range required
C Integration of tools. (new concepts for mixed
Observed delay (ns)

time delays. Also implemented in digital/analog simulation; transmission lines in

2

many transistor models. 10

transient simulators)
D Achieve 1 or 2 fab cycles (need exact emulation)
1
10

Validation in Progress STATE-OF-THE-ART AT START OF PROGRAM:

10
0
0 1 2 3 4
A Limited ability to model new devices
10 10 10 10 10
Specified delay (ns) B Inadequate dynamic range 40–60 dB
Input Terminal Voltage (volts)

1 C Many unconnected EDA tools

0.5 D NRE for a mixed signal chip $50M + 2 years
0
Extracted amplitude and time-delay (Bluetooth/802.11 complexity, 8–20 fab cycles)
-0.5 parameters for in-band linear and non-
-1 linear (3,5,7th order) from 8510C
0 2000 4000 6000 8000 10000 12000 14000
TECHNOLOGIES DEVELOPED
Time (ps)
measurements of an HP 495A TWTA. A Rapid development of models (completed)
Output Terminal Voltage (volts)

3
2 Created TWTA model using 4 instances (6 days versus 1 year in spice, e.g. BSIM3SOIv3 )
1
of Vccsd with extracted parameters. B 140 dB dynamic range required to determine actual
0
performance (achieved 160 dB)
-1
Voltage gain ~10, transit time ~10.5 C Proven distributed circuit concepts: True time delay for the
-2
-3
0 2000 4000 6000 8000 10000 12000 14000
nsec reflect well in simulated results. first time; multiphysics/multiscale environment.
Time (ps)
(Sinusoidal input at 7.5 GHz.) D Experimental validation of precise simulations.
Major features Accessibility
Feature Initial State Goal Achieved
of The Art
fREEDA runs on all Linux and cygwin
Dynamic 40–60 dB SPICE 140 dB 160 dB flavors
Range > 120 dB ADS

Multi Limited Thermal / Thermal / Can be downloaded as a single executable

on windows (16 MB)
Physics EM / Circuit EM / Circuit (Must first install cygwin)
Time Delay 2 or 3 time Unlimited Unlimited
steps Improved Documentation (on line)

www.freeda.org

Transient Dynamic Range

0.05
Time Delays
(Defined as the detection of a Spice handles only short (< 4 time step) time delays.
SPICE (UCB)
small signal in the presence of a fREEDA has no limit
0.04 Algorithm 10
4

large signal.)
TWTA used to validated fREEDA’s
X-band MMIC 10
3

ability to handle models with long

160 dB

Observed delay (ns)

Primarily achieved through time delays. Also implemented in 10
2

• better error estimation 0.03 many transistor models.

• better time point selection

Input Terminal Voltage (volts)

1
1
Error 40 dB line
10

0.5
0

0.02 0
10
10
0
10
1
10
2 3
10
4
10

CONVENTIONAL Specified delay (ns)

Result from -0.5

Error Backward -1
Euler 0 2000 4000 6000 8000 10000 12000 14000
estimate Time (ps)

Output Terminal Voltage (volts)

0.01 3
IDEAL 2
RESULT Result from trapezoidal
1 1 ns
NEW 0
-1

0 -2
0 0.002 0.004 0.006 0.008 0.01 -3
0 2000 4000 6000 8000 10000 12000 14000

Tn+1
Tolerance Time (ps)
Tn-1 Tn
Products Conclusions
Delivery of best in class software tools: (beta release)
„
„ fREEDA
„ New Circuit Concept
„ High dynamic range multi physics circuit simulator
„ Easy development of advanced device models
„ Now available as single binary for Windows (16 MB)
„ S2IBIS3
„ Digital macromodeling tool
„ EMPDK
„ Em-Aware physical design kit tool (JAVA)
V1 V2
„ (Can also be run in conjunction with Electric Editor) REF REF
„ UIUC2D
„ EM modeling tool for 2D geometries
„ ICWAVE
„ On chip, comprehensive, 3D EM modeling LOCAL REFERENCE
„ PRIME
TERMINAL i1 i2
„ EM reduced Order Model macromodeler tool (Foster Model)
„ Directly interfaces with fREEDA Our common view of a port
1 2
„ Synthesizes R, L, C, K models for Spice.
is that it has two terminals i1 i2
All packages can be accessed through http://www.freeda.org
PRIME and UIUC2D http://alpha1.ece.uiuc.edu/download
For PRIME: username: prime pwd: fitting How to extend this beyond two terminal ports?
For UIUC2D: username: uiuc2d pwd: rlcgsyn
For ICWAVE Contact Andreas Cangellaris

Acknowledgements
„ UIUC TEAM „ NCSU TEAM
„ Integral Equation Solvers „ Simulator „ EM-Circuit
„ V. Okhmatovski „ C. Christofferson Integration
„ A. Rong „ S. Luniya „ M. Abdullah
„ S. Wang „ A. Khalil
„ J. Morsey
„ S. Skaggs „ J. Patwardhan
„ V. Kourkoulos
„ F. Hart „ S. Nakazawa
„ FEM Solvers „ M. Basel „ C. Hicks
„ T. Yioultsis „ C.-R. Chang „ U. Mughal
„ L. Proekt (Post-doc) „ P. Heron „ T. Nuteson
„ Model Order Reduction „ W. Kanj „ M. Summers
„ T. Yioultsis „ G. Rhyne „ R. Mohan
„ J. Morsey „ R. Bollapragada
„ S. Uppathil
„ B. Biswas
„ Modeling
Sponsors:
„ N. Kriplani
DARPA „ S. Velu
Army Research Office „ H. Guiterrez
„ W. Jang