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Multirate hierarchical time integration for electronic circuits

J. ter Maten 1,2 , A. Verhoeven2 , A. El Guennouni1 , and Th. Beelen1
1
Philips Electronics Nederland B.V., Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands
2
Eindhoven University of Technology, Den Dolech 2, 5600 MB Eindhoven, The Netherlands

Electrical circuits are hierarchically defined, in which electrical components are combined with submodels. These last ones
may contain submodels themselves. This construction gives options for dedicated time integration procedures. We describe an
extension that allows for a dynamically partitioned multirate time integration that retains a number of hierarchical efficiencies.
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1 Time integration of hierarchical circuits

By Nodal Analysis a network description of an electric circuit gives rise to an implicit system of differential-algebraic equa-
tions (DAEs)
d
[q(t; x)℄ + j(t; x) = 0 (1)
dt

in which the unknown x contains the nodal voltages. The equations for the nodal voltages are current contributions that sum
up to zero (Kirchhoff Current Law, KCL) at each node. In the above, effects due to capacitors can be described by q, while
resistors and current sources are described by j. To be able to deal with voltage-defined components the set of unknowns
is extended with the currents through these components. The additional voltage-jump equations for these current unknowns
describe these last ones implicitly. These equations satisfy Kirchoff Voltage Law. The modeling of inductors requires proper
definitions for both functions q and j.
In fact q (and similarly j) is obtained from summing up local elementwise contributions qe that use local operators BeT , to
select (extract) the specific unknowns, and Ae to add (store) the results to the proper equations
X
q(t; x) = Ae qe (t; BeT x): (2)
e

In fact, each contribution is a very sparse one, and ususally Ae = Be . For instance, a capacitor, based on qe = C1 v , with
v = x1 x2 , gives rise to C1 e1;2 eT1;2 x, where e1;2 = e1 e2 . For controlled elements one may have Ae 6= Be .
The same mechanism can be generalized to deal with hierarchically defined circuits. It allows for a domain-decomposition.
Consider a super-circuit that contains j submodels, each with unknowns x(j ) . We write
   
y(j ) 0
x (j )
= + (3)
0 z(j )
in which y(j ) and z(j ) represents the terminals and the internal unknowns. An essential well-posedness condition is that
the system of equations provides a procedure such that z(j ) = g(j ) (y(j ) ). For identifying y(j ) with nodes xsuper;(j ) at the
super-circuit level we introduce

Bj (i; k ) =
1 if unknown k sub  i
super
(4)
0 else

Then: xsuper;(j ) = Bj y(j ) and y(j ) = BjT xsuper;(j ) . In fact also the super-circuit has a sub-model like form: here the ground
node acts as terminal. The equations (1) can be written as

d X N
X
N
d
0 = Bj q(j ) (t; x(j ) ) + Bj j(j ) (t; x(j ) ) + qsuper (t; x) + jsuper (t; x)
dt dt
j =1 j =1

y (j )
=
T
Bj x super;(j )

z (j )
= g (j )
(y
(j )
)

The DAE-nature and the consequences for the solutions are described in more detail in [4]. For the impact of topology see [6].
Usually these equations are integrated by applying BDF time integration methods. In each step a Newton method is used to
 Corresponding author: e-mail: Jan.ter.Maten@philips.com

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solve the non-linear system of equations. Gaussian elimination allows for an hierarchical-friendly Newton procedure using
recursions. The first hierarchical recursion is a bottom-up procedure for the equation and matrix assembly process. In the same
procedure also a partial matrix decomposition is made after which the partial Schur components for the terminal unknowns
are added to the next higher level. Finally a top-down recursion extracts the internal unknowns from the terminal ones [1].
The hierarchical time integration procedure allows for: (i) Bypassing in Newton; (ii) Bypassing in time when terminals are
not changing much. The procedure also allows for a safe multirate time integration procedure.

2 Multirate time integration of hierarchical circuits

In [2, 5] multirate methods based on BDF-methods were introduced. In [3, 7, 8] their application for electronic circuits is
described.
-s
 s
s
tn+q tn+q

H L A
s
s
s tn+1

s s  h
tn
xL 6 xA tn

interface

We assume a domain partitioning in a latent part of an electrical circuit (L), on which a large time step H can be used, and a
neighbouring, active, area (A) where a smaller time step h has to be used. For simplicity we even let L and A be submodels.
At the interface between L and A, the time integration on the active part A requires a proper contribution from the latent part
L. Because the interface is along a submodel we can speak of the value of the terminal current that is needed to complete
the KCL-equation. To compute this, in general, its assembly may require a hierarchical recursion through the latent part (the
terminal of L may also be a common terminal in a hierarchical sequence of submodels) [1]. To overcome this procedure we
propose to enlarge the number of terminals of a submodel by adding extra ones representing unknowns for terminal currents.
Assuming that the boundaries of the submodels are relatively small compared to the internal parts, we only slightly increase
the number of unknowns in the new approach. The benefit comes from the fact that now time integration of the active part
does not require evaluation within the latent part: one can just interpolate the terminal current unknowns.
This procedure allows for a dynamically partitioned multirate procedure in which each active part is slightly enlarged to fit a
submodel. For instance, for a chain of models the activeness can be followed through time. In addition all traditional hierar-
chical bypass options are conserved. We finally remark that the well-posedness assumption on the submodels automatically
guarantees that the active part can be uniquely derived from the values at the terminals – for more general partitions this
property should have to be checked (especially because of the equations being DAEs).

References
[1] J.G. Fijnvandraat, S.H.M.J. Houben, E.J.W. ter Maten, J.M.F. Peters: Time domain analog circuit simulation, To appear in: Journal of
Computational and Applied Mathematics, 2005.
[2] C.W. Gear, D.R. Wells: Multirate linear multistep methods, BIT, 24 (1984), 484-502.
[3] A. El Guennouni, A. Verhoeven, E.J.W. ter Maten, T.G.J. Beelen: Aspects of Multirate Time Integration Methods in Circuit Simulation
Problems, To appear in Proc. ECMI-2004 (Eindhoven, The Netherlands), Springer Verlag.
[4] M. Günther, U. Feldmann, J. ter Maten: Modelling and discretization of circuit problems, In W.H.A. Schilders, E.J.W. ter Maten (Eds):
Handbook of Numerical Analysis, Vol. XIII: Special Volume on Numerical Methods in Electromagnetics, Elsevier North Holland,
pp. 523-659, 2005.
[5] S. Skelboe, P.U. Andersen: Stability properties of backward Euler multirate formulas, SIAM J. Sci. Stat. Comput., Vol.10-5, pp. 1000-
1009, 1989.
[6] C. Tischendorf: Topological index calculation of DAEs in circuit simulation, Surveys Math. Industry, Vol. 8 (3-4), pp. 187-199, 1999.
[7] A. Verhoeven, A. El Guennouni, E.J.W. ter Maten, R.M.M. Mattheij: A general compound multirate method for circuit simulation
problems, To appear in Proc. SCEE-2004 (Capo D’Orlando, Sicily, Italy), Springer Verlag.
[8] A. Verhoeven, A. El Guennouni, E.J.W. ter Maten, R.M.M. Mattheij: Multirate methods for the transient analysis of electrical circuits,
Presented at GAMM-2005, Luxembourg, 28 March - 1 April 2004.

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