ECE 124A

VLSI Principles
Lecture 3
Prof. Kaustav Banerjee Electrical and Computer Engineering E-mail: kaustav@ece.ucsb.edu @

1 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

NOR Gate

2 PMOS must be in series.. 2 NMOS must be in parallel.

2 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

CMOS NOR Implementation

3 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

CMOS 3-input NOR Implementation 3-

4 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

Combinational Logic

Output state X should always be avoided: static power

Output state Z is of relevance in certain gates such as multiplexers

5 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

Compound Gates
Y= A.B + C.D Needs 20 transistors.

6 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

Compound Gates

Y= A.B + C.D

Pull-down (when is Y =0?)

Pull-up (when is Y=1?)

Need 8 transistors
7 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

Compound Gates

8 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

Pass Transistors

9 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

Transmission Gates: Pass Transistors in Parallel

Both 0 and 1 passed strongly

s s

Double Rail Logic: both the control input and its complement is required

10 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

Tristate Buffer

11 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

Tristate Buffer

12 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

Transmission Gate as Tristate Buffer

Non restoring: Non-restoring: input-signal will slowly degrade over a number of stages

13 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

Tristate Buffer as Inverter

Restoring: O/P is directly connected to Vdd or GND

14 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

Multiplexer (MUX)
Connects one of n inputs to the output. Used as data selectorsencoders

2:1 MUX 21 A Y
1 output

4:1 MUX A 22 B inputs C D

s1 s2

inputsB

2 Select signals

1 Select signal

Y = As +Bs

Y = As1s2 + +Bs1s2 + Cs1s2 + Ds1s2

In general, 2n inputs will have n select signals

Y mk I k
k 0

2n 1

mk is a minterm of the n control variable and Ik is the corresponding data input 15

Lecture 3, ECE 124A, VLSI Principles

Kaustav Banerjee

Multiplexer (MUX)

Y = D1.S +D0.S

16 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

NonNon-restoring MUX
Y = D1.S +D0.S

17 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

Inverting and Restoring MUX

S/S = 0/1
Y = D1.S +D0 S D1 S +D0.S

D0 = 0 Y =1=D0 0: 1 D0

18 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

A 4:1 MUX

Using three 2:1 MUXs

19 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

Stat c C OS Su a y Static CMOS Summary

In static circuits at every point in time (except when switching) p the output is connected to either GND or VDD via a low resistance path.
fan-in of n (or n-inputs) requires 2n (n N-type + n P-type) devices

Non ratioed Non-ratioed logic: gates operate independent of PMOS or NMOS sizes (since no conflict between pull-up and pull-down networks) No path ever exists between Vdd and GND: low static p p power Fully-restored logic: (NMOS passes 0 only and PMOS passes 1 only Gates must be INVERTING: Y = X so that X=1 (NMOS pullX, pull down network is ON) for Y=0 (node is fully discharged)

20 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

Latches atc es

CLK=1: D to Q CLK=0:Holds state of Q

As long as CLK remains high: D to Q g

21 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee

Flip- ops Flip-Flops p

Combines two latches: One O +ve sensitive (slave) and one ve iti ( l ) d sensitive latch (master) Edge Triggered FF or Master-Slave FF Master
QM

Slave

CLK=0: D to QM QM = D
QM

Slave holds previous value of Q

CLK=1: master cant sample input and holds value of D Slave opens and QM=(D) =Q
22 Lecture 3, ECE 124A, VLSI Principles Kaustav Banerjee