Low Cost Technology for Transmit Receive Modules

G. D. Morrison, A. D. McLachlan & A. M. Kinghorn Selex Galileo Crewe Toll, Edinburgh EH5 2XS, United Kingdom.
Abstract The growing maturity of ESCAN radar for airborne applications calls for greater emphasis on cost-effective packaging in the active antenna. An attractive solution is to distribute the TRM components across a multi-channel PCB, adopting commercial assembly techniques where possible. Component design, PCB structure and antenna layout are key enablers of low cost manufacture. Keywords TR module; ESCAN antenna; RF packaging; chipin-board; design for manufacture.

to enclose more than a single circuit, so many costly modules are needed in a typical antenna. Furthermore, the expansion mismatch with the parent structure or motherboard inevitably calls for compliant interfaces such as mating connectors, which again add complexity and cost. A radical and attractive alternative is to dispense with the local ceramic substrate and its associated enclosure, and instead to mount the components individually on the antenna motherboard. This eliminates the relatively expensive and massive substrate-package combination, and incidentally can allow a closer spacing of the TR channels and hence higher operating frequency. At the same time, the PCB can now incorporate in a single entity the functions of control circuit, RF manifold and radiating elements. B. Implementations Various approaches are possible to the distribution of TRM components over an organic PCB. In the chip-in-board approach, the bare semiconductor dice are mounted directly in or on the multilayer board, with wire bonds being formed between the chip surface and the surrounding copper lands. If necessary, local covers can then be added as protection or shielding for the dice. An alternative implementation is to mount the dice in flip-chip format, though this technique is limited to the intermediate layers of the PCB. As chip-in-board is one of the more unorthodox solutions, it is treated here in some depth, but many of the observations are also applicable to other implementations. III. PCB CONSTRUCTION & MATERIALS

I.

INTRODUCTION

The operational benefits of an electronically scanned (ESCAN) radar antenna have been confirmed in several demonstrator programmes. For radar manufacturers the challenge now is to market this technology at a price comparable to existing mechanically scanned radars, while also satisfying the desire for greater functionality and reduced mass. Given the downward trend in gallium arsenide component cost, attention is increasingly directed at the packaging of the active devices and at the effort of integrating the antenna. In particular, there is a growing recognition that antenna cost can be reduced significantly by abandoning individually housed TR modules in favour of distributed assemblies, in which the components of multiple channels are mounted directly on a multilayer printed circuit board. Accordingly, in this paper the feasibility is discussed of applying commercial surface-mount and chip-in-board technology to airborne ESCAN radar antennas. II. DISTRIBUTED TR CIRCUITS

A. Concept With current semiconductor technology it is difficult to realise a complete transmit-receive circuit in a single integrated circuit. Instead the digital circuit, vector-control function, LNA and HPA typically call for a diversity of silicon, GaAs and perhaps GaN components, and these are usually mounted on a ceramic substrate that provides interconnexion while also lending itself to hermetic sealing. For thermomechanical reasons such sealed ceramic packages are seldom large enough

When DC and RF signals are to be combined within a single multilayer PCB, there is merit in choosing a stripline configuration for the RF transmission line. This inherently affords better shielding than open microstrip, and allows the DC layers to overlie the RF. Although it is generally desirable to minimise the overall thickness of the PCB, thin triplate dielectric layers effectively increase the line loss, because the contribution of copper and bonding film becomes dominant. Thus, where the antenna layout calls for transmission lines more than a few centimetres long, the triplate should be at least 1mm thick. Figure 1 shows a typical PCB cross-section.

A further attraction of the distributed approach is the possibility of integrating the radiating element within the PCB, in the form of printed structures such as a Vivaldi taper or a dipole. This eliminates the potential mismatch and insertion loss of conventional connectors, and also opens the interesting prospect of exploiting HPA or LNA devices that have impedances other than the conventional 50 ohms. It is possible to procure the PCB dielectric already bonded to a thick metal backing plate, but in forming ground vias it will then be necessary to penetrate this plate and connect to it. Where the material is aluminium this calls for zincating or similar treatments, and the minimum attainable via diameter may be objectionably large. On the other hand, the bonding of a previously fabricated board to a separate heat exchanger is compatible with standard PCB processes and design rules. IV. ACTIVE TRM COMPONENTS

Figure 1. Typical Multilayer PCB with Die Well

At the edge of the die-well, a discontinuity inevitably arises where the stripline emerges into open microstrip, and this effect is exacerbated in manufacture if the step in track width does not correspond accurately with the edge of the well. As a mitigation, the classical stripline structure (Dimension a = Dimension b) may be replaced with asymmetrical triplate or buried microstrip, where a >>b. The field distribution in the buried transmission line now resembles that in the open area, lessening the likelihood of a poor match. These stripline structures all need judicious and plentiful vias between the upper and lower ground planes, and call for an appropriate RF connector at the edge of the PCB. In a thick stripline board (a+b 1mm) with low dielectric constant, the insertion loss is largely dictated by the tan of the PCB material. PTFE composites (tan 0.001) are unsurpassed in this respect, but they call for special metallising and lamination processes on account of their low chemical reactivity and moreover exhibit poor mechanical properties. An attractive alternative is a glass-reinforced polyolefin such as Rogers 4000 series, which can be processed in much the same way as conventional glass-epoxide material while still having lower loss (tan 0.003) than FR4 or polyimide. At 10GHz the stripline loss is typically 10dB/m as opposed to 7dB/m for the same dimensions in PTFE. Where multiple TR channels are distributed over a single PCB, it is convenient to include the RF manifold within the same board. This is often implemented as a network of Wilkinson couplers, with a 100 ohm resistor at each split. Surface-mounting of these resistors occupies valuable board area, while burying the chips is a specialised and potentially inconsistent procedure. A cost-effective alternative is to form the resistors directly on the stripline layer, in a single operation during manufacture of the PCB. This is done either by photoetching a previously deposited resistive foil, or by screen printing a resistive polymer ink. In order to minimise parasitic reactance the resistor size is always kept small (typically just 1 or 2 mm2, subject to power handling requirements), so the aspect ratio and hence resistance are very sensitive to small dimensional errors. Furthermore in the screen-printed case the resistor thickness too is process-dependent, and the overall imprecision can therefore be large. Careful tolerance analysis is needed, informed by process statistics, while the printing operation itself must be tightly controlled.

For vector control and amplification the authors have previously1 advocated a chipset that can be made on a highyielding commercial process with 6 minimum wafer diameter. This is conducive not only to consistent RF performance but also to low cost. Thermal resistance and parasitic reactance are minimised by mounting the active components as bare dice rather than in surface mounted packages. As in conventional TRMs, a high degree of semiconductor integration is favourable to the component count and space requirement, but a further advantage is the reduced number of wirebonds from chip to board and from chip to chip, with consequent improvement in manufacturing yield. For this reason it is advantageous to have a semiconductor process such as SiGe or enhancement-mode GaAs that can accommodate the serial-to-parallel control function within the MMIC while also providing both low noise figure in the receive path and good PAE in transmit. On the other hand, a very large die (TCE = 4ppm/K for SiGe and 6ppm/K for GaAs) is poorly expansion matched to the baseplate (TCE 23 ppm/K for typical aluminium alloys) so may not survive severe temperature cycling. A good compromise is to define the HPA as a separate die from the vector-control MMIC, and to mount it on an intermediate molybdenum carrier; as a further advantage, this sub-assembly can if necessary support fine-featured Lange couplers that cannot be realised in the main PCB, and it also permits largesignal testing before integration. To allow wire bonding to the chip component, ledges at one or two levels are provided at the edge of the die well, with gold-plated copper pads at the bond locations. As indicated in Figure 1, it may be convenient to dispose the RF and DC pads at different heights, corresponding to the tracking layers within the PCB, or alternatively all pads may sit on a single tier. In both cases two processes critical to success are the machining of the cavity and the control of lateral spread in the bonding films. Moreover, if the fabricated board is to be bonded to the baseplate it will usually be necessary to support the thin ledges of the PCB during that operation. Figure 2 shows a typical die well, in this case with bond pads on a single ledge around the chip aperture.

If in addition the top surface of the PCB is extensively metallised, the diffusion paths by which moisture reaches the cavity can be relatively long. Nevertheless, vulnerability to a moist environment is a perceived disadvantage of chip-inboard technology and it therefore deserves careful consideration. Diffusion of moisture from the atmosphere, in which the water concentration is [H2O]a, through a permeable wall, causes the internal concentration of water vapour [H2O]i to increase with time, t, such that [H2O] i / H2O] a = 1 exp(-t/).
Figure 2. Die Well with Wire Bonding Ledge

(1)

V.

DC & CONTROL FUNCTIONS

If the wall (in this case the PCB dielectric) is of thickness L and area A, and the cavity has volume V, then it can be shown2 that the time constant (which corresponds to 0.63 of the equilibrium concentration) is given by

While much of the DC and control functioning of the antenna can be subsumed in a small number of ASIC or FPGA components, there remains a rump of passive and discrete devices that are best procured in low-cost packages for surface mounting on the top surface of the PCB. These can be attached in a standard soldering operation before the bare dice are introduced. For example, Figure 3 shows a prototype transmitreceive channel realised with a combination of bare dice in cavities (lidded in this view) and standard surface-mounted DC components.

= VL/AP + L2/2D,

(2)

where D is the Fick diffusion coefficient and P is the permeability of the wall material. In the present case, where a small cavity is surrounded by relatively thick walls, it is the second term of (2) that dominates, so that wall thickness (i.e. the path length for diffusion) is the important characteristic, together with the diffusion coefficient. With realistic figures for path length (~10mm) and diffusion coefficient3 (~8x10-12m2/s), a time constant of the order of months is obtained. Accordingly, the exchange of moist air during operational altitude cycling (minutes or hours at altitude) is negligible. Of greater concern is the effect of prolonged storage in tropical conditions, which can be simulated experimentally by accelerated damp heat tests. In order to demonstrate the robustness of this technology, chip-in-board test pieces were populated with a silicon ASIC and a pHEMT GaAs chip set comprising vector-control MMIC, LNA and HPA, then wire-bonded and sealed. These test pieces were subjected to the following stresses.

Figure 3. Transmit-Receive Channel

Stress
ESS Temperature Cycle Damp Heat Altitude Vibration

Test Conditions
15 temp cycles & vibration. 500 cycles, -55 to +125C Voltage applied, but drain currents pinched off. 85C, 85%RH, 1000 hours. Voltage applied, but drain currents pinched off. 90 cycles, then additional 36 hour outgas at 65,000ft. Random 10Hz to 2000Hz; 0.04g2/Hz; 1 hour/axis.

Modern switch-mode power supplies are compact and have efficiencies well over 90%, allowing the necessary low voltages (typically -3V, +3V and +10V in the case of GaAs) to be provided locally within each antenna PCB. Combined with adequate power-plane provision within the multilayer PCB, this lessens the need for local charge storage, even when long transmit pulses must be sustained. The amount of tracking and hence the number of layers needed in the PCB depends on the scheme adopted for distributing beam-forming information to the individual TR channels. In particular, a series data bus is less demanding than the conventional star distribution, and should be considered in cases where the specified rate of update will allow it. VI. ENVIRONMENTAL PROTECTION

As indicated in Figure 1, environmental protection is provided by soldering or gluing a metal cover over the die well.

Subsequent successful electrical testing confirmed the ability of this construction to withstand a military airborne environment. In particular, the accelerated Damp Heat test had been reckoned equivalent to somewhere between 54 and 274 years of operation at 25C and 50% RH. Further protection can be afforded by specifying a benzocyclobutene (BCB) coating on the dice, often in combination with glob-top encapsulation. Alternatively, a zeolite getter can be printed

on the underside of the lid before sealing; in contact with water vapour this forms a hydrate stable up to approximately 150C, and thus serves to desiccate the cavity. VII. DESIGN FOR MANUFACTURE The full cost benefits of this technology can only be achieved if rigorous design for six-sigma (DFSS) is applied from the outset. This requires accurate information on the manufacturing yield and throughput of all proposed processes, such as component placement, wirebonding, and sealing, and it therefore entails close liaison with the manufacturing facility, typically through an Integrated Product Team. The first-time yield (FTY) and final yield are estimated from two numbers: firstly the defects per million opportunities (DPMO) of each assembly process and its associated equipment, and secondly the number of opportunities for defects, which is a function of the number of components and the interconnexion count. In the chip-and-wire approach, and assuming full robotic assembly, it is often the wire bonding process that largely determines FTY, hence the previously mentioned preference for highly integrated chip-sets and consequently reduced bond count. While optimisation of the bonding process and handling is essential, a further potential variable is the bond pad on the organic circuit board. Standard gold plating formulations that are specified for mated connectors are unsuitable for thermosonic wire bonding, while a further potential problem is contamination of the bond pad during lamination. Only through collaboration with the PCB manufacturer can these aspects be controlled. An important design decision is the number of TR channels to be embraced in the PCB, and this will be strongly influenced by the DFSS analysis and by the knowledge that rework may be uneconomical. These practical manufacturing considerations, no less than abstruse sub-arraying schemes, are likely to determine the optimum partitioning of a low-cost antenna. VIII. TEST Test strategy is crucial to the success of this approach, and must be applied coherently to the whole manufacturing sequence, from wafer fabrication through to calibration of the complete antenna. A distinct advantage of pre-packaged active components is the ease with which they can be tested after wirebonding and before mounting on the PCB. By contrast a die submitted to chip-in-board assembly must have been 100% screened at wafer level, as subsequent testing is impractical and replacement is costly. Again, a stable and high-yielding semiconductor process is mandatory.

Functional testing of the PCB assembly should preferably precede cavity sealing, and is facilitated by the provision of surface test points because so much of the circuitry is likely to be inaccessible. If, as described above, the RF manifold and the radiating elements are incorporated within the same board as the active circuits, it may be impossible to connect directly to the RF inputs and outputs of each TR circuit, and consideration should be given to including couplers within the PCB to facilitate such testing. Full characterisation of the TR circuits and of the antenna typically involves the exercise of several thousand possible gain-phase combinations at a number of frequency points, and may have to be performed over a range of temperatures. Once again, the earlier insistence on uniform components and tightly controlled manufacturing process will prove beneficial here, by allowing a reduction in the number states that must be 100% tested. Nevertheless, automated vector network analysers and RF switch matrices are essential if test is not to prove a bottleneck, and as a further challenge to the test engineer it may be necessary to access each TR circuit by through-space coupling, not through a conventional mating connector. IX. SUMMARY & CONCLUSIONS

Having secured access to commercial sources of active components, the radar manufacturer can combine these with a mixed DC-RF circuit board in order to achieve a cost effective ESCAN antenna. This may for example exploit non-hermetic packaging, which appears capable of withstanding harsh airborne conditions. From the outset the design must be optimised for automated manufacture, and this in turn calls for accurate knowledge of process capability. In this way it is becoming possible to extend the undoubted operational benefits of electronically scanned antenna technology to a wide range of radar users. ACKNOWLEDGMENTS The authors are grateful for the expert help and advice provided by Mr G Panaghiston of BAE SYSTEMS Advanced Technology Centre and Mr Robert Dry of Filtronic plc. REFERENCES
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