Teaching Material For

Microcomputers and Interfacing

Course code: ECEG-4501 Credit hrs: 3 ECTS Credits: 5
By
) r e r u t c e L t n a t s i s s 1 A ( 1 0 2 , y r a u r b e F

Teaching Material For

Microcomputers and Interfacing

Course code: ECEG-4501 Credit hrs: 3 ECTS Credits: 5
By
) r e r u t c e L t e r n a t i s i s s s A e u s 1 (

1 a

, s e u e

y s

r e

II

Acknowledgement
I am very much thankful to the Department of Electrical and Computer Engineering for allowing me to write a teaching material on Microcomputers and Interfacing. I am thankful to the reviewers for reviewing the teaching material. I am also very much thankful to my wife for encouraging me and assisting me to write this material. In addition, I would like to thank Mr. Muhammed and Mr. Alem who helped me in writing and editing this document and to Electrical and Computer Engineering Department students for their help in improvement of the material. Furthermore, I am thankful to all the staffs of Electrical and Computer Engineering Department for their help during the completion of this teaching material.

Author

III

Preface
This teaching material is prepared to serve as a valuable teaching material and study guide to the students of Electrical and Computer Engineering Department and to the Computer Engineering stream students in particular to support them in their self-study as well as it could also be used by practicing engineers and technicians. The purpose of this book is to give an in-depth study of both the hardware and software included in microcomputer systems. Although the concepts considered are general in nature, the discussion is based on a particular microprocessor, the Intel 8086, and its associated supporting devices and software. Of the more popular 16-bit single chip processors, the 8086 was chosen because it provides a varied instruction set that includes extensive arithmetic operations and string manipulations and has several advanced architectural features designed to support multiprocessing. It is assumed that the reader is familiar with at least one of high level language and has knowledge of elementary logic. This book consists of: A review of general microcomputer modules or subsystems and evolution of microprocessor. The internal architecture of microprocessor and instruction sets of the 8086 including the arithmetic, logic, and control transfer instructions. Examples are included to enhance the readers understanding of the applications of various instruction set. Pin descriptions of the 8086 microprocessor and bus cycle timing are discussed. The common types of internal memory and interfacing of the input output and memory are described. 8086 peripheral controls: programmable peripheral interface 8255 (PPI); universal synchronous/asynchronous receiver/transmitter 8251a (USART); programmable interrupt controller 8259A (PIC); and programmable interval timer 8254(PIT).

The teaching material microprocessor and interfacing create an environment for selfreliant teaching and learning practices. Besides, it is based on the new curricula and lecture notes for undergraduate course on microcomputers and interfacing that I have been teaching at Mekelle University, Electrical and Computer Engineering for the past four years. Fesseha Manna

IV

Table of Contents

Pages

Chapter One ................................................................................................................................ 1 INTRODUCTION TO MICROPROCESSORS AND MICROCOMPUTERS....................................... 1

1.1 INTRODUCTION TO INTEL FAMILY OF MICROPROCESSOR.................................................... 1 1.2 STORED PROGRAM COMPUTERS .......................................................................................... 1 1.3 EVOLUTION OF THE INTEL MICROPROCESSORS ................................................................... 2 1.4 OVERVIEW OF MICROCOMPUTER STRUCTURE AND OPERATION ........................................ 3 1.4.1 MEMORY .................................................................................................................... 3 1.4.2 INPUT/OUTPUT PORTS ............................................................................................... 3 1.4.3 CENTRAL PROCESSING UNIT ...................................................................................... 3 1.4.4 BUSES ......................................................................................................................... 4 1.4.5 HARDWARE, SOFTWARE, AND FIRMWARE ................................................................ 4 Chapter Two ................................................................................................................................ 5 8086 CPU ARCHITECTURE ........................................................................................................... 5 2.1 INTRODUCTION TO 8086 CPU ARCHITECTURE...................................................................... 5 2.2 FETCH AND EXECUTE ............................................................................................................. 7 2.3 PROGRAMMING MODEL ....................................................................................................... 9 2.4 SEGMENTED MEMORY ........................................................................................................14 2.5 MEMORY MAP .....................................................................................................................15 2.6 SEGMENT REGISTERS ..........................................................................................................16 2.7 LOGICAL AND PHYSICAL ADDRESS.......................................................................................18 2.8 ADVANTAGES OF SEGMENTED MEMORY ...........................................................................20 Chapter Three............................................................................................................................21 INSTRUCTION SET OF THE 8086 ................................................................................................21 3.1 DEFINING MEMORY LOCATIONS .........................................................................................21 3.2 ADRRESING MODES .............................................................................................................21 3.2.1 IMMEDIATE ADDRESSING MODE .............................................................................22 3.2.2 REGISTER ADDRESSING MODE .................................................................................22 3.2.3 DIRECT ADDRESSING MODE .....................................................................................22

3.2.4 INDIRECT MEMORY ACCESS ADDRESSING MODES ..................................................22 3.2.5 STRING ADDRESSING MODE ....................................................................................23 3.3 DATA TRANSFER INSTRUCTIONS .........................................................................................25 3.4 SPECIAL DATA TRANSFER INSTRUCTION .............................................................................26 3.5 SEGMENT OVERRIDE ...........................................................................................................29 3.6 STRING INSTRUCTION..........................................................................................................30 3.7 REPEAT PREFIX.....................................................................................................................34 3.8 LOGICAL INSTRUCTIONS ......................................................................................................35 3.8.1 BOOLEAN FUNCTION................................................................................................35 3.9 SHIFT AND ROTATE INSTRUCTIONS.....................................................................................39 3.10 ARITHMETIC INSTRUCTIONS .............................................................................................39 3.10.1 ADDITION AND SUBTRACTION INSTRUCTION........................................................39 3.10.2 MULTIPLICATION AND DIVISION ............................................................................42 3.11 TRANSFER OF CONTROL INSTRUCTION .............................................................................45 3.11.1 Unconditional jump instruction .............................................................................45 3.11.2 Conditional jump ....................................................................................................48 3.12 Loop instructions ...............................................................................................................49 3.13 Push and pop instructions .................................................................................................51 3.14 Call and return instructions ...............................................................................................52 3.15 Software interrupts ...........................................................................................................54 3.16 Processor control instruction ............................................................................................57 Chapter Four..............................................................................................................................60 THE 8086 CUP MODULE ............................................................................................................60 4.1 8086 CPU READ AND WRITE BUS CYCLE .............................................................................60 4.1.1 BUS CYCLE TIMING ...................................................................................................60 4.2 8086 CPU PIN DESIGN/DESCRIPTIONS ................................................................................62 4.3 GENERATING THE 8086 SYSTEM CLOCK & RESET SIGNALS ................................................. 67 4.3.1 COLD STARTING THE 8086 ....................................................................................68 4.4 MICRO COMPUTER BUS-TYPES AND BUFFERING TECHNIQUES ..........................................69 4.5 THE 8086 MINIMUM MODE CPU MODULE .........................................................................70 VI

Chapter Five ..............................................................................................................................71 MAIN MEMORY SYSTEM DESIGN ..............................................................................................71 5.1 TYPES OF MAIN MEMORY ...................................................................................................71 5.2 INTERFACING MEMORY ......................................................................................................73 5.3 ADDRESS DECODING TECHNIQUES .....................................................................................76 5.3.1 THE 3-TO-8 LINE DECODER (74LS138) ......................................................................76 Chapter Six.................................................................................................................................78 BASIC INPUT AND OUT PUT.......................................................................................................78 6.1 PARALLEL I/O .......................................................................................................................78 6.2 Serial I/O ..............................................................................................................................80 6.3 PROGRAMMED INPUT OUTPUT ..........................................................................................83 6.4 INTERRUPT DRIVERS I/O ......................................................................................................86 6.5 DIRECT MEMORY ACCESS (DMA) ........................................................................................87 Chapter Seven ...........................................................................................................................90 PERIPHERAL CONTROLLERS FOR THE 8086 ...............................................................................90 7.1 THE 8255 POGRAMMABLE PERIPHERAL INTERFANCE (PPI)................................................ 90 7.1.1 INTERFACING THE 8255 ...........................................................................................92 7.1.2 SPECIFYING THE CONTROL WORD (Mode Selection)...............................................94 7.1.3 Bit Set/Reset .............................................................................................................96 7.1.4 Mode 0: Simple Input or .Output. ............................................................................97 7.1.5 MODE 1: STROBED I/O .............................................................................................97 7.2 THE 8251A UNIVERSAL SYNCGRINOUS/ASSYCHRNOUS RECEEIVER/TRNASMETER (USART) .................................................................................................................................................105 7.2.1 INTERFACING THE 8251A .......................................................................................106 7.2.2 GENERATING THE ASYNCHRONOUS BAUD RATE CLOCK .......................................109 7.2.3 PROGRAMMING THE 8251A FOR THE ASYNCHRONOUS MODE............................110 7.2.4 PROGRAMMING THE 8251A FOR THE SYNCHRONOUS MODE ..............................112 7.3 PROGRAMMABLE INTERRUPT CONTROLLER (8259A) ....................................................... 113 7.3.1 INTERRUPT SEQUENCE ...........................................................................................117 7.3.2 PROGRAMMING THE 8259A ..................................................................................119

VII

7.3.3 INITIALIZATION COMMAND WORDS (ICWS) ..........................................................119 7.3.4 OPERATION COMMAND WORDS (OCWS)..............................................................121 7.3.5 CASCADE MODE .....................................................................................................121 7.4 PROGRAMMABLE INTERVAL TIMER (8254).......................................................................122 7.4.1 FUNCTIONAL DESCRIPTION ....................................................................................123 7.4.2 BLOCK DIAGRAM ....................................................................................................124 7.4.3 8254 SYSTEM INTERFACE .......................................................................................126 7.4.4 OPERATIONAL DESCRIPTION ..................................................................................126 7.4.5 MODE DEFINITIONS................................................................................................134 7.4.6 OPERATION COMMON TO ALL MODES.................................................................. 138

VIII

List of Figures

Pages

Figure 1.1 block diagram of a simple microcomputer ..................................................................... 3 Figure 2.1 a model of the 8086 CPU................................................................................................. 6 Figure 2.2 fetch and execute ............................................................................................................ 8 Figure 2.3 8086 programming model.............................................................................................10 Figure 2.4 register SI is pointing at memory location 1000H .....................................................10 Figure 2.5 the bit definitions for the 16-bit flag register ...............................................................12 Figure 2.6 an even-addressed bank and an odd-addressed bank of the 8086 ..............................15 Figure 2.7 Memory map for the 8086 microprocessor. .................................................................16 Figure 2.8 Memory segment. .........................................................................................................17 Figure 3.1 LDS transfers double word ............................................................................................29 Figure 3.2 shift and rotate instructions ..........................................................................................37 Figure 3.3 register usage for multiplication and division instructions ...........................................43 Figure 3.4 Stack area after executing an INT type instruction. ......................................................55 Figure 3.5 interrupt jump table ......................................................................................................55 Figure 3.6 interrupt jump table ......................................................................................................56 Figure 4.1 memory, I/O read/write bus cycle timing .....................................................................61 Figure 4.2 8086 CPU pin design ......................................................................................................63 Figure 4.3 the four control bus signals ...........................................................................................64 Figure 4.4 Decoding status signals S3 and S4.................................................................................65 Figure 4.5 tri-state buffers and its truth table ...............................................................................70 Figure 5.1 pin description common to all memory ........................................................................73 Figure 5.2 Interfacing 8k-byte memory to the 8086 CPU. .............................................................74 Figure 5.3 The memory bank write selection input signal: ............................................................75 Figure 5.4 simple address decoding technique. .............................................................................75 Figure 5.5 pin description of 3-to-8 line decoder...........................................................................76 Figure 5.6 the 74LS138 3-to-8 line decoder connected to memory ..............................................77 Figure 6.1 input output port address decoder and 8-bit output port. ..........................................79 Figure 6.2 One-bit input and output port. .....................................................................................81

IX

Figure 6.3 Standard asynchronous serial data format. ..................................................................82 Figure 6.4 parallel printer interface to the 8086 using programmed input output .......................84 Figure 6.5 flow chart for the printer control program ...................................................................85 Figure 6.6 execution process of interrupt service routine. ............................................................87 Figure 6.7 A DMA controller interface ...........................................................................................88 Figure 7.1 Pin definition of the 8255 Chip......................................................................................90 Figure 7.2 (a) block diagram and (b) pin description of 8255 (PPI)................................................91 Figure 7.3 interfacing the 8255 to the 8086 maximum-mode CPU module. .................................93 Figure 7.4 control words of 8255, when bit 7 = 0, a bit set/reset operation is indicated .............95 Figure 7.5 control words of 8255 when bit 7 = 1, any of the modes 0, 1, or 2 can be programmed. ........................................................................................................................................................ 96 Figure 7.6 Interfacing 8255 I/O Ports in Mode 0............................................................................98 Figure 7.7 (a) input configuration; (b) control word; (c) status word of the 8255A in Mode 1 (Strobed input) ...............................................................................................................................99 Figure 7.8 (a) Output Configuration; (b) control word; (c) status word of the 8255A in Mode 1 (Strobed output)...........................................................................................................................100 Figure 7.9 interfacing the 8255A in mode 1 (strobed input/output) ...........................................101 Figure 7.10 8255 mode 2 status word. ........................................................................................103 Figure 7.11 interfacing two computers using mode 2. ................................................................103 Figure 7.12 block diagram for the INTEL 8251A USART ...............................................................105 Figure 7.13 pin descriptions for the INTEL 8251A USART. ...........................................................106 Figure 7.14 interfacing the 8251A to the 8086 microprocessor maximum-mode CPU module. 108 Figure 7.15 (a) Asynchronous mode instruction word format; (b) synchronous mode command word format. ................................................................................................................................110 Figure 7.16 8251A status register ................................................................................................111 Figure 7.17 (a) block diagram (b) pin configuration of 8259........................................................114 Figure 7.18 Interfacing 8259A (PIC) to 8086 microprocessor ......................................................118 Figure 7.19 cascading the 8259. ...................................................................................................121 Figure7.20 block diagram and pin-configuration of 8454 ............................................................122 Figure 7.21 control word register and counter functions; internal block diagram of a counter .125 Figure 7.22 system interface ........................................................................................................127

Figure 7.23 control word format ..................................................................................................127 Figure 7.24 few possible programming sequence .......................................................................129 Figure 7.25 counter latching command format ...........................................................................130 Figure 7.26 Read-Back Command format. ...................................................................................131 Figure 7.27 status byte .................................................................................................................132 Figure 7.28 null count operation ..................................................................................................132 Figure 7.29 read/write operations summery ...............................................................................133 Figure 7.30 Read-back command example. .................................................................................133 Figure 7.31 Gate pin operations summery...................................................................................137 Figure 7.32 minimum and maximum initial counts. ....................................................................138

XI

List of Tables
Table 2.1 8086 flag word Table 2.2 segment register assignments Table 3.1 effective address calculations for the indirect memory access addressing mode Table 3.2 addressing modes of the 8086 microprocessor Table 3.3 MOV instruction Table 3.4 special data transfer instructions Table 3.5 Default register assignments Table 3.6 segment override prefix Table 3.7 string instruction Table 3.8 repeat prefix Table 3.9 logical instructions Table 3.10 shifts and rotate instructions Table 3.11 addition and subtraction instructions Table 3.12 multiplication and division instructions Table 3.13 jump instruction Table 3.14 conditional jump instructions Table 3.15 loop instructions Table 3.16 push and pop instructions Table 3.17 call and return instructions Table 3.18 software interrupt instructions Table 3.19 processor control instructions Table 4.1 S3 S7 status bit definitions Table 4.2 memory access encoding Table 4.3 CPU state following RESET Table 6.1 8086 bus condition during HOLD (minimum mode) Table 7.1 Truth table for the 8255A PPI Table 7.2 8255 port addresses for the interface in figure 7.3 Table 7.3 8251A control logic truth table

Pages
12 19 23 24 26 27 30 31 32 34 36 38 40 44 47 48 50 51 53 57 58 65 66 68 88 92 94 107

XII

Table 7.4 pin description of 8259A Table 7.5 PIC interrupt vectors Table 7.6 pin description of 8454

115 120 123

XIII

Chapter One I TRODUCTIO TO MICROPROCESSORS A D MICROCOMPUTERS 1.1 I TRODUCTIO TO I TEL FAMILY OF MICROPROCESSOR
The three leaders in the 16-bit processor area are the Zilog (Z8000), the Motorola (M6800), and the Intel (8086). This course is concerned primarily with the Intel 8086 and its associated devices. The 8086 microprocessor is actually just one integrated-circuit (IC) chip in a family of 16-bit microprocessors designed by Intel and providing a powerful but general purpose microprocessor supported by specialpurpose co-processors. For example, the iAPX86/21 is a three-chip microcomputer system based on the 8086 microprocessor, the 8087 numerical data processor (NDP), and the 8089 input output processor (IOP) The 8087 and 8089 expands the capabilities of the 8086. Using the 8087, the 8086 microprocessor can perform complex mathematical operations up to 100 times faster than it can alone. Using the 8089, much of the burden of controlling the peripheral devices (printers, disk drives, etc) is lifted from the 8086, allowing it to concentrate on other tasks. The 8088 microprocessor is identical to the 8086 but can read memory only 8-bits at a time Intels 80X86 families of microprocessors is the most widely used architecture in modern microcomputer systems. The family includes both 8-bit microprocessors (8085/88) 16-bit microprocessors (8088, 8086, 80c186, and 80286) and 32-bit microprocessors (80386, 80486, Pentium processor families) The original IBM personal computer (PC) uses the 8088, which is the 8-bit version of the 8086. The 80286 microprocessor is the advanced version of 8086. Note that the numbers 8086, 8088 was probably chosen to avoid copy right violation with Intel.

1.2 STORED PROGRAM COMPUTERS

One of the first digital computers was a machine called ENIAC (Electronic Numerical Integrator and Computer). It was designed and built at the Moore School of Electrical Engineering at the University of Pennsylvania in 1946. ENIAC contained over 18,000 vacuum tubes, weighed more than 30 tones, and required 1500 square feet of floor space. It was programmed by setting up to 6000 switches and connecting cables between the various units of the computer.
1

While ENIAC was under construction, John von Neumann, also of the Moore School of Electrical Engineering, proposed totally new computer architecture. Now called the stored program concept, Von Neumann suggests that just like the data, the computer program be stored in memory. The computer would then be permanently wired to fetch its instruction from memory instead of being rewired for each new program. Interestingly enough, virtually all computers today are still based on the von Neumann architecture and stored program concept.

1.3 EVOLUTIO OF THE I TEL MICROPROCESSORS

Microprocessors and microcomputers generally are categorized in terms of the maximum number of binary bits in the data they processes, i.e., their word length. Over time, five standard data widths have evolved for microprocessors and microcomputers: 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit. The worlds first microprocessor, the Intel 4004, was a 4-bit (nibble of data) microprocessor. It has the following characteristics: It addressed 4096- 4-bit wide memory locations. Its instruction set contained only 45 instructions. Execute instructions at slow rate of 50 KIPS (kilo instructions per second).

Beginning in 1970, a second generation of microprocessors was introduced. These devices, the 8008, 8080, and 8085 were 8-bit microprocessors and were designed to processes 8-bit (1-byte-wide) data instead of 4-bitdata. They were characterized by higher performance operation, larger system capabilities, and greater ease of programming. These extended capabilities led to wide spread acceptance of multichip 8-bit microcomputers for special-purpose system designs. Examples are electronic instruments, cash registers, and printers. In the mid-1970s, third-generation 16-bit microprocessor was developed. In 1979 the Intels first 16-bit microprocessor was released. The next year its 8-bit version, the Intel 8088 was followed. This was the birth of Intels 8086 family architecture, such as the 80286, 80186, and 80188. These 16-bit microprocessors provided higher performance and had the ability to satisfy a broad scope of special-purpose and general-purpose microcomputer applications. In 1985, Intel Corporation introduced its first 32bit microprocessor, the 80386DX, which brought true minicomputer-level performance to the microcomputer system. They were followed by a yet higher performance family, the Pentium processors, in 1993. Today, its fourth generation memberthe Pentium IV processor, represents this family.
2

1.4 OVERVIEW OF MICROCOMPUTER STRUCTURE A D OPERATIO

The major parts of a microcomputer are the central processing unit (CPU), memory, and the input and output circuitry or I/O. these parts are connected by three sets of parallel lines called Buses. The three buses are the address bus, the data bus and the control bus.
Data bus

Input device Input output (I/O) ports Output device Control bus

Central processing unit (CPU)

Control bus

Memory

Address bus

Figure 1.1 block diagram of a simple microcomputer

1.4.1 MEMORY
The memory section usually consists of RAM and ROM. It may also have magnetic floppy disks, magnetic hard disks or laser optical disks. Memory has two purposes. The first purpose is to store the binary codes for the sequence of instructions you want the computer to carry out. The second purpose of the memory is to store the binary-coded data with which the computer is going to be working.

1.4.2 I PUT/OUTPUT PORTS

The input/output or I/O section allows the computer to take in data from the outside world or send data to the outside world. Peripherals such as keyboards, videodisplay terminals, printers and modems are connected to the I/O section. These allow the user and the computer to communicate with each other. The actual physical devices used to interface the computer buses to external systems are often called ports.

1.4.3 CE TRAL PROCESSI G U IT

It controls the operation of the computer. In microcomputers the CPU is a microprocessor. It fetches binary-coded instructions from memory, decodes the instruction in to a series of simple actions, and carries out these actions in a sequence of steps. It contains an address counter or instruction pointer register, which holds the address of the next instruction or data item to be fetched from memory; Generalpurpose registers,

which are used for temporarily storage of binary data; and circuitry, which generates the control bus signals. The entire CPU with timing and control functions on a single chip is known as Microprocessor. Therefore a Microprocessor or MPU is an integrated circuit that contains many processing capabilities of a large computer.

1.4.4 BUSES
ADDRESS BUSES It consists of 16, 20, 24, or 32 parallel signal lines. On these lines the CPU sends out the address of the memory or I/O port location that is to be written to or read from. The number of memory locations that the CPU can address is determined by the number of address lines. If the CPU has N address lines, then it can directly address 2N memory locations. For Example a CPU with 16 address lines can address 216 or 65,536 memory locations. For N = 20, 220 = 1,048.576 locations are addressed. When the CPU reads data from or writes data to a port, it sends the port address out on the address bus. DATA BUS It consists of 8, 16, or 32 parallel lines. They are bidirectional, this means that the CPU can read data in from memory or from a port on these lines, or it can send data out to memory or to a port on these lines. CO TROL BUS It consists of 4, to 10 parallel lines. CPU sends out signals on the control bus to enable the outputs of addressed memory devices or I/O devices. Typical control bus signal are memory read, memory write, I/O read, and I/O write. For example, to read a byte of data from a memory location, the CPU sends out the memory address of the desired byte on the address bus and then sends out a memory read signal on the control bus. The memory read signal enables the addressed memory device to output a data word on to the data bus. The data word from memory travels along the data bus to the CPU.

1.4.5 HARDWARE, SOFTWARE, A D FIRMWARE

Hardware is the name given to the physical devices and circuitry of the computer. Software refers to the programs written for the computer. Firmware is the term given to the programs stored in ROMs or in other devices which keep their stored information when the power is turned off.

Chapter Two 8086 CPU ARCHITECTURE 2.1 I TRODUCTIO TO 8086 CPU ARCHITECTURE
The 8086 was the first 16-bit Microprocessor to be introduced by Intel Corporation. It is designed to be backwardly compatible with the older 8080/8085 series of 8-bit microprocessors. The backward compatibility allows programs written for the 8080/8085 to be easily converted to run on the 8086. The word 16-bit means that its arithmetic logical unit, internal registers, and most of its instructions are designed to work with 16-bit binary words. The 8086 has a 16-bit data bus, so it can read data form or write data to memory and ports either 16-bits or 8- bits at a time. The 8086 has a 20-bit address bus, so it can address any one of 220 or 1,048,576 memory locations. Each of the 1,048,576 memory addresses of the 8086 represents a byte-wide location. Words will be stored in two consecutive memory locations. If the first byte of a word is at an even address, the 8086 can read the entire word in one operation. If the first byte of the word is at an odd address, the 8086 will read the first byte of the word in one operation, and the second byte in another operation. The microprocessor functions as the CPU in the stored program model of the digital computer. Its job is to generate all system timing signals and synchronize the transfer of data between memory, I/O, and itself. It accomplishes this task via the threebus system architecture. The microprocessor has a software function. It must recognize, decode, and execute program instructions fetched from the memory unit. This requires arithmetic logic unit (ALU) within the CPU to perform arithmetic and logical (AND, OR, NOT, compare, etc.) operations. Figure 2.1 is a model of the 8086 CPU. It is divided into two separate functional units called Bus Interface Unit (BIU) and Execution Unit (EU) Bus Interface Unit (BIU) The BIU is made up of the address generation and bus-control unit, the instruction queue, and the instruction pointer. It has the task of making sure that the bus is used to its fullest capacity in order to speed up operations. This function is carried in two ways. First, by fetching the instructions before they are needed by the execution unit and storing them in the instruction queue, the 8086 MPU is able to increase computing speed. Second, by taking care of all bus-control functions, the EU is free to concentrate on processing data and carrying out the instructions. The instruction pointer contains the location or address of the next instruction to be executed.
5

BIU provides hardware functions, including generation of the memory and I/O addresses for the transfer of data between the outside world (outside CPU) and the CPU (E.U)

Figure 2.1 a model of the 8086 CPU

Instruction Queue: - The instruction queue is used as a temporary memory storage area for data instructions that are to be executed by the MPU. The BIU, through the buscontrol unit, pre-fetches instructions and stores them in the instruction queue. This allows the execution unit to perform its calculations at maximum efficiency. Because the BIU and EU essentially operate independently, the BIU concentrates on loading instructions into the instruction queue. This usually takes more time to do than the calculations performed by the execution unit. In effect, the BIU and the EU work in parallel. The instruction queue is a First- In- First- Out (FIFO) memory. This means that the first instruction loaded into the instruction queue by the bus control unit will be the first instruction to be used the ALU. Execution Unit (EU) The EU is where the actual processing of data takes place inside the 8086 MPU. It is here that the arithmetic and logic unit (ALU) is located, along with the registers used to manipulate data and store immediate results. The EU accepts instructions and data that have been fetched by the BIU and then processes the information. Data processed by the EU can be transmitted to the memory or peripheral devices through the BIU. EU has no direct connection with the outside world and relies solely on the BIU to feed it with instructions and data as indicated in figure 2.1 ALU: - The ALU is the calculator part of the execution unit. It consists of electronic circuitry that performs arithmetic operations or logical operations on the binary represented electrical signals. The control system for the execution unit can also be thought of as part of ALU. It provides a path for the flow of instructions into the ALU, the general registers, and the flag register.

2.2 FETCH A D EXECUTE

Although the 8086 still functions as a stored program computer organization of the CPU in to a separate BIU and EU allows the fetch and execute cycles to overlap. To see this, consider what happens when the 8086 is fist starred:1. The BIU outputs the contents of the Instruction pointer Register (IP) on to the address bus, causing the selected byte or word to be read in to the BIU. 2. Register IP is in cremated by 1 to prepare for the next instructions fetch. 3. Once inside the BIU, the instruction is passed to the queue. It is a FIFO storage register sometimes called pipeline 4. Assuming the queue is initially empty; the EU draws this instruction from the queue and begins execution.
7

5. While the EU is executing this instruction, the BIU proceeds to fetch anew instruction, and fill the queue with several new instructions. Depending on the execution time of the first instruction, the BIU may fill the queue with several new instructions before the EU is ready to draw its next instruction. Fetch Time Execute Fetch Execute Fetch (a) Execute Fetch

BIU EU

Fetch Wait

Fetch Execute

Fetch Execute

Fetch

Read data Fetch*

Fetch*

Fetch

Execute1 Wait

Execute Execute2 Wait

(b) Figure 2.2 fetch and execute (a) The conventional (non pipelined) microprocessor follows a sequential fetch and executes cycle. (b) The 8086 pipelined architecture allows the execution unit (EU) to execute instruction without the delay associated with instruction fetching. * These bytes are discarded 1 this instruction requires a request data not in the queue 2 jump instructions occurs The BIU is programmed to fetch a new instruction whenever the queue has a room for one (with 8088) or two (with 8086) additional bytes. The advantage of this pipelined architecture is that the EU can execute instructions almost continually instead of having to wait for the BIU to fetch anew instructions. There are three conditions that will cause the EU to enter a wait mode. The first occurs when an instruction requires access to a memory location not in the queue. The BIU must suspend fetching its instructions and output the address of this memory location. After waiting for the memory access, the EU can resume executing instruction codes from the queue and the BIU can resume filling the queue. The second condition occurred when instruction to be executed is a jump instruction. In this case control is transferred to a new (non sequential) address. The queue, however, assumes that instructions will always be executed in sequence and thus will be holding the wrong instruction codes. The EU must wait while the instruction at the jump address is fetched. Note that any bytes presently in the queue must be discarded (they are overwritten).

The other condition that can cause the BIU to suspend fetching instructions occurs during execution of instructions that are slow to execute. For example, the instruction AAM (ASCII adjust for multiplication) requires 83 clock cycles to complete. At four clock cycles per instruction fetch, the queue will be completely filled during the execution of this single instruction. The BIU will thus have to wait for the EU to pull one or two bytes from the queue before resuming the fetch cycle.

2.3 PROGRAMMI G MODEL

In order to program the 8086/88 the various registers in the BIU and EU should be placed in to logical groups to form a programming model.

AX BX CX DX

AH BH CH DH

AL BL CL DL

Accumulator Base Count Data Data group

SP BP SI DI IP

Stack pointer Base pointer Source index Destination index Instruction pointer Pointer and index group

FlagsH FlagsL

Status and control flags

ES CS DS SS

Extra Segment Code Segment Data Segment Stack Segment Segment group

Figure 2.3 8086 programming model The data group consists of the accumulator Register (AX), Base register (BX), counter register (CX), and Data register (DX). Each can be accessed as a byte or a word. Thus BX refers to the 16-bit base register but BH refers only to the high-order 8 bits of this register. The data registers are normally used for storing temporary results that will be acted on by subsequent instructions. The pointer and index group are all 16-bit registers (you cannot access the low or high bytes alone). These registers are used as memory pointers. For example, the instruction MOV AH, [SI] has the word interpretation moves the byte whose address is contained in register SI to registers AH SI thus points at the desired memory locations. The brackets around SI are used to indicate the contents of memory pointed to by SI Not the value of SI itself. Example 2.1 If SI = 1000H, in the figure 2.4 what is the contents of register AH after the instruction MOV AH, [SI] is executed?

1004H 1003H 1002H 1001H 1000H

BD 4F 17 3A 26 SI

Figure 2.4 register SI is pointing at memory location 1000H Solution from the figure SI is pointing at the byte 26H. Thus AH will store 26H.

10

Register IP (instruction pointer) It is included in the pointer and Index group, but this register has only one function-to point to the next instruction to be fetched to the BIU, It is physically part of the BIU and not under direct control of the programmer as are the other pointer registers. Stack Pointer Register A stack is a section of memory set aside to store addresses and data while a subprogram is being executed. An entire 64 K bytes segment is set aside as stack in 8086 MPU. The upper 16 bits of the starting address for this segment is kept in the stack segment register. The Stack Pointer (SP) register contain the 16-bit offset from the start of the segment to the memory location where a word was most recently stored on the Stack. The memory location where a word was most recently stored is called the top of Stack. Figure 2.4 shows the details. The physical address for a stack read or for a stack write is produced by adding the contents of the stack pointer register to the segment base address in SS. To do this the contents of the Stack segment register are shifted four bit positions left and the contents of SP are added to the shifted result. For example, if SS = 5000H and SP = FFE0H. 5000H in SS is shifted left four bit positions to give 50000H. When FFEOH in the SP is added to this, the resultant physical address for the top of the stack will be 5FFEOH. The physical address can be represented either as a single number 5FFEOH, or it can be represented in SS:SP form as 5000:FFEOH Other pointer and Index Registers In addition to the Stack Pointer register, SP, the EU contains a 16-bit Base Pointer (BP) register. It also contains a 16-bit Source Index (SI) register and a 16-bit Destination Index (DI) register. These three registers can be used for temporary storage of data just as the general purpose registers. However, their main use is to hold the 16-bit offset of a data word in one of the segments. That is, the pointer and index registers are usually used to point to or index to an address in memory. When used in this manner, these registers are address registers that designate a specific location in the memory that may be frequently used by the program. The addresses contained in these registers can be combined with information from the BIU to physically locate the data in the memory. FLAG REGISTER Figure 2.5 shows the bit definitions for the 16-bit flag register. Flag registers in the EU holds the status flags typically after ALU operation. It indicates the condition of the microprocessor and controls its operation.

11

16-bit flag register contains nine active flags, 6 of the flags are status (condition) indictors, reflecting properties of the result of the last arithmetic or logical instruction. These are called conditional or status flags. These are carry flag (CF), parity flag (PF), auxiliary flag (AF), zero flag (ZF), sign flag (SF), overflow flag (OF). FlagsH FlagsL

u u u u OF DF IF TF SF ZF u AF u PF u CF u = undefined. Figure 2.5 The bit definitions for the 16-bit flag register Table 2.1 8086 flag word Bit position Name 0 2 CF PF Function Carry flag: set on high-order bit carry or borrow; Cleared otherwise. Parity flag: set if low-order 8-bits of result contain an even number of 1-bit; cleared otherwise. Auxiliary flag: Set on carry from borrow to the low order 4-bits of AL: cleared otherwise. Zero flag: set if result is zero: cleared otherwise. Sign flag: set equal to high-order bit of result (0 if positive, 1 if negative) Single step flag: once set, a single step interrupt occurs after the next instruction executes; TF is cleared by the single-step interrupt. Interrupt-enable flag: when set, maskable interrupts will the CPU to transfer control to an interrupt vector specified location. Direction flag: causes the string instruction to auto decrement the appropriate index register when set, clearing DF causes to auto increment. Overflow flag: set if the signed result cannot be expressed within the number of bits in the destination operand; cleared otherwise.

4 6 7

AF ZF SF

TF

IF

10

DF

11

OF

12

DF, IF, and TF can be set or reset to control the operation of the processor. The remaining flags are status indicators. Example 2.2 If register AL = 7FH and the instructions ADD Al, 1 (add one to AL) is executed, it gives the following result: AL= 80H CF = 0 PF= 0 Af= 1 Zf= 0 Sf= 1 OF=1 ; 7H+1= 80H ; There is no carrying out of bit 7 ; 80H has an odd number of logic 15 ; There is a carry flag ;The result is not zero ; Bit 7 is set ; the result (+128) exceeds the capacity of (signed) register AL

The 8086 has several instructions that can be used to transfer program control to a new memory location based on the state of the flags. For example, the instruction sequence ADD AL, 1 ; add 1 to register AL JNZ 0100H ; jump to location 0100H if the result is not zero (ZF = 0)

The above result will transfer control to location 0100H if the result of the ADD AL, 1 instruction is not zero. If it is desired to test for the zero condition, the JZ (jump if zero) instruction can be used. Three of the control flags can be set or reset directory by the programmer and are used to control the operation of the processor. These are trap flag (TF), interrupt flag (IF), and directional flag (DF). When TF (trap flag) is set, control is passed to a special address (previously defined by the programmer) after each instruction is executed. Normally, a program to display all the CPU registers and flags is stored there. Setting TF therefore causes the processor to operate in software singlestepping mode, pausing after each instruction is executed. This is very useful for program bugging. When IF (the interrupt flag) is set, external interrupt requests on the 8086/88 INTR in put line will be enabled. When INTR is driven high (i.e., an interrupt occurs), control is transferred to an interrupt service routine (ISR). When this routine has finished, it normally executes an IRET (interrupt return) instruction and control is transferred back to the instructions in the main program that was executing when the interrupt occurred. The DF (direction flag) is used with the block move (also called string) instructions. When DF is set the block memory pointer will automatically decrement; if reset, the pointer will increment.

13

The segment register groups are used by the BIU to determine the memory address output by the CPU when it is reading or writing from the memory unit. To fully understand these registers, we must first study the way the 8086 divides its memory in to segments.

2.4 SEGME TED MEMORY

Even though the 8086 is considered a 16 bit microprocessor (it has a 16 bit data bus width), its memory is still thought of in bytes. At first this may seem a disadvantage. Actually there are good reasons. 1. It allows the process to work on bytes as well as words (especially important with I/O devices such as printers, terminals, and modems, all of which are designed to transfer ASCII-encoded (7 or 8 bit) data. 2. Many of the 8086 operation codes are single bytes. Other instruction may require anywhere from two to seven bytes. By being able to access individual bytes, these odd-lengthened instructions can be handled. The 8086/88 has a 20 bit address bus, allowing it to output 220, or 1,048,576 different memory addresses. The 8086 reads 16 bits from memory by simultaneously reading an even-addressed byte and an odd-addressed byte. For this reason the 8086 organizes its memory in to an even addressed bank and an odd addressed bank as shown in the figure 2.6. Note that the 8086 provides control bus signals that can be decoded by the memory to determine if a byte or a word is to be accessed. If a word begins at odd-even address the CPU must perform two memory read cycles; one to fetch the low-order byte and a second to fetch the high-order byte. This slows down the processor. Note that the 8088 with its 8 bit data bus interfaces to the IMB of memory as a single bank. When it is necessary to access a word (written on an even- or an odd-addressed boundary) two memory read (or write) cycles are performed.

14

Even bank 1048574

Odd bank 1048575

4 2 0

5 3 1

16-bit data word to 8086 Figure 2.6 an even-addressed bank and an odd-addressed bank of the 8086

2.5 MEMORY MAP

There are 16 64 kilo-byte blocks beginning at hex address 00000 and ending at address FFFFFH. Be sure to note that five hex digits are required to represent a memory address. The diagram in the figure 2.7 is called a memory map it is a guide showing how the system memory is allocated. For example, it might show RAM (read/write memory) from 00000 to 3FFFFH, ROM (read-only memory) from FF000H to FFFFFH, and the remainder of the memory space unused. This type of information is vital to the programmer, who must know exactly where his or programs can be safety leaded. Some memory locations are marked reserved and others dedicated. The dedicated locations are used for processing specific system interrupts and the reset function. The reserved locations are for future hardware and software products. If you make use of these memory locations, you risk in compatibilities with these future products.

15

Figure 2.7 Memory map for the 8086 microprocessor.

2.6 SEGME T REGISTERS

Within the IMB of memory space, the 8086/88 defines four 64KB memory blocks called the code segment, stack segment, data segment, and extra segment. Each of these blocks of memory is used differently by the processor. The code segment holds the program instruction codes the data segment stores data for the program. The extra segment is an extra data segment (often for shared data). The stack segment is used to store interrupt and subroutine return addresses. The four segment registers shown in the figure 2.8 (CS, DS, ES, and SS) are used to point at locations 0 (the base address) of each segment. The problem of the segment registers being 16 bits wide but the memory address is 20 bits wide is solved by BIU by appending four 0s to the low-order bits of the segment

16

register. In effect, this multiplies the segment register contents by 16. Then CS register contains B3FFH but is interpreted as pointing to address B3FF0H. The point to note is that the beginning segment address is not arbitrary-it must begin at an address divisible by 16. Another way of saying this is that the low order hex digit must be 0. Also note that the four segments need not be defined separately they can be particularly or completely over lapped. Indeed, it is allowable for all four segments to completely overlap (CS = DS = ES = SS) Example 2.3 Calculate the beginning and ending addresses for the data segment assuming that register DS=E000H. Solution The base address is found by appending four 0s. Base address: E0000H. The ending address is found by adding FFFFH (64K). Ending address: E0000H + FFFFH = EFFFFH.

Figure 2.8 Memory segment.

17

Memory locations not defined to be within one or the current segments cannot be accessed by the 8086/08 without first redefining one of the segment registers to include that location. Thus, at any given instant a maximum of 256K (64K x 4) bytes of memory can be utilized. The contents of the segment registers can only be specified via software. Instructions to load these registers should be among the first given in any 8086 program. The 8086 divides its 1M byte of memory address space into four segments, called the data, code, stack, and extra segments. The four segment registers DS, CS, SS, and ES point to location 0 of the current segment. In this example the stack and extra segments are partially overlapped.

2.7 LOGICAL A D PHYSICAL ADDRESS

Addresses with in a segment can range from address 0 to address FFFFH. This corresponds to the 64KB length of the segment. An address within a segment is called an offset or logical address. The logical address is an offset from location 0 of a given segment. The actual or real address is called the physical address. The physical address is 20 bits long and corresponds to the actual binary code output by the BIU on the address bus lines. Example 2.4 Calculate the physical address corresponding to logical address D470H in the extra segment. Repeat for logical address 2D90H in the stack segment assume ES: 52B9, and SS: 5D27. Solution: The physical address for the extra segment and stack segment is same which is equal to 60000H Example 2.5 If IP = 10000H, where exactly is the next instruction fetching going to come from? Or where will the instruction MOV [BP], AL ;Move a copy or register AL to the memory location pointed to by register BP- store register AL? The answer is that every instruction that references memory has a default segment registers as shown in the table 2.2 (segment register assignments).

18

Table 2.2 segment register assignments Type of Memory reference Instruction fetch Stack operation General data String source String destination Default Alternate Offset (logical address) IP SP Effective address SI DI Effective address

Segment Segment CS SS DS DS ES None None CS, ES, SS CS, ES, SS None CS, ES, SS

BX used as pointer DS BP used as pointer SS

CS, ES, DS Effective address

The above table indicates that some memory references can have their segment definitions changed. For example, BP can also be used as a pointer into the code, data, or extra segments. On the other hand, Instruction fetches occur only from the code segment, with IP supplying the offset or logical address. Similarly, register BP used as appointer defaults to the stack segment. The table is programmed in to the BIU Example 2.6 What physical memory location is accessed by the instruction MOV (BP), AL is BP= 2C30H? Assume the segment definition shown in figure 2.8. Solution The table 2.2 indicates that the stack segment will be used. The physical address is 5D270H +2C30H 5FEA0H The table 2.2 segment register assignment indicates that some memory references can have their segment definitions changed. For example, BP can also be used as a pointer in to the code, data, or extra segments on the other hand, instruction codes can only be stored in the code segment with IP used as the offset. Similarly, string instructions

19

always uses the extra segment. The segment override is used to access these alternate segments.

2.8 ADVA TAGES OF SEGME TED MEMORY

One program can work on several different sets of data by reloading register DS to point to the new data. Programs that reference logical addresses only can be loaded and run anywhere in memory. An inactive program can be temporarily saved on a magnetic disk and a new program brought in to take its place-without concern for the physical location of this new program ( re-locatable programs)

Exercise 2.1 1. If IP = 3456H, where exactly is the next instruction fetch going to come from? 2. Where will the instruction MOV [BP] AL store register AL? Assume BP= 2C30H 3. Calculate the physical address corresponding to logical address. 76 D4H in extra segment. 38A4H in stack segment 4. Calculate the ending address of each segment assume BS= 358B= 35+= 5834, DS 8500?

20

Chapter Three I STRUCTIO SET OF THE 8086 3.1 DEFI I G MEMORY LOCATIO S
Usually, only the logical addresses are important. Indeed the physical address depends on the contents of the segment registers even though the logical address remains constant. When writing assembly language programs it is convenient to assign logical addresses labels or names. For example, the sequence DATA SEGMENT MEMBDS DB ? DATA ENDS Assigns the label MEMBDS to the byte at logical address 0 in the data segment. None of the three statements is a microprocessor instruction. However, they are pseudo instructions recognized by an assembler program. The operator DATA SEGMENT tells the assembler to store the following codes in the data segment. The second line uses the define byte operator (DB) to assign the label MEMBDS (memory byte in data segment) to a byte in the data segment. The ? symbol indicates that the contents of this byte is undefined. The statement DATA ENDS ends the data segment. If it is desired to define a word, the DW operator can be used. For example MEMWDS DW 1234H In this case the label MEMWDS will refer to a memory word location and the contents of that location will be initialized to 1234H (instead of being left undefined). To define a 32-bit double word the DD operator is used. A quad word (8 bytes) DQ. 10 bytes DT. The operators allow the programmer to specify memory locations by a name rather than by their specific address, they make the program clearer and more understandable.

3.2 ADRRESI G MODES

A computer instruction is made up of an operation code and zero, one, or two operands. The operation code identifies the operation to be performed while the operands identify the source and destination of the data operated on. The operands can specify a CPU register, a memory location in one of the memory segments, or an I/O port. The different ways in which the microprocessor generates these operand addresses are called the addressing mode. Table 3.2 lists the nine modes available with the 8086 microprocessor.
21

3.2.1 IMMEDIATE ADDRESSI G MODE

Instructions that use the immediate addressing mode get their data as part of the instruction. This mode represents a special case in which the data (located within the instruction) is stored in code segment instead of data segment. For example MOV AX, 1000H It is commonly used to load a register or memory location with some initial data. Following instructions then operate on this data. Note that the segment registers may not be specified.

3.2.2 REGISTER ADDRESSI G MODE

Some instructions simply operate on or move data back and forth between CPU registers. For Example MOV DX, CX puts a copy of register CX in register DX. Note that the operand requires no memory reference. The register addressing mode can be combining with immediate addressing mode to load a segment register. For example MOV AX, 8010H MOV DS, AX ; load AX with 8010H ; copy AX into DS

3.2.3 DIRECT ADDRESSI G MODE

All of the remaining addressing modes listed in table 3.2 require access to for at least one of the instruction operand. In the direct addressing mode the memory address is supplied directly as part of the instruction. However labels are often given to these addresses so that the programmer need not be concerned with the numeric address. For Example, MOV AH, MEMBDS ;store the contents of memory location MEMBDS in register AH.

3.2.4 I DIRECT MEMORY ACCESS ADDRESSI G MODES

The direct addressing mode is useful for infrequent memory accesses. However, when a memory location must be read from or written to several times with in a program, the repeated fetching of the two-byte logical address makes this mode inefficient. The indirect addressing mode solves this problem by storing the memory address in a pointer or index register (BX, BP, SI, or DI). In addition a 2s complement displacement (a single byte) can be added to the pointer or index to offset the location pointed at. Table 3.1 shows the various combinations possible.

22

Table 3.1 effective address calculations for the indirect memory access addressing mode Effective address Addressing mode Register index Displacement Base register None None Indexed Based + BX or BP + None Index register + None + SI or DI + SI or DI None

+ 127 to -128 + None

+ 127 to -128 + BX or BP +

Based and indexed None Based and indexed +127 to -128 with displacement

+ BX or BP + SI or DI + BX or BP + SI or DI

In general, a displacement can be added to a base register and the result added to an index register. This is called based and indexed with displacement. In between there are the economy modes, which use only a base or index register with or without a displacement. The resulting address is often referred to as the effective address (EA). Note that the displacement is limited to a single byte, allowing the EA to be varied +127 bytes (7FH) or -128 bytes (80H) from the pointer base. Note that BYTE PTR and WORD PTR are assembler pseudo operators needed to help the assembler determine if a byte or word memory access is required. By using these pointers the proper instruction codes will be generated by the assembler. The default memory segments for all the indirect addressing modes are the stack segment when register BP is involved and the data segment when register BX, SI, or DI is involved.

3.2.5 STRI G ADDRESSI G MODE

A string is a sequence of bytes or words stored in memory. Because of their importance, the 8086 has several instructions designed specifically for handling strings of characters. DS:SI is used to point to the string source and ES:DI is used to point to the string destination. Note that SI and DI are automatically incremented or decremented depending on the value of DF (directional flag).

23

Table 3.2 addressing modes of the 8086 microprocessor

Example 3.1 Identify the addressing mode for each of the following instructions: 1. 2. 3. 4. 5. MOV AH,47H MOV AH, [BP+2] MOV AH, [BP+SI] MOV AH, [XRAY] ;XRAY defines a memory location MOV AH, TEMP[BX] ;TEMP defines a memory location

Solution 1. Immediate; 2. Based; 3. Based and indexed; 4. Direct; 5. Based.

24

3.3 DATA TRA SFER I STRUCTIO S

There are over 3000 different 8086 instructions to consider, if each op-code is combined with each addressing mode. The data transfer group of instructions allows the microprocessor to communicate with the outside world via the input and output instructions. They also provide means for moving data into and out of memory and between the CPU registers. MOV instruction Table 3.3 lists the various types of data transfers possible using the MOV instruction. Note that the operand is always written in the form of destination, source. The data moved can be a byte or a word, although the pointer, index, and segment registers can only be accessed as a word. The destination and the source cannot both specify memory locations. The flags are unaffected by this group of instructions.

25

Table 3.3 MOV instruction

3.4 SPECIAL DATA TRA SFER I STRUCTIO

These are data transfer instruction that do not use the MOV mnemonics. These are shown in table 3.4 XCHG instruction performs a register to register or a register to memory swap that takes the place of three MOV instructions.

26

The 8 low-order flag bits can be stored in or loaded from register AH using the instructions SAHF and LAHF. Table 3.4 special data transfer instructions

27

I /OUT: a byte or a word of data can be input or output but must pass through the accumulator. AL must be used as the source or destination for 8-bit I/O operations. The port address can be specified in two ways: Direct mode: the instruction supplies the address but is limited to ports 0 255 (one byte) Indirect mode: register DX holds the 16-bit port address allowing access to all 65,536 ports Example 3.2 write the program required to output the word in BX to I/O ports 8004H and 8005H. Solution MOV DX, 8004H ;point DX at the port address MOV AX, BX ;data must be in AX OUT DX, AX ;output the data LEA (Load Effective Address) instruction will load pointer and index registers with the effective address of the labels Example LEA BX, MEMBDS will load register BX with effective address of MEMBDS. We would not have to know this address. LDS (load pointer using data segment) and LES (load pointer using extra segment) instructions are intended for loading entirely new address, including the segment register. They load the 16-bit destination register and ES or DS segment register with the contents of the double-word memory operand.
28

Example 3.3 Assume that MEMWWDS defines a double word beginning at address 1000H in the data segment as shown in the figure 3.1. What physical address will BX be pointing to after . the following instruction sequence? LEA SI, MEMWWDS LDS BX, DWORD PTR[SI]

Figure 3.1 LDS transfers double word Solution The instructions loads BX and DS with the contents of the double word pointed at by SI. In this case BX=8010 and DS=E000H. The physical address pointed to by BX BX=E0000H+8010H=E8010H. =E0000H+8010H=E8010H. Note the single instruction LDS BX, MEMWWDS could be used with the same effect. XLAT is useful for extracting data from a table using register AL as the offset into the table.

3.5 SEGME T OVERRIDE

Every instruction that access memory has a particular segment register that it uses to memory determine the EA of the memory operand. The alternate segment column in this table indicates that the default assignment can be overridden for some types of memory references. The four segment override prefix instructions are CS:, DS:, ES:, and SS:. prefix Note that the segment override is in effect for the one instruction only and thus must be specified for each instruction to overridden.

29

Table 3.5 Default register assignments

A typical application for the segment override is to allow data to be stored in the code segment. Example 3.4 CODE SEGMENT COUNT DB 0FFH MOV AL, CS:COUNT The variable COUNT is defined within the code segment, requiring the MOV instruction to use the CS: override to access this memory location.

3.6 STRI G I STRUCTIO

These instructions are used for moving large blocks of data or strings. For all these instructions the memory source is DS:SI and the memory destination is ES:DI. Segment override can applied only to the source address. The destination must be the extra segment. The offset memory pointers, DI and SI, are automatically incremented or decremented depending on the state of DF by 1 for bytes or by 2 for words. STOS (store string byte or word) and LODS (load string byte or word) instructions transfer a byte or word from the accumulator to memory or from the memory to the accumulator MOVS (move string byte or word) instruction combines these two operations, transferring the byte or word from the memory source to the memory destination.

30

Table 3.6 segment override prefix

31

Table 3.7 string instruction

32

SCAS (scan string byte or word) and CMPS (compare string byte or word) instructions allow the destination byte or word to be compared with the accumulator (SCAS) or the memory source (CMPS). After execution the flags are set to reflect the relationship of the destination to the source element. The conditional jump instructions can then be used to make decision such as jump if AL is greater than the memory byte or jump if the destination memory word equals the source memory word.
33

3.7 REPEAT PREFIX

Preceding the instructions STOS or MOVS with the REP (repeat) instruction causes these instructions to be repeated a number of times equal to the contents of the CX register. By loading CX with the number of words or bytes to be moved, a single string instruction (and REP prefix) can move up to 65,536 bytes. Table 3.8 repeat prefix

34

Example 3.5 Write the 8086 program required to fill the 1000D byte of memory in the extra segment beginning at address BLOCK with the data byte 20H. Assumed that the DF is to be 0. Solution ;AL holds the data byte ;DI holds the address of block ;load CX with 1000D ;store AL at ES:DI, increment ;DI, and repeat 1000 times REPE/REPZ (repeat while equal or zero) and REP E/REP Z (repeat while not equal or not zero) forms of the REP prefix are intended for use with the SCAS and CMPS string instructions. They allow the string operation to be repeated while equal (REPE/REPZ) or while not equal (REPNE/REPNZ). MOV AL, 20H LEA DI, BLOCK MOV CX, 03E7H REP STOSB

3.8 LOGICAL I STRUCTIO S

The logical instructions refers to the Boolean logical functions, such as AND, OR, NOT, exclusive OR, and to the rotate and shift instructions. These instructions are all performed in the ALU and usually affect all the flags.

3.8.1 BOOLEA FU CTIO

Each function is performed bit by bit between the source and destination operands. CF and OF are reset. Example 3.6 Determine the contents of register AL and the state of the flags after the following instructions are executed. MOV AL, 6DH MOV BH, 40H AND AL, BH Solution First write the register contents in binary: 01101101 01000000 01000000 (AL) (BH) =40H (AL)

The flags are affected as follows: CF = 0 ;CF is reset by the AND instruction
35

PF = 0 ;40H has an odd number of logic 1s AF = x ;AF is undefined ZF = 0 ;the result is not zero SF = 0 ;bit is reset OF = 0 ;OF is reset by the AND instruction Table 3.9 logical instructions

36

The applications of A D The destination operand can be forced low by choosing those bits as 0 in the source operand. To consider the source operand a mask for testing selected bits of the destination operand. In the above example all bits are masked except bit 6. If this bit is 0, the result is zero, if it is 1, the result is non zero. AND AL, BH JZ START Using the AND instruction results in a destructive bit test because the contents of the destination operand is altered by the instruction.

Figure 3.2 shift and rotate instructions

37

TEST: this instruction performs the same function as AND instruction, but doesnt alter the source or destination operand. This is a particular handy instruction to use when several bits must be tested. OR instruction can be used to force selected bits high. Example OR AL, 80H will force bit 7 of AL high without changing any of the other bits in this register. Exclusive-OR can be used to complement selected bits. Example XOR AL, 80H will complement bit 7 of register AL without changing any of the other bits. Table 3.10 shifts and rotate instructions

38

3.9 SHIFT A D ROTATE I STRUCTIO S

There are several shift and rotate instructions. The rotated quantity can be an 8-bit or a 16-bit CPU register or memory location. The main difference between a shift and a rotate is that the shifted bits fall off the end of the register, where as the rotated bits wrap around. Within the shift group of instructions there are both arithmetic (SAL and SAR) and logical (SHL and SHR) shift instructions. The arithmetic shifts operate so that the sign bit (bit 7 or bit 15) doesnt change when the shift occurs. The SAL instruction in effect multiplies the data by 2 (maintaining the correct sign), and SAR divides the data by 2. The overflow flag (OF) will be set if the shifted quantity exceeds the limits for an 8- or 16-bit register (+127 to -128 for bytes and +32767 to -32768 for words). The shift and rotate instructions can be repeated up to 255 times by loading register CL with the desired count. Example 3.7 MOV CL, 5 RCL DX, CL Will rotate the contents of register DX left 5 times through the carry

3.10 ARITHMETIC I STRUCTIO S

The 8086/88 can add and subtract 8- and 16- bit numbers in any of the general CPU registers, and using certain dedicated registers, perform multiplication and division of signed or unsigned numbers.

3.10.1 ADDITIO A D SUBTRACTIO I STRUCTIO

There are two forms of addition and subtraction instructions. One includes the carry and the other doesnt. Note that the destination and source operands can be register and register, register and memory, memory and register, immediate data and register, or immediate data and memory. For example, suppose we wish to add the 32 bit number in register BX:AX to the 32-bit number DX:CX. BX AX +DX CX DX CX Although there are no 32-bit addition instructions, the problem is easily solved by the ADC (add with carry) instruction.
39

For Example ADD CX, AX ADC DX, BX

;CX ;DX

CX + AX DX + BX + CF

The first instruction does not include the carry, as there is no carry in at this point. If the addition of AX and CX sets CF, the second addition will add this to the sum of the DX and BX. The SUB (subtract) and SBB (subtract with borrow) instructions work similarly, with CF representing the borrow condition. Table 3.11 addition and subtraction instructions

40

When adding or subtracting one from a memory pointer or counter variable, the I C (increment) and DEC (decrement) instructions should be used. The EG (negate) instruction forms the 2s complement of the destination operand, effectively reversing its sign. This is done by subtracting the destination from 0. Example 3.8 Determine the value of AL and the value of the flags following the instruction sequence MOV AL, 5 NEG AL Solution AL = 00000000 - 00000101 = 11111011 = FBH = -5.

41

The flags are affected as follows: CF = 1 ;NEG sets CF except when the operand is 0 PF = 0 ;FBH has an odd number of logic 1s AF = 1 ;there is a borrow out of bit 4 ZF = 0 ; the result is not 0 SF = 1 ;bit 7 is set OF = 0 ;there is no overflow condition

The CMP (compare) instruction is useful for determining the relative size of two operands. Normally it is followed by a conditional jump instruction such as jump if equal or jump if greater than or equal.

3.10.2 MULTIPLICATIO A D DIVISIO

Multiplication and division can be performed on signed or unsigned numbers. The source operand can be a memory location or a CPU register, but the destination operand must be register AX (and register DX for 32-bit results). The register usage is shown in figure 3.3 for both byte and word operations. Note that the immediate operands are not allowed. Example 3.9 Write a program to input two 8-bit unsigned numbers from input ports A0H and B0H and output the product to 16-bit output port 7080H. Solution IN AL,0A0H MOV BL, AL IN AL, 0B0H MUL BL MOV DX, 7080H OUT DX, AX Division can be performed on the word in AX or the double word in DX:AX. The divisor can be an 8-bit or a 16-bit memory location or CPU register. Note that the remainder is returned in register AH or DX when the result does not come out even. Example 3.10 Write a program to divide the unsigned word input at indirect I/O port 8000H by 500D. Determine the result if the input data is 56,723.

42

Solution MOV DX, 8000H MOV BX, 01F4H IN AX, DX DIV BX The result is AX = INT (56,723/500) = 113=71H and DX = MOD (56,723/500) = 223 = 00DFH A special problem can occur when the divisor is so small as to cause the quotient to overflow the register dedicated to the result. For example, dividing 65,000 by 2 leaves a result too large to fit in register AL alone. When this occurs a special divide by zero software interrupt is automatically generated by the 8086. This causes control to be transferred to the address stored in locations 00000-00003H. The integer multiplication (IMUL) and division (IDIV) instructions are similar to the unsigned forms except that the most significant bit represents the sign of the number. For integer byte division the quotient is limited to the range +127 to -128 and to the range +32767 to -32768 for word division. The register usage is shown

Figure 3.3 register usage for multiplication and division instructions The multiplication and division instructions can be performed on 8-bit or 16-bit register or memory source operands. Specific registers are dedicated to these functions as shown.

43

Table 3.12 multiplication and division instructions

44

3.11 TRA SFER OF CO TROL I STRUCTIO

All programs execute in a sequential manner (fetch instruction whose address is in IP, increment IP, and execute the instruction). However, there are times when it is necessary to transfer program control to an address that is not the next instruction in sequence. Examples are: Group of instructions that must be executed repeatedly Groups of instructions that are shared throughout a program (subroutine) Conditional transfers based on the state of the flags, and Software interrupts.

3.11.1 U CO DITIO AL JUMP I STRUCTIO

There are five forms of the jump instruction. Three of them are unconditional, (control is transferred to the target address without regard for the state of flags) When a program control is transferred to a new address relative to the value in IP, it is called near or relative jump (direct form). When the target address is within -128 to +127 bytes of IP, it is called short jump. Using short jump one byte of object code can be saved. Because one less byte is required, the short form is best. In fact, when assembling
45

your program, the assembler will automatically generate a short jump if it can determine that the target address is located within -128 to +127 bytes. The following group of instructions shows assembly language program demonstrating the near jump instruction ADDR HEX CODES LABELS OP-CODE OPERANDS 0000 B3 04 MOV BL, 04H 0002 E5 06 REPEAT: IN AX, 06H 0004 F6 F3 DIV BL 0006 E7 9A OUT 9AH, AX 0008 E9 F7 FF JMP REPEAT 000B And the following program is rewritten using the JMP SHORT instruction; one byte of code is saved. ADDR HEX CODES LABELS OP-CODE OPERANDS 0000 B3 04 MOV BL, 04H 0002 E5 06 REPEAT: IN AX, 06H 0004 F6 F3 DIV BL 0006 E7 9A OUT 9AH, AX 0008 E9 F8 JMP SHORT REPEAT 000A The memory indirect and register indirect forms of the jump instruction specify the actual 16-bit target address. These two forms are not thus relative. Example JMP SHORT REPEAT instruction can be replaced with two instructions. MOV BX, 00002 JMP BX Note that using indirect jump, any address within the code segment can be specified. However, an extra instruction is required to set the target address. The main advantage of using relative jump is that the resulting program is relocatable anywhere within the code segment. When control is transferred to a target address in a new code segment, it is called a far jump. Again direct and indirect forms are possible but neither form is relative. The direct form requires the assembler operator FAR PTR to identify the label as being in a new code segment. The indirect forms must specify a double word for the new CS and IP values.

46

Table 3.13 jump instruction

47

3.11.2 CO DITIO AL JUMP

The conditional jump instructions perform a short jump based on the condition of the status flags. Tables below show and list all the testable conditions. Usually, a conditional jump instruction is placed after an arithmetic or logical instruction, transferring control depending on the result of that instruction. Table 3.14 conditional jump instructions

48

Example 3.11 Explain the operation of the following program. MOV BL, 47H IN AL, 36H CMP AL, BL JE MATCH JA BIG JMP SMALL Note that MATCH, BIG, and SMALL must be located within -128 to +127bytes of the corresponding conditional jump instruction Solution The program inputs a data byte from input port 36H and then compares it with 47H. If a match occurs, control is transferred to the program beginning at address MATCH. If the input byte is >47, control is transferred to the program beginning at address BIG. If none of these conditions are met, control is passed to the program beginning at address SMALL. In summary, the conditional jump instructions are among the most important in the processors instruction set, because they allow the processor to make decisions based on program condition.

3.12 Loop instructions

Loop instructions are used to set up a group of instructions to execute several times. They combine the decrement counter and transfer of control instruction Decrement register which holds the loop count by 1 at the end of each loop JNZ (jump to the start if count register is not zero) Example 3.12 Using the loop instruction, write a program segment to output 256 bytes from data table beginning at address TABLE to output port A0H. Assume DF=0 Solution LEA SI, TABLE MOV CX, 0100H AGAIN: LODSB OUT 0A0H, AL LOOP AGAIN
49

Table 3.15 loop instructions

This example shows the string and loop instructions actually perform two operations each. LODSB (load string byte) is equivalent to MOV AL, [SI] INC SI And LOOP AGAIN replaces the equivalent instructions DEC CX JNZ AGAIN The LOOPE or LOOPZ (loop if equal or zero) and LOOPNE or LOOPNZ (loop if not equal or not zero) instructions test CX and ZF. For example, LOOPE loops while equal this means that if CX0 and ZF=1, the loop will be repeated. These two forms are useful when comparing two strings or looking for a match between a CPU register and a byte or word in a data table. Note all forms the loop instruction repeat until CX=0, this means that the loop will be repeated 65,536 times if CX=0 initially.
50

3.13 Push and pop instructions

The PUSH and POP instructions use the stack area of the memory. Stack Segment (SS) is a 64K-B memory segment whose base address determined by SS register. Two CPU registers SP, and BP normally points into this area. The stack is a special area in memory used by the processor for temporary data storage. SS segment is LIFO type of memory. Data is pushed onto the stack by the PUSH source instruction. And the POP destination instruction causes the data currently on top of the stack to be popped into the destination operand. Note the stack actually grows downward with each successive PUSH instructions. Table 3.16 push and pop instructions

51

Example 3.13 PUSH CX PUSH BX

Registers should be popped off the stack in the reverse order in which they were pushed on. Before using the stack it is important that register SP be initialized to a high memory location allowing room for the stack to grow. Finally, PUSHF and POPF instructions allow the processor flags to be stored on the stack. This can be useful with interrupts and subroutines as the entire state of the machine ul (all CPU registers and flags) can be saved and then restored later.

3.14 Call and return instructions

The CALL and RET instructions allow the programmer to use a group of instructions as a subroutine or procedure that can be executed several times from within the main program. The CALL instruction is similar to an unconditional jump except that the value of IP is pushed onto the stack, Control then transfer. The subroutine must end with a RET instruction, which causes the top of the stack to be popped into IP, neatly returning control to the instruction in the main program with which it left off. The far CALL differs from the near CALL in that the value of CS (in addition to IP) is saved on the stack. For this reason a far RET instruction is used to pop CS and IP from n the stack when the far procedure has ended.

52

Table 3.17 call and return instructions

53

3.15 Software interrupts

An interrupt is a request of the processor to suspend its current program and transfer control to a new program called the interrupt service routine (ISR). The interrupt request can be initiated in hardware or software. For the 8086, applying a logic 1 to the INTR or NMI input line will initiate the interrupt request. Software interrupts are initiated by giving the instruction INT type. The processor responds by pushing the flags, CS, and IP on to the stack. It then loads new value for CS and IP from an interrupt jump table located in absolute memory from 00000 003FFH. These 1KB allow 256 different software interrupt request

54

Figure 3.4 Stack area after executing an I T type instruction. SP is the new value of register SP

Figure 3.5 interrupt jump table If an INT 23H is executed, the processor will multiply 23H by 4 (rotate left twice), resulting in the jump table address 0008CH. CS and IP will then be loaded with the double word stored in 0008CH through 0008FH (CS in the higher order word, IP in th the
55

lower order word). When ISR has finished, the IRET instruction should be executed to pop the flag register from stack (in addition to CS and IP).

400H

Type 255

3FCH Type 254

14H 10H CH 8H 4H 0H

Type 5 Type 4 Type 3 Type 2 Type 1 Type 0 Over flow Break point NMI non interrupt Trap Division error maskable

CS high byte CS low byte IP high byte IP low byte

Figure 3.6 interrupt jump table

56

Table 3.18 software interrupt instructions

3.16 Processor control instruction

Processor control instructions are used to control the operation of the processor and set or clear the status indicators. The STD (set direction flag) and CLD (clear direction flag) instructions are used to set or clear this flag. STI (set interrupt enable flag) and CLI (clear interrupt enable flag) enable or disable maskable interrupts on the INTR input line. Clearing this bit blocks all interrupts on INTR effectively masking this input.

57

There is no instruction for setting or resetting TF (trap flag), but the following sequence of instructions can be used to set TF. PUSHF MOV BP, SP OR BYTE PTR[BP+1], 01H POPF The HALT instruction will stop the processor and cause it to enter an idle loop. However, once halted it can be restarted only via a hardware interrupt or system reset. Table 3.19 processor control instructions

58

59

Chapter Four THE 8086 CUP MODULE 4.1 8086 CPU READ A D WRITE BUS CYCLE
A microprocessor endlessly follows the sequence: 1. Fetch the next instruction in sequence from memory 2. Execute the instruction 3. Go to step-1 The fetch cycle is actually a memory read operation in which the byte or word pointed to by the program counter (or instruction pointer) is transferred from memory to the instruction register in the CPU. Execution of the instruction may require additional memory or I/O read/write operation, or an internal CPU activity. In all; there are five unique operations or bus cycles possible: 1. 2. 3. 4. 5. Memory read Memory write I/O read I/O write Bus idle (internal operation not requiring access to memory or I/O)

Note that three sets of wires (or buses) are dedicated to this transferring of data between the CPU and the memory and I/O units.

4.1.1 BUS CYCLE TIMI G

Figure below illustrates bus cycle timing for the four active bus cycle types. Each cycle begins with the output of the memory or I/O port address during the T1 clock cycle. It can be a 20-bit memory address, a 16-bit indirect input output port address, or an 8-bit direct I/O address (using register DX), or an 8-bit direct I/O address. Examining the address lines only, it is not possible to determine if this is a memory or an input output address. Neither can tell the direction of the data flow. i.e., the CPU performing a read or write cycle? For this reason a control bus is required. This bus consists of the four active low signals: 1. 2. 3. 4.  MEMR  MEMW  IOR  IOW
60

Figure 4.1 memory, I/O read/write bus cycle timing During an active bus cycle the microprocessor may perform a memory read, memory write, I/O read, or I/O write operation. The control and address buses are used to specify the memory or I/O address and the direction of data flow on the data bus lines. One bus cycle contains four CPU clock periods called T-states. To see how the three buses shown work together. Consider the sequence of events that occur during a memory read bus cycle. T1. The processor out puts the 20-bit memory addresses. The data lines are open circuited and all control lines disabled. T2. The MEMR control line is driven low. The memory unit recognizes this bus cycle as a memory read and prepares to place the addressed byte or word on to the data lines.

61

T3. The microprocessor configures its data bus lines for input but takes no further action. This state is provided primarily to give the memory time to work up the data byte o r word. T4. The microprocessor now expects the data to be on the data bus lines. It latches the contents of these lines and releases the memory read control signal. This marks the end of the bus cycle. The microprocessor controls all the bus timing. The memory must be able to supply the  selected data byte or word by the time MEMR goes high during the T4-state. If it cannot do so, the CPU will read random information on the data bus lines. This will lead to unpredictable results. Note that only one control signal can be active at a given time. The processor cannot read from its memory at the same time it is outputting to an input output device. Example 4.1 Describe the contents of the address, data, and control bus lines when the instruction MOV [1000H], BX is executed. Assume DS = 09D3H and BX = 1234H Solution The instruction requires a memory write to location 1000H of the data segment. During T1 the 20-bit address bus will hold 09D30H + 1000H = 0AD30H.  During T2 the control bus signal MEMW will go low and the data bus will contain 1234H (BX).  During T4 the memory latches this data by the time MEMW returns high.

4.2 8086 CPU PI DESIG /DESCRIPTIO S

The 8086 has 40 pin dual-in-line package (DIP). It has 20-bit address bus 16-bit data bus 3-pin power and 17-pins devoted to miscellaneous control and timing functions. Time multiplexing: is a design technique in which one circuit pin has more than one function. For example the data pins (labeled AD0 AD15) are address lines during the T1 clock state, but become data lines during the T2 T4 states. A special de-multiplexing circuit is required to extract the separate data and address lines.
62

Figure 4.2 8086 CPU pin design Using time multiplexing the pin breakdown becomes 16 data and address pins 4 address (and status) pins 3 power pins 17 control and timing pins.

63

Data bus (AD0 AD15) these 16 pins form the CPUs bidirectional data bus. These lines are valid only during the T2 through T4 clock states. During T1 they hold the 16bits of the memory or I/O address. Address bus (AD0 AD15 and A16/S3 A19/S6) these 20-pins correspond to the CPUs 20-bit address, data and status lines on AD0 AD15 bus and allow the processor to access 1,048,576 unique memory locations. They are active during T1 state, switching to become the data and status lines during the T2-T4 clock states. Address latch enable (ALE) the signal output on this pin can be used to de-multiplex  the address, data, and status lines on AD0 AD15, A16/S3 A19/S6, BHE/S7. Every cycle begins with the output of ALE pulse during the T1 clock state. The 20-bit address is guaranteed to be valid when ALE switches from high to low near the end of T1. This signal can be used to strobe the address into latch. Memory input output (M/) memory and I/O signal. The 8086 does not output separate memory and I/O read and write signals. It is output early in the T1 state and   identifies the current bus cycle as a memory (M/IO= 1) or I/O (M/IO= 0) operation. Read () this active low output signal indicates that the direction of data flow on the  bus is from memory or I/O in to the processor. It can be combined with M/IOto form  MEMR and  control signals. It is output during the T2 state and removed during the IOR T4 state. The memory or I/O device is assumed to have placed the addressed byte or  word on to the data lines by the time RD returns high. Write () indicates that data is to flow from the CPU to memory or to an I/O device during T2 state. This gives the memory or I/O plenty of time to latch the data byte or  word before WR is removed during T4. Figure below shows how , , and M/IO can RD WR be combined to generate a conventional four-line control bus. Figure 4.3 indicates generating the four memory and I/O control bus signals from the 8086 , , and RD WR  M/IO outputs.

Figure 4.3 the four control bus signals

64

Clock (CLK) All events in the microprocessor are synchronized to the system clock applied to the CLK pin. The maximum frequency for the 8086 is 10MHz. the 8284A is used as a clock generator. Status (A16/S3 A19/S6 and /S7) these five status signals are output during states T2 T4. They are intended primarily for diagnostic testing purposes, as their definitions in the table below indicate. It is possible to decode S3 and S4 to provide four separate 1MB address spaces for the extra, data, code, and stack memory segments. This is shown in figure 4.4. All memory read or write operations are intercepted by this circuit, causing the appropriate physical memory block to be accessed. Table 4.1 S3 S7 status bit definitions S4 0 0 1 1 S3 0 1 0 1 Bus cycle access is to Extra segment Stack segment Code segment (or none) Data segment

S5, IF (interrupts enabled flag) S6, 0 (indicates 8086 is on the bus) S7, spare status (not used).
Extra Stack Code Data

1 MB 74LS138 S3 S4  RD  WR  M/IO  E A B 1/2

0 1 2 3

 E

 E

 E

 E

Figure 4.4 Decoding status signals S3 and S4

65

Decoding status signals S3 and S4 allows the extra, stack, code, and data segments to be located in physically separate 1MByte address space. Bus high enable (/S7) this signal is multiplexed with the S7 status indicator. It is  output during the T1 state. When BHE is low, it indicates that AD8 AD15 are involved in the data transfer. This can occur for memory or I/O word accesses or when accessing a  data byte from an odd address. BHE and A0 are typically used to select even or odd memory banks or I/O ports. Table 4.2 memory access encoding  BHE 0 0 1 1 A0 0 1 0 1 Action Access 16 bit word Access odd byte to D8- D15 Access even byte to D0- D7 No action

Data transmit/receive (DT/  ) this signal is intended to control the direction of data flow through the buffers (if any) connected to the system data bus. When low it indicates a read operation, and when high, a write operation.  Data enable (DE ) this signal intended to be used with DT/R to enable a set of bidirectional buffers connected to the system data bus. it prevents bus contention (two circuits attempting to drive thw same bus line) by disabling the data bus buffer s until the T2 state, when the address/data lines no longer hold the memory or I/O address. Minimum/maximum mode (M /) the 8086 can be operated in one of two modes called the minimum and maximum modes. The function of pins 24 through 32 changes  depending on the logic level applied to this pin. For minimum mode operation MN/MX=1 RESET: when pulsed high this input causes the 8086 to terminate its present activity and perform a reset sequence. The status of the old job is lost. Reset is normally used when first starting the system or after a system crash.   This input is used together with the WAIT instruction. If the TEST input is high when the WAIT instruction is encountered, execution of the program is suspended and  the CPU enters an idle mode. Only when TEST returns low will execution resume. Normally, this input is driven by the 8087. This prevents the CPU from accessing a memory result before the other microprocessor has finished its calculations.
66

READY the READY input is sampled on the rising edge of the T2 clock pulse. If this line is found low (not ready) an extra T3 state is inserted by the processor. The cycle repeats until the READY input is found high. The READY input is usually driven by a slowmemory device that cannot supply data as fast as required with normal CPU timing. Interrupts (I TR, MI, and ) INTR and NMI are hardware-initiated interrupt requests that function exactly as software interrupts. NMI is rising-edge triggered and INTR is an active high-level trigger. The INTR input can be masked by resetting the IF processor status bit (CLI). NMI is a non maskable interrupt that will always be serviced. As such it should be reserved for catastrophic events such as power failure or memory errors. When NMI is active, control automatically transfers to the address stored in locations 000080000BH. When INTR is active an interrupt-acknowledge cycle is performed. The interrupting device is expected to place an 8-bit type number on to the low-order data bus. Control then transfers to the address stored in locations type x 4 through type x 4 + 3. Hold and hold acknowledge (HOLD and HLDA) HOLD is an active high CPU input that causes the processor to open circuit all of its bus lines. This effectively disconnecting the CPU from its memory and I/O, allowing a second processor to access these devices. This is referred to as direct-memory-access (DMA). HLDA acknowledges the DMA request to the DMA controller. Power and ground (Vcc and G D) the 8086 requires a single +5v power source and has two ground pins.

4.3 GE ERATI G THE 8086 SYSTEM CLOCK & RESET SIG ALS
The 8086 requires a clock signal with fast rise& fall time (< 10ns), logic 0 and 1 levels of 0.5 to 0.6v and 3.9 to 5.0v, respectively, and a duty cycle of 33%. The processors RESET signal must be synchronized to the system clock and persist for at least 4T states. The Intel 8284A clock generator meets all the requirements for the clock and RESET signals. The 8086 clock signal All the activities of the 8086 are sequential and synchronized to a system clock signal. During T1 the memory or I/O address is output T2 Control signals are activated. T3 the memory and I/O are given time to respond
67

T4 the data is in put or output. Importance of clock signal Without the clock signal to synchronize these events we would have disorder. Internally, the microprocessor is designed with dynamic logic gates that require periodic refreshing or they will lose their data. The clock signal provides this refresh. For this reason the clock must never be stopped.

4.3.1 COLD STARTI G THE 8086

When power is first applied to the 8086, all its internal registers RAM contain random data. Because of this, the processor will fetch its first instruction from a random memory location (containing a random instruction), leading to an unpredictable result. The RESET input is provided for gaining control of the machine when it is first started. When this pin is driven high, most of the 8086 CPU register are rest as shown in the table. Table 4.3 CPU state following RESET CPU Flags Instruction pointer CS register DS register SS register ES register Queue Contents Clear 0000H FFFFH 0000H 0000H 0000H Empty

Because, the CS register contains FFFFH, the CPU will fetch its first instruction from physical address FFFFOH + 0000H = FFFF0H. RESET thus solves the random start address problem associated with Cold starting the processor. We must ensure that a useful program resides in memory beginning at the reset start address FFFF0H. Note that RAM cannot be used at this address. ROM is mapped in to this address space, because the content of ROM is not lost when power is

68

removed. We can be sure that the 8086 will have a useful program to execute when it is first started. There are only 16 bytes between addresses FFFFOH and FFFFFH (the end of memory). So the instruction at FFFF0H is normally a jump to some other location where a longer program resides (again in ROM). This program could be a boot strap Loader program that initializes the computer and then loads a more complex program from a disk drive (usually the operating system) in to RAM.

4.4 MICRO COMPUTER BUS-TYPES A D BUFFERI G TECH IQUES

There are three types of buses to be found in a micro computer system (not to be confused with the address, data and control buses, which are dedicated to particular task) Type 1:- one transmitter, several receives. Example, the address bus. Type 2:- one receiver, several transmitters. Example, when the processor requires reading a status port-technique called polling determining the active device. Type 3:- several transmitter and receivers. Example, the bidirectional data bus. Each of these bus types requires special buffering techniques to ensure reliable data transmission. The purpose of the buffer will be to minimize the ac and dc loading effects associated with multiple receivers and transmitters on a single bus line. For example, each receiver requires a dc load current from the transmitter. The effect of this load is to reduce the high-level output voltage (VOH). And increase the low-level output voltage (VOL) this in turn reduces the noise immunity of the system. In addition to a dc load, each receiver also presents as ac load, this is the receivers input capacitance that must be charged and discharged each time the transmitters output changes state. The effect is to increase the propagation delay time for the transmitted signal. This decreases the time available to the memory or I/O device for reading or writing data.

69

Input E 0 Input E 1

Data bus line = input

Data bus line = input

E 0 0 1

I 0 1 X

Data bus 0 1 free

Figure 4.5 tri-state buffers and its truth table Tri-state buffers (74Ls240/241/244) These contain eight buffers in one package and are the most common types. In addition to the two logic states, these buffers out put a third state called the tri-state, which is actually a high-impedance or open circuit. Note that, as a general rule, a bus buffer should be used when even the bus loading exceeds the drive capabilities of the microprocessor or when it is necessary to drive receivers off the main CPU card (due to the capacitive loading associated with edge connectors and backplane wiring in a multi card system . It is not only advantageous to use a buffer for the transmitter, but by also buffering each receiver input, the number of receivers that can be safely driven is increased. Two triWRITE state gates are required for each bi-directional bus line with separate  and  READ enables.

4.5 THE 8086 MI IMUM MODE CPU MODULE

 When the 8086 MN/MX pin is wired to +SV, the processor operates in the minimum mode. In this mode the CPU provides all the control signals for the system. The minimum mode is intended for simple single-processor systems on one printed circuit board (PCB). The maximum mode is intended for more complex systems with separate I/O and memory boards, it also supports co-processors. The 8086 minimum mode CPU module is a hardware module providing all the signals required to interface memory and I/O in a practical 8086- based micro computer system.

70

Chapter Five MAI MEMORY SYSTEM DESIG

Memory that interfaces directly to the microprocessor is referred to as main memory. It has the following characteristics: 1. Any location can be accessed at random. 2. Each byte has its own unique address. 3. Data is read or written in one CPU bus cycle. Devices like floppy-disk drive are referred to as secondary storage device. The data from secondary storage device is read byte by byte from the sane (I/O port) address.thi s means that to the CPU, each byte of data on the disk appears to be stored at the same address.

5.1 TYPES OF MAI MEMORY

There are four common types of main memory Mask-programmable readonlymemory (ROM) It is programmed at the factory according to a truth table supplied by the user. In this way the manufacturer can sell the same ROM chip to many different customers, altering only the mask that defines the diode connections. Field-programmable ROMs There are several types of ROMs that can be programmed by the user in the field. These devices are referred to as programmable read-only memories (PROMs). Fusible-link PROMs one type PROM uses a low current fusible link in series with the output. By applying a current pulse to the desired output, the fuse can be melted and a logic 1 or 0 permanently programmed. A typical application would be a boot PROM in microcomputer system. UVlight-erasable PROMs (EPROMs) The most popular types of PROM used in microcomputer systems is the erasable programmable read-only memory (EPROM). This device can be programmed, erased, and reprogrammed many times over by the user. EPROMs use a floating-gate avalanche injection MOS (FAMOS) transistor cell to store charge. Applying a special programming voltage (Vpp) causes a high electric field to be developed in the channel region of the transistor. This in turn causes electrons to jump the silicon dioxide barrier between the channel region and the floating gate.

71

During programming the select gate is given a positive bias which helps attract these electrons to the floating-gate electrode. Because the floating gate is surrounded by silicon dioxide (an excellent insulator), the injected charge is effectively trapped. Cells with trapped charge cause the transistor to be biased ON, where as those cells without trapped charge are biased OFF. Blank EPROMs have no charge and each cell stores a logic 1. The EPROM can be erased by subjecting each to ultraviolet (UV) light, which has a wave length of 2537 angstroms. The electrons on the floating gate absorb photons from the UV-light source and acquire enough energy to reverse the programming process and return to the substrate. EPROMs are packaged in special ceramic packages with quartz windows to allow erasure. In operation the EPROM window should be covered with an opaque label because normal room fluorescent lighting could erase the device. Electrically erasable PROMs (EEPROMs) There are several disadvantages to the UV EPROM. These are: 1. The device must be removed from the circuit board to be erased. 2. Byte erasure is not possible; all cells are erased when exposed to UV light. 3. The quartz window package is expensive. Because of these problems the EEPROM is developed. This device can be programmed and erased without removing the chip from its socket. In addition, both byte and bulk erasure modes are possible. Some applications of EEPROM are , although it will not replace conventional RAM, it can be used to hold programs and data that are that are subject to frequent changes: for example, inventory records, set points for NC (numerical controlled) machine tools, and motion paths for industrial robots. A particular interesting application of the EEPROM is programming via a remote data link. Using a telephone interface called a modem; the central factory can call up the EEPROM field system and transfer new data or modify the system software. Static and dynamic RAMs Two types of semiconductor RAM are popular. In static RAM four to six transistors are connected to form a simple RS flip-flop. In a static RAM, data, once entered, remain valid as long as the power supply is not turned off. On the other hand, to retain data in a DRAM, in addition to power supply, a periodic refreshing with in specific interval of time is required, because the elements are made of capacitive. Because of the refresh and address multiplexing requirements, interfacing a

72

DRAM to a microprocessor is more complex than SARM interface. However, DRAM controller chips are available to simplify this task.

5.2 I TERFACI G MEMORY

The one basic characteristic of all 8086 memory designs is the requirement to partition the memory in to two banks. One bank stores the even-addressed bytes and the other the  odd-addressed bytes. The A0 address line and BHE control signal must be used in the memory interface to select the appropriate bank as required by the current CPU instruction. Pin connections common to all memory devices are The address inputs Data outputs or input/ outputs.  Some type of selection input (chip select CS) and  At least one control input used to select a read or write operation (OE-output enabled; -write enabled) WE

Figure 5.1 pin description common to all memory Address connections All memory devices have address inputs that select a memory location within the memory device. A 2K memory device has 11 address pins (A0-A10); therefore, 11 address inputs are required to select any of its 2048 (2K) internal memory locations. The remaining nine address pins (A19A11) are connected to the inputs of a decoder. The decoder selects the memory from the many 2KB sections of the entire 1MB address range of the microprocessor. Data connections Data connections are the points at which data are entered for storage or extracted for reading. Most devices are 8-bits (a byte) wide memory.
73

 Chip select () Chip select Selects or enables the memory device. If CS input is active (a logic 0), the memory device performs a read or write operation; if it is inactive (a logic-1) the memory device cannot perform a read or write operation because it is turned off or disabled.

Figure 5.2 Interfacing 8k-byte memory to the 8086 CPU.  Control connection A ROM usually has only one control input, output enabled (OE) connection, which allows data to flow out of the output data pins of the ROM. A RAM memory device has either one or two control inputs: i) ii)  R/W or  and  (write and output enabled) WE OE

 If a memory write or read cycle is to occur, the chip select () and write enabled (WE,    R/W = 0) or output enabled (OE or R/W = 1) are active. Figure 5.2 shows that two ships are required. One stores the even bytes and connects to DB0DB7. The other stores the odd bytes and connects to DB8DB15. A13-address lines are required to access all of the 8K-bytes. AB1AB13 address lines are connected to the memory chip address lines A0A12. You must remember that AB0 and

74

 BHE are required to select the appropriate bank. Thus the interface provides a total of 16Kbytes of memory. The memory idles with all data pins open-circuited until the  input is taken low. When CS  is low, a read cycle will occur provided that  is high (disabled) and  is low (then WE OE CS used to enable the output buffers). For even byte transfer only AB0 will be low and memory-A is selected. For odd byte transfer memory-b will be selected and  only will be low. Note that  and  are BHEB WE OE  WR  and  which are generated from BHE, , and A0 pins of the MEMR driven by MEMW microprocessor as shown in the figure below.

 BHE  WR AO

  HWR (MEMW)

  LWR (MEMW)

Figure 5.3 The memory bank write selection input signal:   HWR (MEMW) high bank write  (MEMW) low bank write LWR  The address decoder must decode the unused address lines AB0AB19. Figure below shows one possibility. This circuit forces the unused address lines to be 111111B and maps the circuit to the range FC000 FFFFFH
AB14 AB15 AB16 AB17 AB18 AB19

 MEMORY SELECT

This line is low for any address between FC000 - FFFFFH

Figure 5.4 simple address decoding technique. This address decoder causes the memory interface to reside in the 16k-byte range FC000 FFFFFH.

75

5.3 ADDRESS DECODI G TECH IQUES

The 8086 microprocessor provides a 20 bit memory address that allows up to 1MB of main memory. Most memory interface, however, do not fill this entire range. This means that for a given memory design, several of the address lines are going to be unused. However, these unused lines are very important because they determine the range of the address the memory interface will occupy. An address decoder is a circuit that examines these extra address lines and enables the memory for a special range of addresses. This is an important part of any memory design, as one block of memory must not be allowed to overlap another. The decoder ranges from simple NAND gates to programmable array logic (PAL) devices.

5.3.1 THE 3-TO-8 LI E DECODER (74LS138)

One of the most common although not only, integrated circuit decoders found in many microprocessor-based systems is the 3-to-8 line decoder shown below.

Figure 5.5 pin description of 3-to-8 line decoder. For any of the decoders output to go low, the three enable inputs (G2A, G2B, and G1) must all be active. To be active the G2A and G2B inputs must both be low (logic 0) and G1 must be high (logic 1). Once the decoder is enabled the address inputs (A, B, and C) select which output pin should goes low. Only one of the eight outputs ever goes low at any time. Eight memory devices  inputs can be connected to the eight outputs of the decoder at the same time. That is why it is called a very powerful device because it selects eight different memory devices at the same time.

76

Figure 5.6 the 74LS138 3-to-8 line decoder connected to memory The 74LS138 3-to-8 line decoder can be used to provide eight consecutive memory-block select signals. A 256 KB memory array is shown in the figure 5.6. It consists of four 64Kbyte blocks of memory and a 74LS138, 3 to 8 line decoder. The low order address lines AB1AB16 select one of 64KB in each memory bank. The decoder allows only one bank to be enabled at a time. Example output 0 will be active when the enable inputs are active and A17A19 are 000. This corresponds to the address range 00000H 1FFFFH.

77

Chapter Six BASIC I PUT A D OUT PUT

The input/output port is the pathway for data as it is transferred between the microprocessor and its peripherals. There are two types of I/O ports: parallel and series. Because the microprocessor naturally works with data in 8-bit or 16-bit chunks the parallel port is the easiest to implement. All bits comprising the data word are input or out put together in parallel. In serial I/O port, the data bits are lined up and transmitted one bit at a time. This technique is slower than the parallel design, but does have certain advantages. a) Simultaneous transmission and reception can occur with only three conductor cable. b) The serial data bits can also be converted to audio tones (using circuit called a modem) and transmitted over the telephone network. The 8086 microprocessor can access information from ports as well as from the memory. There are two instructions for this purpose IN and OUT. These instructions can send data from the accumulator (AX, AL or AH) to ports or receive data from ports into the accumulator

6.1 PARALLEL I/O

The hard ware requirements for a parallel I/O port are similar to those of a memory interface. When the CPU performs an output instruction the data on the bus must be stored by the port. Similarly, when an input instruction is executed, the I/O port must gate its data on to the data bus line. Just as each memory location has its own memory address, each I/O port has its own port address. The 8086 has only two I/O instructions IN AL (or AX), PORT and OUT PORT, AL (or AX). The I/O cycle is similar to that which occurs during a memory cycle, the address bus carries the port address on A0A7 for direct I/O cycle and A0A15 for indirect I/O cycle. Just as the 8086,s memory must be divided into even- and odd-addressed memory banks, its I/O must be divided into even- and odd-addressed ports. The D0D7 data bus lines are used to transfer data from even-addressed port and D8 D15 are used for odd-addressed  ports. BHE and A0 are used to identify the type of transfer.  The condition M/IO = 0 is used to identify the current bus cycle as an I/O operation.  RD  and WR then indicate the direction of data flow.
78

  The job of the input port is to detect an input output read bus cycle (M/IO and RD = 0) decode the port address and gate the input data on to the appropriate data bus lines through tri-state gates and the output port is designed to detect an I/O bus cycle and decode the port address, but this time the data on the bus must be latched. Figure below indicates how eight-even addressed and eight odd-addressed port select signals are selected.

Figure 6.1 input output port address decoder and 8-bit output port. Example 6.1 Draw the output port interface circuit (decoding scheme) for the instruction OUT 9, AL or OUT DX, AL when DX = xx09.

79

Solution The hardware required for an output port is similar to that of an input port except that the DSP (device select pulse) signal is used to strobe a latch instead of the tri state buffers. Figure 6.1 shows a circuit that provides 16-separate select signals. BHEB and AB0 are used to select even addresses (IC3) and odd addresses (IC4). Note that for a  word select (BHEB and AB0A both low), both decoders are disabled. This might be desirable for byte-oriented peripherals that you do not want selected accidentally by an    inadvertent 16-bit I/O cycle. SEL9 is combined with IOWB in IC5 to generate the OUT9 DSP (Device Select Signal) signal which causes IC6 latch to store the data on DB8 DB15. MemoryMapped I/O The address space of the 8086 is divided into 1,048,576 bytes of memory space and 65,536 bytes of I/O space. These two regions do not overlap because memory addresses are selected with the memory commands, while the I/O addresses are selected with the I/O commands. But consider designing a one byte (or word) read/write memory. It would use latches to store the data written during a memory write cycle, and tri-state gates to drive the bus during a memory read cycle exactly the same hardware that would use for an output or input. This is the essence of memory-mapped I/O. in hardware it appears to be a conventional I/O port. But because it is mapped to a memory address, it is accessible in software using any of the memory read or write instructions. For example, the instruction MOV BH, MEMBDS becomes an input instruction (input the data at port MEMBDS to register BH). Indirect I/O is also possible. The advantage of memory-mapped I/O is the large number of instructions and addressing modes available for referencing memory when compared to the single input and output commands available with an I/O-mapped port.

6.2 Serial I/O

A serial I\O port is like a 1-bit parallel port. For example consider the figure below. Partial decoding is used such that all even (byte) ports between xxF0H and xxFEH are OUT FOH selected. The  and  DSP signals connects the DB0 data bus line to the IN F0H serial line (input output). The serial data is thus transmitted and received as bit 0 of port F0H (or port F2H, F4H, etc).

80

There are two basic methods used for serial data transmission and reception. These are asynchronous and synchronous serial communication. With appropriate software the circuit shown below can function as a serial I/O channel.

Figure 6.2 One-bit input and output port. Synchronous serial communication The synchronous data transfer scheme is the simplest of all data transfer schemes. In this scheme the processor does not check the readiness of the device. The I/O device or peripheral should have matched timing parameters. Whenever data is to be obtained from the device or transferred to the device, the user program can issue a suitable instruction for the device. At the end of the execution of this instruction, the transfer would have been completed. The synchronous data transfer scheme can also be implemented with small delay (if the delay is tolerable) after the request has been made. The mode-O input or output in 8155 or 8255 is an example of synchronous data transfer. Bisync protocol because there is no start bit, a special sync character is required in all synchronous serial formats. This character tells the receiver that data is about to follow. The USART, accordingly, must have a special hunt or search mode so that the sync character can be found.

81

Because there is no stop bit, a clock signal usually accompanies the synchronous data to maintain synchronization Asynchronous serial communication The asynchronous data transfer scheme is employed when the speed of processor and I/O device does not match. In this scheme the processor sends a request to the device for read/write operation. Then the processor keeps on polling the status of the device. Once the device is ready, the processor executes a data transfer instruction to complete the process. To implement this scheme, the device should provide a signal which may be tested by the processor to ascertain whether it is ready or not. The handshake data transfer without interrupt (mode-l and mode-2) of 8155 or 8255 is an example of synchronous data transfer. One of the most common applications for a serial I/O port is to interface the keyboard or a video display terminal (VDT). Because of the change of the data rate (number of data or character transmitted per second) between the processor and the peripheral, difficult to tell when the starts or stops, how long should each bit persist, and how are the microprocessor and peripherals synchronized an asynchronous communications protocol (set of universally accepted rules) must be established. The accepted technique for asynchronous serial communications is to hold the serial output line at logic 1 level until data is to be transmitted. Each character is required to begin with logic 0 for one bit time. This first is called the start bit and is used to synchronize the transmitter and receiver. For Example, figure below shows the standard asynchronous serial data format for 7BH 1 0
Start 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 2 stop bit | bit | one byte | | One character |

Figure 6.3 Standard asynchronous serial data format. The data byte (7BH) is framed between the start bit and 2 stop bits. The above figure illustrates how the data byte 7BF would look when transmitted in the asynchronous serial format. The data is sent least significant bit first and framed between a start bit (always a 0) and one or two stop bits (always a 1). The start and stop bits carry no information but are required because of the asynchronous nature of the data.

82

All microprocessors are capable of generating serial data without special hardware. A program can be used to output the data byte by rotating each bit to be transmitted to the bit 0 position of the accumulator and output. Recovering the serial data requires a more complex program but again no special hardware is required. The program begins by waiting for the one-to-zero transition of the start bit, once found, the middle of the bit is located by waiting for delay/2 seconds. If the input is still zero, a valid start bit is assumed and the program then waits for one additional bit time (thus sampling in the middle of all following bits). As each bit is read, it is rotated right-through the carry- and after eight reads the entire byte has been recovered. The ninth read should return the first stop bit, but if this bit is low a framing error is indicated, i.e., the program is out of synchronous with the data. If high the data byte can be saved and the program begins searching for the next start bit. Note that the receiver and transmitter data rates must be exactly matched. When setting up a serial port several parameters must be specified. The most common are: 1. Data bits /character, usually 5 to 8 2. Stop bits, one or two 3. Parity bit, used to detect single bit errors, may be specified as odd or even or no parity 4. Baud rate (data rate) One of the considerations to be made when designing or using a serial port is to select a compatible set of communications parameter for the computer and peripheral. Regardless of the type of I/O port, serial or parallel, a strategy must be developed to control or synchronize the flow of data through that port. The techniques are: Programmed input output Interrupt driven input output Direct memory access (DMA)

6.3 PROGRAMMED I PUT OUTPUT

Microcomputer system design requires that input output devices such as key boards, displays, sensors and other components receive servicing in an efficient manner so that large amounts of the total system tasks can be assumed by the microprocessor with little effect.
83

The most common method of servicing such devices is the programmed I/O approach. This is where the processor must test each device in sequence and in effect ask each one if it needs servicing. A large portion of the main program is looping through this continuous polling cycle and that such a method would have a serious detrimental effect on system throughput, thus limiting the tasks that could be assumed by the microcomputer and reducing the cost effectiveness of using such devices.

Figure 6.4 parallel printer interfacing to the 8086 using programmed input output

84

Figure 6.5 flow chart for the printer control program

85

For example, assume that a 100-character/s (cps) printer is interfaced to a parallel output port. It is capable of printing a new character every 10 ms (1/100 cps). The following output routine can be used to supply data to the printer. AGAIN: LODSB OUT DPORT, AL LOOP AGAIN ; Fetch byte to AL ; send to printer ; Do CX times.

Using this routine, the 8086 can output data at 128,205 cps. There is an obvious mismatch in the data rates of the printer and microprocessor. The printer will latch the data on the data pins DATA1- DATA8 when its  input STROBE , BUSY, and  signals form a set of handshaking signals is low. The STROBE ACKNLG exchanged between the CPU and the printer. The CPU extends its hand with the  pulse, saying hare is the data the printer acknowledges via the  ACKNLG STROBE pulse, saying I have got it. You can send me some more. BUSY indicates that the printer is busy printing a character, has some error condition, or is in an OFF-LINE state. The most important point to note about this interface is the use of the  and STROBE BUSY signals to synchronize the microprocessor and peripheral. Because the transfer of data to the printer is done under program control, the technique is referred to as programmed I/O. Polling loop is a form of loop by which the CPU continually tests the printers busy flag (external device, if they are ready). Note that, the instruction in the polling loop will be executed several times (1,666) between each printed character. It is wrong to have the microprocessor simply spinning its wheels waiting for slow printer to be done, without doing some other jobs.

6.4 I TERRUPT DRIVERS I/O

When interfacing a peripheral to a microprocessor, the real problem for the microprocessor is not knowing when the peripheral is READY. One solution is to program the CPU to repeatedly poll the peripherals BUSY/READY flag. However, this has a built-in disadvantage in that all the resources of the processor are devoted to waiting for this flag. No other task can be performed. A more logical approach would be to have the peripheral tell the CPU when it is READY. This is the purpose of the microprocessors interrupt input. At the end of each instruction the processor samples this line. If it is active, control is transferred to a special interrupt service routine (ISR). Figure 6.6 shows the CPUS response to an interrupt.

86

Figure 6.6 execution process of interrupt service routine. When an interrupt occurs, normal processing is suspended while a special interrupt service routine (SR) is executed. Normal processing resumes when this routine is completed. During time 1 the processor is assumed to be executing its main task. At time 2the peripherals READY flag causes an interrupt to occur. After finishing the current instruction at time 3, the CS, IP, and flag registers are pushed on to the stack at time 4. Control then transfers to the ISR at time 5. During time 6 the ISR is executed, terminating with the instruction IRET (interrupt return). The CS, IP, and flag registers are recovered from the stack during time 7 and the original task is resumed at time 8. Note that the 8086 has two interrupt pins, labeled INTR and NMI.

6.5 DIRECT MEMORY ACCESS (DMA)

We have seen two different methods for controlling the flow or data through a microprocessor I/O port. DMA is the third technique. Using DMA, the peripheral is synchronized to main memory, not the microprocessor. The real bottleneck in the data transfer process is the microprocessor it set. When a text file is out put to a disk drive, we are concerned with transferring of data from memory to that drive, yet with the programmed or in interrupt driven I/O approaches, that data must first be read from memory in to the CPU and then transferred to the disk drive. The microprocessor is an unnecessary middle man in this process, with the result that the transfer rate is decreased. The DMA approach is to turn off the processor and let the disk drive access the data file in memory itself. This is called Direct Memory Access (DMA). Note that, in the minimum mode two control signals are available: HOLD and HLDA. Figure below shows how these signals are used by the DMAC.

87

Figure 6.7 A DMA controller interface The DMA controller allows the peripherals to interface directly with memory without CPU intervention. This allows the data transfer rate to approach the access time of the memory. Table 6.1 8086 bus condition during HOLD (minimum mode) Signal AD0- Ad15 A16/S3- A19/S6  RD  M/IO  WR  INTA  DT/R  DEN ALE HLDA condition

Open circuit

Low High

The cycle begins with the peripheral requesting service via the DAMRQ (DMA request) input of the DMAC. The DMAC, in turn, drives the 8086s HOLD input high, requesting that the CPU enter a HOLD state. The processor responds by finishing the current bus cycle (if any) and then open circuits (Tri-states) its address, data, and (most) control signals as shown.

88

HLDA is output high by the 8086, acknowledging the hold request. In a system with address, data, and control bus buffers, HLDA is used to disable these buffers so that the CPU is completely disconnected from the memory and I/O. Upon receiving HLDA, the DMAC applies DMACK (DMA acknowledge) to the peripheral requesting service normally via the chip select input of the peripheral. The DMAC is now in control of the system outputting all the control and address bus signals just as if it were the system processor. The DMAC is normally programmed by the 8086 prior to the DMA operation for particular type of transfer. For example, it might be programmed to transfer 100 bytes from memory beginning at address 1000:0000H to I/0 port A3H. when the DMAC takes  over the buses, it chip selects the output port at A3H, drives the  and MEMR control IOW signals low, and then sequentially out puts the address for each of the 100 bytes to be transferred. Note that the data moves directly from memory to the I/O port not through the DMAC. This allows a very high transfer rate.

89

Chapter Seven PERIPHERAL CO TROLLERS FOR THE 8086

Peripheral interfacing refers to hardware and software techniques utilized to control the flow of data between a microcomputer and its peripherals. The actual data path may be serial or parallel. The synchronization technique may use polling, interrupts, or DMA.

7.1 THE 8255 POGRAMMABLE PERIPHERAL I TERFA CE (PPI)

The 8255 is a general-purpose parallel I/O interfacing device. It provides 24 I/O lines organized as three 8-bit I/O ports labeled A, B, and C. Pin definitions and a block diagram are provided in the figures below.

Figure 7.1 Pin definition of the 8255 Chip Programming of the ports is restricted to bytes or nibbles (4 bits). Each of the ports A or B can be programmed as 8 bit input or output port. Port C can be divided in half with the top most or bottom-most 4 bits programmed as inputs or out puts. Individual bits of a particular port cannot be programmed. In the figure below twenty-four I/O pins are provided, grouped as three 8-bit I/O ports. There is one-bit control port.

90

Figure 7.2 (a) block diagram and (b) pin description of 8255 (PPI). The 8255 is a very versatile device. It can be programmed to look like three simple I/O ports (called mode 0), two handshaking I/O ports (called mode 1), or a bidirectional I/O port with five handshaking signals (called mode 2). The modes can also be intermixed. For example, port A can be programmed to operate in mode 2 while port B operates in mode 0. There is also a bit set/reset mode that allows individual bits of port C to be set or reset for control purpose. Table 7.1 shows how the four internal registers (or ports) are accessed for read and write operations by the CPU. Two address input lines, labeled A0 and A1 determine which register is to be selected. For example, the control port is accessed when A1A0 = 11. WR The  and  input determine the direction of data flow over the chips 8-bit RD bidirectional data bus. Note that each of the data ports can be read from or written to. The control port, however, can only be written to. The byte written to this port determines the mode of operation of the three data ports.

91

Table 7.1 Truth table for the 8255A PPI A1 0 0 1 0 0 1 1 x 1 x A0 0 1 0 0 1 0 1 x 1 x  RD 0 0 0 1 1 1 1 x 0 1  WR 1 1 1 0 0 0 0 x 1 1  CS 0 0 0 0 0 0 0 1 0 0 Input operation (READ) Port A data bus Port B data bus Port C data bus Output operation (WRITE) Data bus port A Data bus port B Data bus port C Data bus control Disable function Data bus tri-state Illegal condition Data bus tri-state

Similar to the memory device, the 8255 can be accessed only when its  (chip select) CS input is low. Thus this input is normally driven by an address decoder to assign the device to a specific range of I/O addresses.

7.1.1 I TERFACI G THE 8255

The address decoder is similar to that used when interfacing memory and provides even and odd port-select signals. These are, in turn, used to chip select an even 8255 (interfaced to the low-order data bus lines) and an odd 8255 (interfaced to the high order data bus lines). Example 7.1 Determine the 8255 port addresses in figure 7.3 for direct I/O instructions and indirect I/O instructions. Solution, the direct I/O instructions supply an 8 bit fixed address as part of the  instruction on AB0-AB7. The decoding in figure 7.3 will cause PORT SEL to be active over the range. AB7- AB0 = 00000XXX = 00H - 07H

92

Figure 7.3 interfacing the 8255 to the 8086 maximum-mode CPU module. Two 8255s provide three consecutively addressed 16-bit I/O ports. IC3 combines the     PORT SEL signal with AB0 and BHE to produce EVEN PORT SEL and ODD PORT SEL. There will be four combinations of each of these signals because they do not include AB1  and AB2. For example, EVEN PORT SEL will be active if the direct port address is 0, 2,  4, or 6. Similarly, ODD PORT SEL will be active if the direct port address is 1, 3, 5, or 7. Because AB1 and AB2 are used to select one of the four ports within the 8255, the four   combinations of the EVEN PORT SEL and ODD PORT SEL signals correspond to port A, B, C and the control port of the 8255. This is shown more clearly in table 7.2. When indirect I/O instructions are given, register DX is used to hold a 16-bit port address. Because AB8-AB15 are not decoded, the circuit is partially decoded for these instructions. The port address range is 0000H 0007, 0100H - 0107H, 0200H - 0207H, ..FF00H - FF07H.
93

Table 7.2 8255 port addresses for the interface in figure 7.3 AB7 AB3 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 AB2 0 0 1 1 0 0 1 1 0 0 1 1 AB1 0 1 0 1 0 1 0 1 0 1 0 1 AB0 0 0 0 0 1 1 1 1 0 0 0 0 BHE 1 1 1 1 0 0 0 0 0 0 0 0 Port 0 2 4 6 1 3 5 7 0 and 1 2 and 3 4 and 5 6 and 7 Description Port A Port B Port C Control port Port A Port B Port C Control port Port A Port B Port C Control port Comment Even port on DB0 - DB7

Odd port on DB DB15

Be careful not to be misled by the interface in figure 7.3. It is not necessary to interface pairs of 8255s to the 8086. If an 8-bit I/O port is sufficient, the even or odd-addressed PPI chip (and corresponding OR gate-IC3) can be deleted. The resulting interface will still span eight consecutive port locations, but every other address will be empty. Finally, the 8255 circuit provides three 16-bit I/O ports and requires only five chips. In addition, each of the six 8-bit ports can be individually programmed as an input or an output port.

7.1.2 SPECIFYI G THE CO TROL WORD (MODE SELECTIO )

There are three basic modes of operation that can be selected by the system software: Mode 0 Basic input/output Mode 1 Strobed Input/output Mode 2 Bi-directional Bus Applying an active-high pulse to the 8255s RESET input will leave the three data ports programmed as inputs. Thus the first few instructions of the applications software will normally program the PPI for the desires operating mode and I/O configuration. This will require one to three bytes to be out put to the control port. Figure below shows how the control world is formed. Bit 7 determines if a bit set/reset or mode definition byte is to be written. The bit set/reset function is not really a control word (it does not alter the previously specified operating mode). Instead, it allows individual bits of port C to be set or reset.

94

Figure 7.4 control words of 8255, when bit 7 = 0, a bit set/reset operation is indicated When bit 7 of the control byte is a 0, one of three operating modes can be specified the three data ports are separated into two groups, labeled group A and B. The ports in group A can be programmed for any of modes 0, 1, or 2. The ports in group B can be programmed for mode 0 or 1 only. Example 7.2 Write the 8086 initialization routine required to program both 8255s in figure 7.4 for mode 0 with, port A an output and port Band C inputs. Solution in figure 7.4 the control word is formed as 10001011=8BH The direct or indirect I/O instructions can be used by duplicating the code in both halves of register AX, both PPI chips can be programmed simultaneously. The program is as follows MOV DX, 0006H ; DX points at ports 6and 7 MOV AX, 8B8BH ; Control word duplicated in AL and AH OUT DX, AX ; Write AL to even PPI and AH to odd PPI. One of the most powerful features of the 8255 is that only one control byte is required to program the mode selection-this is matter how complex the configuration may be.

95

Figure 7.5 control words of 8255 when bit 7 = 1, any of the modes 0, 1, or 2 can be programmed.

7.1.3 BIT SET/RESET

When bit 7 of the 8255 control word is a 0, a bit set/rest operation will be performed. In this mode any one bit of port C can be set to a logic 1 or reset to a logic 0. Note that only one bit can be set or a time. One of the advantages of this mode is that individual bits of port C can be changed without changing any of the others. This is important when port C is used to control the ON/OFF status of several external devices. The device connected to PC4 can be turned on without affecting the status on any devices connected to the other seven outputs. The bit set/reset mode also lends itself to the easy generation of strobe pulses consider the following instruction sequence. MOV AL, 00001001 OUT CTRL_PORT, AL DEC AL

; Set PC4 high

96

OUT CTRL_PORT, AL ; Reset PC4 The bit set/reset function is used in modes 1 and 2 to enable interrupt outputs available in these modes. This will be covered later in this section. To communicate with periphera1s through 8255A, three steps are necessary. 1. Determine the addresses of ports and control register from the chip select logic. 2. Write a control word into the contro1.register. 3. Write instructions to transfer data to the peripherals through ports A, B, and C.

7.1.4 MODE 0: SIMPLE I PUT OR .OUTPUT.

The I/O features of this mode are: Ports A, B &C are programmed for simple I/O. Outputs are latched, and Inputs are not latched. Ports do not have handshake or interrupt capability. Example, twelve DIP switches are interfaced to 8085A via port B and port CL. Twelve LEDs are interfaced via port A and port CL as shown below.

7.1.5 MODE 1: STROBED I/O

Mode 1 is intended for handshaking and interrupt-driven I/O interfaces. In this mode ports A and B are programmed as data ports and Port C is programmed to carry status signals. One of the unique features of this mode is that data transfers can take place without direct CPU intervention. There are four possible configurations for the 8255 when operated in this mode. These correspond to the four combinations of ports A and B as inputs and out puts. It is possible to program port A for mode 1 while using port B in mode 0. Input port timing. When port A or B is programmed as an input port, three control  signals are dedicated to supporting data transfers with this port. These are IBF, STB, and INTR. When the peripheral device has data for the microprocessor, it places that data on  the port A or B input lines and then pulses the 8255 STB input. The PPI replies by latching this data and raising its IBF (input buffer full) line. This is a signal to the peripheral that data has been latched but not yet read by the microprocessor.

97

Figure 7.6 Interfacing 8255 I/O Ports in Mode 0 If the INTE (interrupts enabled) bit of the input port has been set, IBF will also cause the INTR output of that port to go high. The processor now has the choice of polling the IBF line- by reading the mode 1 status word at port C or letting INTR generate an interrupt, thereby alerting the processor that input buffer is full. In either case the processor should branch to a routine that reads the data port. The   falling edge of RD causes the 8255 INTR output to be reset and the rising edge of RD resets IBF. The data transfer in now complete and the peripheral (detecting IBF low) can strobe in the next byte of data.

98

(a)

(b)

(c) Figure 7.7 (a) input configuration; (b) control word; (c) status word of the 8255A in Mode 1 (Strobed input)

99

Output port timing:- when ports A or B are programmed as model 1 output ports, three  ACK lines of Port C are dedicated to supporting this function: OBF, , and INTR. Their word descriptions are also provided in figure 7.8 illustrates output port timing.

(a)

(c) Figure 7.8 (a) Output Configuration; (b) control word; (c) status word of the 8255A in Mode 1 (Strobed output).

100

Assuming that data has been previously written to one of the data ports, the peripheral  monitors OBF (output buffer full). When this line is low, data is available to be read by   the peripheral. Using OBF as a STROBE input, the peripheral latches the data byte and OBF responds with an  (acknowledge) pulse. The falling edge of this pulse sets  high, ACK and if INTE is high, the rising edge causes INTR to also go high.  Again the CPU has the choice of polling or interrupts. OBF can be polled by reading the mode 1 status word at port C. INTR can be used to request an interrupt alerting the CPU  that OBF is high; that is, the peripheral is ready for more data. In either case, the  processor should write a new byte of data to the output port. The falling edge of WR will reset INTR, and there rising edge of  will force  low. The periphery monitoring WR WR , can latch the new data byte and the cycle repeats. OBF

Figure 7.9 interfacing the 8255A in mode 1 (strobed input/output) Model 2 Strobed Bidirectional I/O When operated in mode 2, port A of the 8255 becomes a bidirectional data port supported by five handshaking signals. The handshaking signals are identical to those provided in mode 1 except that they now refer only to port A. This particular mode of operation is useful when transferring data between two computers. When port A is programmed to operate in mode 2, port B can operate in mode 0 or mode 1. If programmed for mode 0, PC0PC2 can be programmed as mode 0 or mode inputs or out puts. If port B is programmed for mode1, PC0-PC2 becomes handshake signals for this port.
101

Considering all the possible combinations, there are four configurations of the 8255 in mode 2. As an example, if we choose to program port A for mode 2, port B as a mode 0 input port, and PC0-PC2 as mode 0 output pins, the control word is 11XXX010. Input port timing. The sequence of events as a data byte is first transferred to the 8255 by the peripheral and then back to the peripheral by the 8255. The peripheral begins outputting a byte to the 8255. 1. Data is output by the peripheral.  2. The peripheral applies a STB pulse to the 8255. 3. When the data is latched, IBF goes high.  4. After STB returns high with IBF still set, INTR goes high, requesting an interrupt if this feature is used. 5. Polling of interrupts can now be used to service the peripheral. The 8255 buffer is  read when RD resets INTR.  6. The falling edge of RD resets INTR. 7. The rising edge of  resets IBF. RD Output port timing:- The following sequence occurs as the processor outputs a byte of data to the peripheral through the 8255. 1. Data is output by the processor and latched by the 8255 (note that the peripheral bus is in a high- impedance state at this time.)   2. The rising edge of WR caused OBF to switch low (the output buffer is full). ACK 3. The peripheral acknowledges  by causing  to go low. OBF  the 8255 release its data onto the bus. 4. On the falling edge of ACK 5.  returns high the output buffer is empty. OBF 6. The rising edge of  sets INTR, requesting an interrupt it this feature is used. ACK 7. Polling or interrupts can now be used to write the next data byte to the 8255. A Subtle point concerning mode 2 operation is that only a single INTR output is available. This raises the question of how the processor can determine if the interrupt requires data to be read or written, that is, who requested the interrupt? Two solutions are possible. One is to use software to poll the mode 2 status word as shown in figure 7.10. In this way IBFA and  can be tested to determine which one requested the interrupt. Control is OBFA then transferred to the proper routine.

102

Figure 7.10 8255 mode 2 status words.  A hardware solution is also possible. The interrupt request can be combined with OBF of IBF to generate two separate interrupts. These could be connected to the interrupt Inputs of the 8259A PIC (programmable interrupt controller). The PIC would then vector each to its own service routine. The 8259A is discussed later in this chapter. Note that it is possible to mask interrupts generated by BIF or . This is done by OBF resetting INTE 1 or INTE 2 with a bit reset operation. The same bits must be set if interrupts are to be enabled. Using mode 2 to interface two microcomputers Most microcomputer peripherals are not bidirectional and thus are interfaced to the 8255 using modes 0 or 1. However, mode 2 can be useful when it is desired to interface two microcomputer over a common (bidirectional) data bus. Figure 7.11 illustrate such a circuit

Figure 7.11 interfacing two computers using mode 2.

103

When operated in mode 2 the 8255 can be used to interface two separate microcomputer systems. To the slave CPU, the master CPU appears to be an 8-bit input and output port.    The 8255 is connected to the master CPU via the CS and RD and WR inputs. It is then programmed for mode 2 operation. The bidirectional port A bus is connected directly to  the slave CPUs 8-bit data bus. In this example the IBF and OBF status bits are connected to the slave as bits D0 and D1 of input port Y. Thus the instruction IN AL, PORT Y. can be used by the slave to poll the master CPU and determine if data should be input or output. When the master has data to be out put to the slave, it first checks  (via the mode 2 OBF status word at port C) and if high, outputs the byte to port A. The slave, polling  via OBF  input y, detects OBF = 0 and performs an input instruction from port z (IN AL, PORT-Z) Note that the IN Z DSP causes the 8255 to place its data on to the port A data lines (via  ) and also causes OBF to return high. In this way full handshaking is achieved ACK between the master and slave CPUs. When the slave has data to be sent to the master, it first polls input port Y. If IBF is low, the 8255s input buffer is empty and ready to receive data. The slave then executes an output instruction to port X (OUT PORT-X, AL). The OUT X DSP strobes the 8255, causing it to accept the data and force IBF high. The master CPU can then poll its mode 2 status port and input the data from port A when IBF is high. This read cycle will then reset IBF and another byte can be transferred. Some applications for this interface are: The slave CPU can be thought of as an I/O processor. For Example, it might be programmed to take temperature samples once every 5 minutes for 24 hours. At the end of this time it will have stored 288 temperature samples in its memory. The master, busy with other tasks, can now read all 288 samples from the slave and process this information. In this way the master need not be tied up with the nitty gritty details of the temperature interface. In fact, the slave could be programmed to preprocess the data and supply only the mean, or the extremes, if desired. In another application the salve CPU could be thought of as a print buffer. Each time the master is called on for a print job it can transfer the data to be printed to its slave CPU (at high speed via the port A parallel interface between the two CPUs). The slave can then print the data at the rate required by the printer, while the master busies itself with some other task.

104

7.2 THE 8251A U IVERSAL SY CGRI OUS/ASSYCHR OUS RECEEIVER/TR ASMETER (USART)
Peripheral interfacing may involve a parallel or serial data path. As we have seen, the 8255 PPI simplifies the task of designing a parallel interface and is directly compatible with a polled or interrupt-driven control scheme. The 8251A USART provides a similar function when a serial interface is required. It provides two basic functions. In the transmit mode it serializes the parallel data output by the processor, automatically inserting start stop, and parity bits (synchronous mode), or sync characters (synchronous mode). In the receive mode it converts the incoming serial data to parallel and checks for parity, framing, and overrun errors. The 8251A has an 8bit bidirectional data bus, allowing the microprocessor to program its function via one to three control bytes

Figure 7.12 block diagram for the I TEL 8251A USART

105

Figure 7.13 pin descriptions for the I TEL 8251A USART.

7.2.1 I TERFACI G THE 8251A

Figure 7.11 provides a block diagram and pin description for the 8251A. Note that a separate receiver and transmitter are provided, each with their own clock inputs (RxC andTxC). RxD is the serial data input and TxD is the serial data output. The RxRDY and TxRDY status signals indicate that the receiver and transmitter data buffers are ready to be read or written, respectively. These lines can be polled to synchronize the processor to the data rate of the USART. For this purpose, the pins are duplicated in an internal status port. SYNDWT/BD is a signal that goes high when the sync character has been detected while operating in the synchronous mode. The processor can poll this signal, and when high, begin inputting characters (polling RxRDY). In the asynchronous mode SYNDET/BD indicates a break condition. This is a continuous logic 0 level on the received line (RxD). It is sent by a receiver to the transmitter to request a break in transmission perhaps because of an error condition. SYNDET/BO is also available via the internal status port. All parallel data exchanged between the CPU and USART travels over the eight bidirectional data bus lines D0-D7. The RD and WR inputs control the direction of data flow. As with the 8255, the CS input must be low for the chip to be selected. The receiver and transmitter, however, continue to function independent of the CS input. Figure 7.14 shows an interface between the 8251A and the 16-bit 8086 microprocessor. In this circuit a data bus multiplexer is used, routing odd port accesses through IC1, and even port accesses through IC2. Note the USART C/D input. When this input is low, the
106

internal data port is selected. When high, the control port is chosen. Because of the multiplexer, AB0 can be used to select these ports. Full decoding is provided for all 16 I/O address lines such that the USART is mapped to consecutive ports 0070H and 0071H (selected by AB0). Tables 7.3 summarize the read and write functions of each of these ports. Table 7.3 8251A control logic truth table    C/D RD WR Port address Function 0 0 1 1 0 1 0 1 1 0 1 0 70H 70H 71H 71H Read data byte Write data byte Read status byte Write control byte

Without the multiplexer, D0-D7 of the 8251A would have to be connected to one side of the 8086s data bus or the other. The resulting circuit would then be mapped to two consecutive even addresses (say, 70H and 72H) or two consecutive odd addresses (say, 71H and 73H). CTS Figure 7.12 also shows the four modern control signals: , . , and . Except DSR DTR RTS , these signals are general purpose inputs and not affect the operation of the for CTS 8251A in any way. They can be controlled via the internal status port (discussed later in this section). , however, must be low if the 8251A internal transmitter is to be CTS enabled. There is no similar receiver enable. The CLK input shown in figure 7.12 is required by the 8251A for internal timing, but no external inputs or outputs are related to this signal. It must have a frequency of 30 times that of the asynchronous receiver or transmitter clock and at least 4.5 times the asynchronous receiver or transmitter clock frequency. The maximum clock frequency is 3.125MHZ. In this example the 8284AS PCLK (peripheral clock) is used. This signal has a frequency of onehalf the system clock frequency and is 2.5 MHz for an 8086 processor. The 8251A has tRD of 200 ns maximum write pulse width of 250 ns. This means that one wait state will be required with the buffered 8086 minimum mode CPU configuration. No wait states are required in the other modes or configurations. As with the 8255, the advanced write command must be used for maximum mode interfaces.

107

Figure 7.14 interfacing the 8251A to the 8086 microprocessor maximum-mode CPU module. The data bus multiplexer allows the chip to occupy two consecutive I/O port locations. Most peripheral controller chips are interfaced without the data bus multiplexer. The circuit in figure 7.14 is intended as an example when bus multiplexing is desired.

108

7.2.2 GE ERATI G THE ASY CHRO OUS BAUD RATE CLOCK

The baud rate clocks of the receiver and transmitter do not have to be exactly matched when the USART is operated asynchronously, However, it is important that the clock frequency will change with precludes the use if R oscillators and similar circuits whose frequency will change with temperature and component aging. There are three different approaches or circuits for generating the baud rate clock signal. Each circuit uses a crystal time base for accuracy and stability. The first circuit is simplest but may require a nonstandard crystal to achieve a particular baud rate. For example, at 1200 baud and assuming a 16 x clock rate (the baud rate clock is normally 16 times the bit rate), the crystal frequency must be 16 x 1200 = 19,200 Hz. Another disadvantage of this circuit is that it is good only for one baud rate. The second circuit uses the crystal oscillator in the 8284A clock generator to establish a stable base frequency. A frequency divider is then required to step this frequency down to the desired frequency. For example, PCLK operates at 2.5 MHz, which when divided by 130, yields 19,230 Hz. This in turn yields a baud rate of 1201 assuming a 16 x clock. The problem with this circuit is that depending on the base frequency, some baud rates may not be achievable. For example, 9600 baud requires a 153,600Hz clock (assuming 16x). This in turn requires a divided-by16.276 counter. The best solution is the third circuit which uses single chip that combines the features from the previous two circuits. Using a crystal time base for stability, its 1.8432MHz base frequency can be divided by integers to achieve 10 different baud rates all within 0.1%. The 8251A can be programmed to accept a 16 x or 64 x baud rate clocks. This feature can be taken advantage of to switch between two different baud rated with the same clock frequency. Example 7.3 What frequency is required for a baud rate of 1200, assuming that the 8251A is programmed for a 16x clock? What does the baud rate become if the 8251A is reprogrammed for a 64x clock? Solution for 1200 baud the clock frequency must be 1200x16=19,200Hz. Now if the USART interprets this as a 64xclock, the baud rate becomes 19,200/64= 300 baud. In the asynchronous mode the baud rate is limited to 19,200 using a 16xclock. Using a 64xclock, the maximum baud rate is 9600. The latter restriction is imposed due to the CLK inputs maximum frequency specification. In the synchronous mode the 8251A baud rate clock is limited to 64 kHz (a 1 x clock must be used). Application The advantages of serial data transmission versus parallel have already been mentioned. In most cases, however, the TTL levels on the serial in and out lines must be
109

translated to EIA (electronics industries associates) RS-232C specifications. This is (typically) -12V for a logic 1 and +12V for a logic 0. Special drivers and receivers are available for this purpose. May computer peripherals use the asynchronous serial RS-232C format, including printers, plotters, and modems. By following this standard, equipment from several different manufactures can readily be interfaced. Another application for asynchronous serial that should not be overlooked is remote control, after translating the USARTs TTL levels to RS-232C levels, the serial data can be transmitted for several hundred, even thousands of feet, to a remote location. Using an 8-bit data byte, 256 devices could potentially be controlled using only a two-conductor (signal and ground) cable.

7.2.3 PROGRAMMI G THE 8251A FOR THE ASY CHRO OUS MODE
When programming the 8251A, the following sequence must be followed: 1. Reset the chip (via external input or internal control byte). 2. Write the mode instruction to the control port. 3. Write the command instruction to the control port.

Figure 7.15 (a) Asynchronous mode instruction word format; (b) synchronous mode command word format.
110

A reset command must be used to start the initialization sequence. The following command will be interpreted as a mode instruction. After this byte has been written, all further writes to the control register will be interpreted as command instructions. The only way to return to the mode instruction is to apply a reset pulse or write a command byte with bit 6 high.

Figure 7.16 8251A status register Example 7.4 Write the initialization routine required to program the 8251A USART for asynchronous transmission with 7 data bits, 2 stop bits, and odd parity. Select a 16 x   clock and program DTR and RTS to be low. Solution the program is as follows: MOV AL, 01000000B OUT 71H, AL MOV AL, 11011010B ;reset command ;control port ;mode instruction: ;7 data, 2 stop, odd parity, 16 x
111

;control port ; command instruction   ;RTS and DTR low, error reset, enable OUT 71H, AL ;command port IN AL, 70H ;dummy read to clear receiver The receiver enable (bit 2 of the command instruction) only inhibits the RxRDY flag not the receiver itself. Thus it is possible for the receiver to have captured a character before or during the initialization routine. The dummy read ensures that the receiver holding register is clear. Once initialized, the USART will automatically begin looking for the start bit of any incoming serial data. Similarly, the transmitter will serialize any data written to the transmitter buffer (output port 70H). However, you must not forget the need to synchronize the processor to the data rate of the USART. For example, even at 19,200 baud, more than 0.5 ms is required to transmit or receive one character (assuming 8 data bits, 1 start, and 1 stop bit). This is a very long time to the processor. Figure 7.16 shows the 8251A status bit definitions obtained when the control port is read. Pay particular attention to TxRDY and RxRDY. Data should not be output unless TxRDY is high, nor should received data be input until RxRDY is high. By polling these pins the processor can be synchronized to the data rate of the peripheral.

OUT 71H, AL MOV AL, 00110111B

7.2.4 PROGRAMMI G THE 8251A FOR THE SY CHRO OUS MODE

The 8251A is a character-oriented serial device and is compatible with the bisync synchronous communications protocol. This is a technique in which the serial data is transmitted framed between sync characters instead of sync bits. The advantage is a much higher character rate because fewer bytes are devoted to maintaining synchronization. When operated in the synchronous mode the 8251A clock must be set for 1 x operation (bits D0 and D1 of the mode instruction must be 0). The clock signal must also accompany the data, either as an additional conductor in a hard-wired system, or encoded with the data when used with a synchronous modem. This is because the receiving and transmitting clock rates must match exactly (0.1%). When programming the 8251A for synchronous mode operation, the following sequence must be followed: 1. 2. 3. 4. Reset the chip (via external input or internal control byte). Write the mode instruction to the control port. Write one or two sync characters to the control port. Write the command instruction to the control port.

112

As with the synchronous mode, the mode instruction can be written immediately after a reset. Following this instruction, the USART expects one or two sync characters to be specified. The next (and all following) writes will be interpreted as command instructions. The format for the mode instruction format does not change from that shown in figure 7.15. After programming the USART for the synchronous mode, the serial output line will be  high (marking) until CTS goes low. At this time the contents of the transmitter buffer will be serialized and transmitted. Normally, this will be one or two sync characters. Polling TxRDY, the processor begins outputting the data to be transmitted. If at any time the transmitters buffer becomes empty, the SYNC characters will automatically be inserted by the 8251A. This is done to maintain synchronization because of the 1 x clock, one data bit is transmitted with each clock pulse. In the receive mode the final command instruction should set bit 7, requesting the 8251A to enter the hunt mode. As each new bit is shifted into the receiver buffer, the resulting character is compared against the sync character(s), if no match is found, a new bit is input. SYNDET/BD goes high to indicate synchronization when the characters match (two contiguous characters if two sync bytes have been specified). Data can now be input by the CPU polling RxRDY, as in the synchronous mode.

7.3 PROGRAMMABLE I TERRUPT CO TROLLER (8259A)

The Intel 8259Aprogrammable interrupt controller handles up to eight vectored priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses NMOS technology and requires a single +5V supply. Circuitry is static, requiring no clock input. The 8259A is designed to minimize the software and real time overhead in handling multi-level priority interrupts. It has several modes, permitting optimization for a variety of requirements. The 8259A is fully upward compatible with the Intel 8259. Software originally written for the 8259 will operate the 8259 in all 8259A equivalent modes.

113

(a)

(b) Figure 7.17 (a) block diagram (b) pin configuration of 8259

114

Table 7.4 pin description of 8259A Symbol Vcc GND  CS Pin No. 28 14 1 Type Name and function I I I Supply: +5v supply. DROUND   CHIP SELECT: a low on this pin enables RD and WR communication between the CPU and the 8259A. INTA functions are independent of CS. WRITE: a low on this pin when CS is low enables the 8259A to accept command words from the CPU. READ: a low on this pin when CS is low enables the 8259A to release status onto the data bus for the CPU. BIRECTIONAL DATA BUS: control, status, and interrupt-vector information is transferred via this bus. CASCADE LINES: the CAS lines form a private 8259A bus to control a multiple 8259A structure. These pins are outputs for a master 8259A and inputs for a slave 8259A. SLAVE PROGRAM/ENABLE BUFFER: this is a dual function pin. When in the buffered mode it can be used as an output to control buffer transceivers (EN). When not in the buffered mode it is used as an input to designate a master (SP=1) or slave (SP=0). INTERRUPT: this pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the CPU, thus it is connected to the CPUs interrupt pin. INTERRUPT REQUEST: asynchronous inputs. An interrupt input is executed by rising an IR input (low to high), and holding it high until it is acknowledged (edge triggered mode), or just by a high level on an IR input (level triggered mode). INTERRUPT ACKNOWLEDGE: this pin is used to enable 8259A interrupt vector data onto the data bus by a sequence of interrupt acknowledge pulses issued by the CPU. A0 ADDRESS LINES: this pin acts in conjunction with    the CS, WR, and RD pins. It is used by the 8259A to decipher various command words the CPU writes and status the CPU wishes to read. It is typically connected to the CPU A0 address line (A1 for 8086, 8088).
115

 WR  RD D7-D0 CAS0CAS2 /EN SP 

2 3 4-11 12,13,15

I I I/O I/O

16

I/O

INT

17

IR0IR7

18-25

 INTA

26

A0

27

The 8259A is a device specifically designed for use in real time, interrupt driven microcomputer systems. It managed eight levels or requests and has built in features for expandability to other 8259As (up to 64 levels). It is programmed by the systems software as an I/O peripheral. A selection of priority modes is available to the programmer so that the manner in which the requests are processed by the 8259A can be configured to match his system requirements. The priority modes can be changed or configured dynamically at any time during the main program. This means that the complete interrupt structure can be defined as required, based on the total system environment. I TERRUPT REQUEST REGISTER (IIR) A D I -SERVICE REGISTER (ISR) The interrupts at the IR input lines are handled by two registers in cascade, the interrupt request register (IRR) and the in-service (ISR). The IRR is used to store all the interrupt levels which are requesting service; and the ISR is used to store all the interrupt levels which are being serviced. PRIORITY RESOLVER This logic block determines the priorities of the bits set in the IRR. The highest priority is selected and strobed into the corresponding bit of the ISR during  pulse. INTA I TERRUPT MASK REGISTER (IMR) The IMR stores the bits which mask the interrupt lines to be masked. The IMR operates on the IRR masking of a higher priority input will not affect the interrupt request lines of lower quality. I T (I TERRUPT) This output goes directly to the CPU interrupt input. The Voh level on this line is designed to be fully compatible with the 8080A and 8086 input levels.  (I TERRUPT ACK OWLEDGE)  Pulses will cause the 8259A to release vectoring information onto the data bus. The INTA format of this data depends on the system mode of the 8259A. DATA BUS BUFFER This 3-state, bidirectional 8-bit buffer is used to interface the 8259A to the system data bus. Control words and status information are transferred through the data bus buffer. READ/ WRITE CO TROL LOGIC The function of this block is to accept output commands from the CPU. It contains the initialization command word (ICW) registers and operation command word (OCW) registers which store the various control formats for device operation. This function block also allows the status of the 8259A to be transferred onto the data bus.
116

 (CHIP SELECT) A LOW on this input enables the 8259A. No reading or writing of the chip will occur unless the device is selected.  (WRITE) A LOW on this input enables the CPU to write control words (ICWs and OCWs) to the 8259A.  (READ) A LOW on this input enables the 8259A to send the status of the interrupt request register (IRR), in service register (ISR), the interrupt mask register (IMR), or the interrupt level onto the data bus. Ao This input signals is used in conjunction with and  signals to write commands into WR RD the various command registers, as well as reading the various status registers of the chip. This line can be tied directly to one of the address lines. THE CASCADE BUFFER/COMPARATOR This function block stores and compares the IDs of all 8259As used in the system. The associated three I/O pins (CASO-2) are outputs when the 8259A is used as a master and are inputs when the 8259A is used as a slave. As a master, the 8259A sends the ID of the interrupting slave device onto the CASO-2 lines. The slave thus selected will send its preprogrammed subroutine address onto the data bus during the next one or two consecutive pulses. INTA

7.3.1 I TERRUPT SEQUE CE

The powerful features of the 8259A in a microcomputer system are its programmability and the interrupt routine addressing capability. The later allows direct or indirect jumping to the specific interrupt routine requested without any polling of the interrupting devices. The normal sequence of events during an interrupt depends on the type of CPU being used. The events occur as follows in an 8086 system: 1. One or more of the INTERRUPT REQUEST lines (IR7-0) are raised high, setting the corresponding IRR bit(s). 2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate  3. The CPU acknowledges the INT and responds with an INTA pulse. 4. Upon receiving an  from the CPU group, the highest priority ISR bit is set INTA and the corresponding IRR bit is reset. The 8259A does not drive the data bus during this cycle.
117

 5. The 8086 will initiate a second INTA pulse. During this pulse, the 8259A releases an 8-bit pointer onto the data bus where it is read by the CPU. 6. This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the end of the second  pulse. Otherwise, the ISR bit remains set until an INTA appropriate EOI command is issued at the end of the interrupt subroutine. When the 8259A PIC receives an interrupt, INT becomes active and an interrupt acknowledge cycle is started. If a higher priority interrupt occurs between the two INTA pulses, the INT line goes inactive immediately after the second INTA pulse. After an unspecified amount of time the INT line is activated again to signify the higher priority interrupt waiting for service. In 8086 mode only two interrupt acknowledge cycles are issued by the processor and no CALL op-code is sent to the processor. The first interrupt acknowledge cycle is similar to that of MCS-80, 85 systems in that the 8259A uses it to internally freeze the state of the interrupt for priority resolution and as a master it issues the interrupt code on the cascade lines at the end of  pulses. On this first cycle it does not issue any data to the INTA processor and leaves its data bus buffers disabled. On the second interrupt acknowledge cycle in 8086 mode the master (or slave if so programmed) will send a byte of data to the processor with the acknowledged interrupt code.

Figure 7.18 Interfacing 8259A (PIC) to 8086 microprocessor

118

7.3.2 PROGRAMMI G THE 8259A

The 8259A accepts two types of command words generated by the CPU: 1. Initialization command words (ICWs): Before normal operation can begin, each 8259A in the system must be brought to a starting point- by a sequence of 2 to 4 bytes timed by  pulses. WR 2. Operation command words (OCWs): these are the command words which command the 8259A to operate in various interrupt modes. These modes are: a. Fully nested mode b. Rotating priority mode c. Special mask mode d. Polled mode The OCWs can be written into the 8259A any time after initialization.

7.3.3 I ITIALIZATIO COMMA D WORDS (ICWS)

General ICW1 and ICW2 must be sent to any 8259A in the system. If the system has any slave 8259A (cascade mode), then an ICW3 must be sent to the master and different ICW3 must be sent to the slave. If the system is an 8086, or if you want to specify certain special conditions, then you have to send an ICW4 to the master and to each slave. ICW1: this byte is required in all modes. Whenever a command is issued with Ao = 0 and D4= 1, this is interrupted as initialization command word 1 (ICW1). Bits D7-D5 and D2 are required only when used with the 8085 microprocessor. That means, they are a do not care bits to 8086 microprocessor. Bit D3 specifies the IR trigger, either level or rising edge. Bit D1 is used to specify that the PIC is to be used in the cascade mode (requiring a subsequent ICW3). Bit D0 must be a 1 for an 8086 microprocessor. Example 7.5 the following instructions program the PIC for the 8086mode, rising edge trigger, and a single PIC. If the PICs port address is 7CH. MOV AL, 00010011B OUT 7CH, AL ICW1 starts the initialization sequence during which the following automatically occur. a. The edge sense circuit is reset, which means that following initialization, an interrupt request (IR) input must make a low to high transition to generate an interrupt. b. the interrupt mask register is cleared c. IR7 input is assigned priority 7 d. the slave mode address is set to 7 e. special mask mode is cleared and status read is set to IRR
119

f. If IC=4, then all functions selected in ICW4 are set to zero. ICW2: it is written to the next port address 7CE (A0=0), specifies the five high order bits of the interrupt type number to be output by the PIC during the INTA bus cycle. The PIC assigns the three low order bits 000-111 to correspond to the active IR input, IR0-IR7. Thus the base type number of the PIC must end with 000B. Example 7.6 Determine the value for ICW2 if the PIC is to be programmed for base address of C8H. What type numbers will be output by the PIC for each IR input, and from which memory locations will the CPU fetch the interrupt vectors? Solution ICW2 is equal to the base address and thus should be programmed for 11001000B. Table below summarizes the type numbers output for each IR input and the corresponding interrupt vector locations in memory. Table 7.5 PIC interrupt vectors Type number output Input IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 By PIC C8H C9H CAH CBH CCH CDH CEH CFH Interrupt vector location 0000:0320-0323H 0000:0324-0327H 0000:0328-032BH 0000:032C-032FH 0000:0330-0333H 0000:0334-0337H 0000:0338-033BH 0000:033C-033FH

ICW3: this byte is also output to port 7EH (A0=1) but is required only if the PIC is to be used in a cascaded system. For a master it specifies the IR input to which a slave is connected. Thus, setting ICW3 to 00000011 indicates that slave PICs are connected to the masters IR1 and IR0 inputs. For a slave PIC, ICW3 indicates the cascade address (master IR input) to which that slave is connected. For example, if the slave is connected to IR6 of the master, ICW3=00000
120

110. During the INTA bus cycle the master will output this address on CAS0-CAS2. If the address matches, the slave will output the type number corresponding to its highestpriority active IR input. ICW4: this byte is also output to port 7EH (A0=1) is required to specify the 8086 mode (bit D0=1). Bit D1 activates the automatic EOI instruction used in the fully nested and automatic rotating priority modes. Bits D2 and D3 specify if the PIC is the master or slave in a buffered CPU environment, and thus control the /EN output. Bit D4 selects SP  the fully nested operating mode.

7.3.4 OPERATIO COMMA D WORDS (OCWS)

After the initialization command words (ICWS) are programmed into the 8259A, the chip is ready to accept interrupt requests at the input lines. However, during the 8259A operation, a selection of algorithms can command the 8259A to operate in various modes through the operation command words (OCWS).

7.3.5 CASCADE MODE

The 8259A can be easily interconnected in a system of one master with up to eight slaves to handle up to 64 priority levels. The master controls the slaves through the 3 line cascade bus. The cascade bus acts like chip selects to the slaves during the  sequences. INTA In a cascade configuration, the slave interrupt outputs are connected to the master interrupt request inputs. When a slave request line is activated and afterwards

Figure 7.19 cascading the 8259.

121

acknowledged, the master will enable the corresponding slave to release the device routine address during bytes 2 of  only for 8086/8088. INTA The cascade bus lines are normally low and will contain the slave address code from the trailing edge of the first  pulse to the trailing edge of the third pulse. Each 8259A in INTA the system must follow a separate initialization sequence and can be programmed to work in a different mode. An EOI command must be issued twice: once for the master and once for the corresponding slave. An address decoder is required to activate the chip select (CS) input of each 8259A. The cascade lines of the master 8259A are activated only for slave input, non-slave inputs leave the cascade line inactive (low).

7.4 PROGRAMMABLE I TERVAL TIMER (8254)

The Intel 8254 is a counter/timer device designed to solve the common timing control problems in microcomputer system design. It provides three independent 16-bit counters, each capable of handling clock inputs up to 10 MHz. All modes are software programmable. The 8254 is a superset of the 8253. The 8254 uses HMOS technology and comes in a 24-pin plastic or CERDIP package with a single +5V supply.

Figure7.20 block diagram and pin-configuration of 8454

122

Table 7.6 pin description of 8454

7.4.1 FU CTIO AL DESCRIPTIO

General The 8254 is a programmable interval timer/counter designed for use with Intel microcomputer systems. It is a general purpose- multi-timing element that can be treated as an array of I/O ports in the system software. The 8254 solves one of the most common problems in any microcomputer system, the generation of accurate time delays under software control, Instead of setting up timing loops in software. The programmer configures the 8254 to match his requirements and programs one of the counters for the desired delay. After the desired delay, the 8254 will interrupt the CPU. Software overhead is minimal and variable length delays can easily be accommodated. Some of the other counter/timer functions common to microcomputers which can be implemented with the 8254 are: Real time clock Event-counter
123

Digital one-shot Programmable rate generator Square wave generator Binary rate multiplier Complex waveform generator Complex motor controller

7.4.2 BLOCK DIAGRAM

DATA BUS BUFFER This 3-state, bi-directional, 8-bit buffer is used to interface the 8254 to the system bus. READ/WRITE LOGIC The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the 8254. A1and A0 select one of the three counters or the Control Word Register to be read from/written into. A low on the  input tells RD  input tells the the 8254 that the CPU is reading one of the counters. A low on the WR 8254 that the CPU is writing either a Control Word or an initial count. Both  and RD are qualified by ,  and  are ignored unless the 8254 has been selected by WR CS RD WR  low. holding CS CO TROL WORD REGISTER The Control Word Register (see Figure 7.21) is selected by the Read/Write Logic when A1, A0 = 11. If the CPU then does a write operation to the 8254, the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters. The Control Word Register can only be written to; status information is available with the Read-Back Command.

124

Figure 7.21 control word register and counter functions; internal block diagram of a counter COU TER 0, COU TER 1, COU TER 2 These three functional blocks are identical in operation, so only a single Counter will be described. The internal block diagram of a single counter is shown in Figure 7.21 The Counters are fully independent. Each Counter may operate in a different Mode.

125

The Control Word Register is shown in the figure 7.21; it is not part of the Counter itself, but its contents determine how the Counter operates. The status register when latched, contains the current contents of the Control Word Register and status of the output and null count flag. The actual counter is labeled CE (for Counting Element). It is a 16-bit presettable synchronous down counter. OLM and OLL are two 8-bit latches. OL stands for Output Latch, the subscripts M and L stand for Most significant byte and Least significant byte respectively. Both are normally referred to as one unit and called just OL. These latches normally follow the CE, but if a suitable Counter Latch Command is sent to the 8254, the latches latch the present count until read by the CPU and then return to following the CE. One latch at a time is enabled by the counters Control Logic to drive the internal bus. This is how the 16-bit Counter communicates over the 8-bit internal bus. Note that the CE itself cannot be read, whenever you read the count, it is the OL that is being read. Similarly, there are two 8-bit registers called CRM and CRL (for Count Register). Both are normally referred to as one unit and called just CR. When a new count is written to the Counter, the count is stored in the CR and later transferred to the CE. The Control Logic allows one register at a time to be loaded from the internal bus. Both bytes are transferred to the CE simultaneously. CRM and CRL are cleared when the Counter is programmed. In this way, if the Counter has been programmed for one byte counts (either most significant byte only or least significant byte only) the other byte will be zero. Note that the CE cannot be written into, whenever a count is written; it is written into the CR. The Control Logic is also shown in the diagram, CLK n, GATE n, and OUT n are all connected to the outside world through the Control Logic.

7.4.3 8254 SYSTEM I TERFACE

The 8254 is a component of the Intel Microcomputer Systems and interfaces in the same manner as all other peripherals of the family. It is treated by the systems software as an array of peripheral I/O ports, three are counters and the fourth is a control register for MODE programming. Basically; the select inputs A0, A1connect to the A0, A1 address bus signals of the CPU.  The CS can be derived directly from the address bus using a linear select method. Or it can be connected to the output of a decoder, such as an Intel 8205 for larger systems.

7.4.4 OPERATIO AL DESCRIPTIO

General After power-up, the state of the 8254 is undefined. The Mode, count value, and output of all Counters are undefined.

126

How each Counter operates is determined when it is programmed. Each Counter must be programmed before it can be used. Unused counters need not be programmed.

Figure 7.22 system interface

Figure 7.23 control word format

127

Programming the 8254 Counters are programmed by writing a Control Word and then an initial count. The Control Words are written into the Control Word Register, which is selected when A1, A0 = 11. The Control Word itself specifies which Counter is being programmed. By contrast; initial counts are written into the Counters, not the Control Word Register. The A1, A0 inputs are used to select the Counter to be written into. The format of the initial count is determined by the Control Word used. Write Operations The programming procedure for the 8254 is very flexible. Only two conventions need to be remembered. 1) For each Counter, the Control Word must be written before the initial count is written. 2) The initial count must follow the count format specified in the Control Word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). Since the Control Word Register and the three Counters have separate addresses (selected by the A1, A0 inputs), and each Control Word specifies the Counter it applies to (SC0, SC1 bits). No special instruction sequence is required. Any programming sequence that follows the conventions in Figure 7.23 is acceptable. A new initial count may be written to a Counter at any time without affecting the Counters programmed Mode in any way. Counting will be affected as described in the Mode definitions. The new count must follow the programmed count format. If a Counter is programmed to read/write two-byte counts, the following precaution applies. A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter. Otherwise; the Counter will be loaded with an incorrect count.

128

Figure 7.24 few possible programming sequence Read Operations It is often desirable to read the value of a Counter without disturbing the count in progress. This is easily done in the 8254. There are three possible methods for reading the counters, a simple read operation, the Counter Latch Command, and the Read-Back Command. Each is explained below. The first method is to perform a simple read operation. To read the Counter, which is selected with the A1, A0 inputs, the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic. Other-wise, the count may be in the process of changing when it is read, giving an undefined result. COU TER LATCH COMMA D The second method uses the Counter Latch Command. Like a Control Word, this command is written to the Control Word Register, which is selected when A1, A0 =11. Also like a Control Word, the SC0, SC1 bits select one of the three Counters, but two other bits, D5 and D4, distinguish this command from a Control Word.

129

Figure 7.25 counter latching command format The selected Counters output latch (OL) latches the count at the time the Counter Latch Command is received. This count is held in the latch until it is read by the CPU (or until the Counter is reprogrammed). The count is then unlatched automatically and the OL returns to following the counting element (CE). This allows reading the contents of the Counters on the fly without affecting counting in progress. Multiple Counter Latch Commands may be used to latch more than one Counter. Each latched Counters OL holds its count until it is read. Counter Latch Commands do not affect the programmed Mode of the Counter in any way. If a Counter is latched and then, some time later, latched again before the count is read, the second counter Latch Command is ignored. The count read will be the count at the time the first Counter Latch Command was issued. With either method, the count must be read according to the programmed format, specifically, if the Counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other read or write or programming operations of other Counters may be inserted between them. Another feature of the 8254 is that reads and writes of the same Counter may be interleaved. For example, if the Counter is programmed for two byte counts, the following sequence is valid. 1) Read least significant byte. 2) Write new least significant byte.
130

3) Read most significant byte. 4) Write new most significant byte. If a Counter is programmed to read/write two-byte counts, the following precaution applies. A program must not transfer control between reading the first and second byte to another routine which also reads from that same Counter. Otherwise, an incorrect count will be read. READ-BACK COMMA D The third method uses the Read-Back Command. This command allows the user to check the count value, programmed Mode, and current states of the OUT pin and Null Count flag of the selected counter(s). The command is written into the Control Word Register and has the format shown in Figure 7.26. The command applies to the counters selected by setting their corresponding bits D3, D2, D1 = 1.

Figure 7.26 Read-Back Command format. The read-back command may be used to latch multiple counter output latches (OL) by setting the COUNT bit D5 = 0 and selecting the desired counter(s). This single command is functionally equivalent to several counter latch commands, one for each counter latched. Each counters latched count is held until it is read (or the counter is reprogrammed). The counter is automatically unlatched when read, but other counters remain latched until they are read. If multiple count read-back commands are issued to the same counter without reading the count, all but the first are ignored. I.e.; the count which will be read is the count at the time the first read-back command was issued. The read-back command may also be used to latch status information of selected counter(s) by setting STATUS bit D4 = 0. Status must be latched to be read; status of a counter is accessed by a read from that counter.

131

The counter status format is shown in Figure 7.27, Bits D5 through D0 contain the counters programmed Mode exactly as written in the last Mode Control Word, OUTPUT bit D7 contains the current state of the OUT pin. This allows the user to monitor the counters output via software, possibly eliminating some hardware from a system.

Figure 7.27 status byte ULL COU T bit D6 indicates when the last count written to the counter register (CR) has been loaded into the counting element (CE). The exact time this happens depends on the Mode of the counter and is described in the Mode Definitions, but until the count is loaded into the counting element (CE), it cant be read from the counter. If the count is latched or read before this time, the count value will not reflect the new count just written. The operation of Null Count is shown in Figure 7.28.

Figure 7.28 null count operation If multiple status latch operations of the counter(s) are performed without reading the status, all but the first are ignored. I.e.; the status that will be read is the status of the counter at the time the first status read-back command was issued.

132

Both count and status of the selected counter(s) may be latched simultaneously by setting   both COUNT and STATUS bits D5, D4 = 0. This is functionally the same as issuing two separate read-back commands at once, and the above discussions apply here also. Specifically, if multiple count and/or status read-back commands are issued to the same counter(s) without any intervening reads, all but the first are ignored. This is illustrated in Figure 7.29. If both count and status of a counter are latched, the first read operation of that counter will return latched status, regardless of which was latched first. The next one or two reads (depending on whether the counter is programmed for one or two type counts) return latched count. Subsequent reads return un- latched count.

Figure 7.29 read/write operations summery

Figure 7.30 Read-back command example.

133

7.4.5 MODE DEFI ITIO S

The following are defined for use in describing the operation of the 8254: CLK Pulse: a rising edge, then a falling edge, in that order, of a Counters CLK in put. Trigger: a rising edge of a Counters GATE input. Counter loading: the transfer of a count from the CR to the CE (refer to the Functional Description). MODE 0: I TERRUPT O TERMI AL COU T Mode 0 is typically used for event counting, After the Control Word is written. OUT is initially low, and will remain low until the Counter reaches zero. OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Counter. GATE = 1 enables counting, GATE = 0 disables counting. GATE has no effect on OUT. After the Control Word and initial count are written to a Counter, the initial count will be loaded on the next CLK pulse. This CLK pulse does not decrement the count, so for an initial count of N. OUT does not go high until N+1 CLK pulses after the initial count is written. If a new count is written to the Counter, it will be loaded on the next CLK pulse and counting will continue from the new count. If a two-byte count is written, the following happens: 1. Writing the first byte disables counting. OUT is set low immediately (no clock pulse required) 2. Writing the second byte allows the new count to be loaded on the next CLK pulse. This allows the counting sequence to be synchronized by software. Again, OUT does not go high until N+1 CLK pulses after the new count of N is written. If an initial count is written while GATE = 0, it will still be loaded on the next CLK pulse. When GATE goes high, OUT will go high N CLK pulses later, no CLK pulse is needed to load the Counter as this has already been done. MODE 1: HARDWARE RETRIGGERABLE O E-SHOT OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin the one-shot pulse, and will remain low until the Counter reaches zero. OUT will then go high and remain high until the CLK pulse after the next trigger. After writing the Control Word and initial count, the Counter is armed. A trigger results in loading the Counter and setting OUT low on the next CLK pulse; thus starting the oneshot pulse. An initial count of N will result in a one-shot pulse N CLK cycles in duration. The one-shot is retriggerable, hence OUT will remain low for N CLK pulses after any
134

trigger. The one-shot pulse can be repeated without rewriting the same count into the counter. GATE has no effect on OUT. If a new count is written to the Counter during a one- shot pulse, the current one-shot is not affected unless the counter is retriggered. In that case, the Counter is loaded with the new count and the one- shot pulse continues until the new count expires. MODE 2: RATE GE ERATOR This Mode functions like a divide-by-N counter. It is typically used to generate a Real Time Clock interrupt, OUT will initially be high. When the initial count has decremented to 1, OUT goes low for one CLK pulse. OUT then goes high again, the Counter re- loads the initial count and the process is repeated. Mode 2 is periodic; the same sequence is repeated indefinitely. For an initial count of N. the sequence repeats every N CLK cycles. GATE = 1 enables counting. GATE = 0 disables counting. If GATE goes low during an output pulse, OUT is set high immediately. A trigger reloads the Counter with the initial count on the next CLK pulse. OUT goes low N CLK pulses after the trigger. Thus the GATE input can be used to synchronize the Counter. After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse. OUT goes low N CLK Pulses after the initial count is written. This allows the Counter to be synchronized by software also. Writing a new count while counting does not affect the current counting sequence. If a trigger is received after writing a new count but before the end of the current period, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count. Otherwise; the new count will be loaded at the end of the current counting cycle. In mode 2, a COUNT of 1 is illegal. MODE 3: SQUARE WAVE MODE Mode 3 is typically used for Baud rate generation. Mode 3 is similar to Mode 2 except for the duty cycle of OUT. OUT will initially be high. When half the initial count has expired, OUT goes low for the remainder of the count. Mode 3 is periodic; the sequence above is repeated indefinitely. An initial count of N results in a square wave with a period of N CLK cycles. GATE = 1 enables counting. GATE = 0 disables counting. If GATE goes low while OUT is low, OUT is set high immediately, no CLK pulse is required. A trigger reloads the Counter with the initial count on the next CLK pulse. Thus the GATE input can be used to synchronize the Counter.

135

After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse. This allows the Counter to be synchronized by software also. Writing a new count while counting does not affect the current counting sequence. If a trigger is received after writing a new count but before the end of the current half-cycle of the square wave, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count. Otherwise; the new count will be loaded at the end of the current half-cycle. Mode 3 is implemented as follows: Even counts: OUT is initially high. The initial count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses. When the count expires OUT changes value and the Counter is re- loaded with the initial count. The above process is repeated indefinitely. Odd counts: OUT is initially high. The initial count minus one (an even number) is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses. One CLK pulse after the count expires. OUT goes low and the Counter is reloaded with the initial count minus one. Succeeding CLK pulses decrement the count by two. When the count expires, OUT goes high again and the Counter is reloaded with the initial count minus one. The above process is repeated indefinitely. So for odd counts, OUT will be high for (N+1)/2 counts and low for (N-1)/2 counts. MODE 4: SOFTWARE TRIGGERED STROBE OUT will be initially high. When the initial count expires, OUT will go low for one CLK pulse and then go high again. The counting sequence is triggered by writing the initial count. GATE = 1 enables counting, GATE = 0 disables Counting. GATE has no effect on OUT. After writing a Control Word and initial count, the Counter will be loaded on the next CLK pulse. This CLK pulse does not decrement the count, so for an initial count of N, OUT does not strobe low until N+1 CLK pulses after the initial count is written. If a new count is written during counting, it will be loaded on the next CLK pulse and counting will continue from the new count. If a two-byte count is written, the following happens: 1. Writing the first byte has no effect on counting. 2. Writing the second byte allows the new count to be loaded on the next CLK pulse. This allows the sequence to be retriggered by software, OUT strobes low N+1 CLK pulses after the new count of N is written.

136

MODE 5: HARDWARE TRIGGERED STROBE (RETRIGGERABLE) OUT will initially be high. Counting is triggered by a rising edge of GATE. When the initial count has expired, OUT will go low for one CLK pulse and then go high again. After writing the Control Word and initial count, the counter will not be loaded until the CLK pulse after a trigger. This CLK pulse does not decrement the count, so for an initial count of N. OUT does not strobe low until N+1 CLK pulses after a trigger. A trigger results in the Counter being loaded with the initial count on the next CLK pulse. The counting sequence is re-triggerable. OUT will not strobe low for N+1 CLK pulses after any trigger. GATE has no effect on OUT. If a new count is written during counting, the current counting sequence will not be affected. If a trigger occurs after the new count is written but before the current count expires, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there.

Figure 7.31 Gate pin operations summery.

137

Figure 7.32 minimum and maximum initial counts.

7.4.6 OPERATIO COMMO TO ALL MODES

PROGRAMMI G When a Control Word is written to a Counter, all Control Logic is immediately reset and OUT goes to a known initial state, no CLK pulses are required for this. GATE The GATE input is always sampled on the rising edge of CLK. In Modes 0, 2, 3, and 4 the GATE input is level sensitive, and the logic level is sampled on the rising edge of CLK. In Modes 1, 2, 3, and 5 the GATE input is rising-edge sensitive. In these Modes, a rising edge of GATE (trigger) sets an edge-sensitive flip-flop in the Counter. This flipflop is then sampled on the next rising edge of CLK; the flip-flop is reset immediately after it is sampled. In this way, a trigger will be detected no matter when it occurs, a high logic level does not have to be maintained until the next rising edge of CLK. Note that in Modes 2 and 3, the GATE input is both edge- and level-sensitive. In Modes 2 and 3, if a CLK source other than the system clock is used. GATE should be pulsed immediately following  of a new count value. WR COU TER New counts are loaded and Counters are decremented on the falling edge of CLK. The largest possible initial count is 0; this is equivalent to 216for binary counting and 104for BCD counting. The Counter does not stop when it reaches zero. In Modes 0, 1, 4, and 5 the Counter wraps around to the highest count, either FFFF hex for binary counting or 9999 for BCD counting, and continues counting. Modes 2 and 3 are periodic; the Counter reloads itself with the initial count and continues counting from there.

138

Bibliography
1. JOHN UFFENBECK, the 8086/8088 FAMILY: DESIGN, PROGRAMMING, AND INTERFACING, Prentice-Hall of India private limited, New Delhi-110 001, 1997. 2. Yu-cheng Liu Glenn A. Gibson, microcomputer systems: the 8086/88 Family Architecture, programming and design Prentice-Hall of India private limited, 2nd-edition, New Delhi-110 001, 2001. 3. Douglas V Hall, Microprocessors and Interfacing: Programming and Hardware, McGraw Hill Inc. New Delhi, 2nd edition, 1992 4. Barry B.Brey, The Intel Microprocessors 8086/8088, 80186, 80286, 80386 and 80486 Architecture, programming and interfacing, Prentice Hall of India, 2001 5. Naod Duga, dept. of Electrical and Computer Engineering Addis Ababa University. 6. Richard C.Detmer, introduction to 80x86 Assembly Language and Computer Architecture, 2001 WWW Resources and software tools: 1. Emu8086, the 8086 Emulator [http://www.emu8086.com], January 2011 2. Intel IA32 Architecture Reference [http://www.developer.intel.com], January 2011 3. http://www.scribd.com/, January 2011 4. http://www.scribd.com/doc/22765799/Intel-8259a-Pic, January 2011 5. http://www.scribd.com/8254-Programmable-Interval-Timer/d/21807707, January 2011

139