Magpali, Jennifer S. Rosas, Maricon A.

WRITTEN REPORT PIPELINING

CMSC 132

Pipelining Is an organizational implementation technique that has been responsible for the most dramatic increases in computer performance. It is an implementation technique whereby multiple instructions are overlapped in execution. It takes advantage of parallelism that exists among the actions needed to execute an instruction. Today, pipelining is the key implementation technique used to make fast CPUs. A Pipeline is a series of stages, where some work is done at each stage. The work is not finished until it has passed through all stages. With pipelining, the computer architecture allows the next instructions to be fetched while the processor is performing arithmetic operations, holding them in a buffer close to the processor until each instruction operation can be performed. Pipeline characteristics 1. Hardware or Software implementation. Pipelining could be implemented in both hardware and software. 2. Large or Small scale. Stations in a pipeline can range from simplistic to powerful, and a pipeline can range in length from short to long. 3. Synchronous or Asynchronous flow. A synchronous pipeline operates like an assembly line: at a given time, each station is processing some amount of information. An asynchronous pipeline allows a station to forward information at any time. 4. Buffered or Unbuffered flow. One stage of pipeline sends data directly to another one or a buffer is place between each pairs of stages. 5. Finite Chunks or Continuous bit streams. The digital information that passes through a pipeline can consist of a sequence or small data items or an arbitrarily long bit stream. 6. Automatic data feed or Manual data feed. Some implementations of pipelines use a separate mechanism to move information, and other implementations require each stage to participate in moving information.

How does Pipelining work? Basic idea: Overlap the execution of a series of instructions. That is, start executing the next instruction in a program before execution of the current one is completed. The pipeline is divided into segments and each segment can execute it operation concurrently with the other segments. Once a segment completes an operation, it passes the result to the next segment in the pipeline and fetches the next operations from the preceding segment.

Linear execution:
Instruction 1 Instruction 2

X
Instruction 4

X
Instruction 3

X X Four sample instructions, executed linearly

Pipelining implementation:
5
IF ID IF EX ID M EX W M

1
W

1
W

IF

ID IF

EX

1
W

ID

EX

Four Pipelined Instructions

1. The instruction Fetch (IF) stage is responsible for obtaining the requested instruction from memory. The instruction and the program counter (which is incremented to the next instruction) are stored in the IF/ID pipeline register as temporary storage so that may be used in the next stage at the start of the next clock cycle. The value in the PC represents an address in memory. The MIPS64 instructions are all 32-bits in length. First we load the 4 bytes in memory into the CPU. Second we increment the PC by 4 because memory addresses are arranged in byte ordering. This will now represent the next instruction. 2. The Instruction Decode (ID) stage is responsible for decoding the instruction and sending out the various control lines to the other parts of the processor. The instruction is sent to the control unit where it is decoded and the registers are fetched from the register file. Decode the instruction and read the registers corresponding to register source specifiers from the register file. Do the equality test on the registers as they are read, for a possible branch. Sign-extend the offset field of the instruction in case it is needed. Compute the possible branch target address by adding the sign-extended offset to the incremented PC. Decoding is done in parallel with reading registers, which is possible because the register specifiers are at a fixed location in a RISC architecture. 3. The Execution (EX) stage is where any calculations are performed. The main component in this stage is the ALU. The ALU is made up of arithmetic, logic and capabilities. The ALU operates on the operands prepared in the prior cycle, performing one of three functions depending on the instruction type.

Memory reference: The ALU adds the base register and the offset to form the effective address. Register-Register ALU instruction: The ALU performs the operation specified by the ALU opcode on the values read from the register file. Register-Immediate ALU instruction: The ALU performs the operation specified by the ALU opcode on the first value read from the register file and the sign-extended immediate.

4. The Memory and IO (MEM) stage is responsible for storing and loading values to and from memory. It is also responsible for input or output from the processor. If the current instruction is not of Memory or IO type than the result from the ALU is passed through to the write back stage. If the instruction is a load, memory does a read using the effective address computed in the previous cycle. If it is a store, then the memory writes the data from the second register read from the register file using the effective address. 5. The Write Back (WB) stage is responsible for writing the result of a calculation, memory access or input into the register file. Register-Register ALU instruction or Load instruction: Write the result into the register file, whether it comes from the memory system (for a load) or from the ALU (for an ALU instruction). Estimated timings of each stage are the following: 1. 2. 3. 4. 5. Instruction Fetch stage 2 nanoseconds Instruction Decode stage 1 nanosecond Execution stage 2 nanoseconds Memory and IO stage 2 nanoseconds Write Back stage 1 nanosecond

Advantages of pipelining implementation More efficient use of processor. Quicker time of execution of large number of instructions.

Disadvantages of pipelining implementation Pipelining involves adding hardware to the chip. Inability to continuously run the pipeline at full speed because of pipeline hazards which disrupt the smooth execution of the pipeline.

References: Computer Architecture: A Quantitative Approach, John Hennessy and David Patterson http://www.cs.sjsu.edu/~lee/cs147/fall2003/23147L25Pipelining.ppt http://murray.newcastle.edu.au/users/students/1999/c9311421/pipe.html#s5 http://www-leland.stanford.edu/class/ee282h/