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Microelectronics Journal 41 (2010) 430439

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Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Designing a compact soft-start scheme for voltage-mode DCDC switching converters

Sizhen Li n, Xuecheng Zou, Xiaofei Chen, Quan Gan
Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, China

a r t i c l e in f o
Article history: Received 15 August 2009 Received in revised form 23 April 2010 Accepted 3 May 2010 Keywords: DCDC switching converter Soft-start scheme Inrush current Digital-controlled current limitation DAC

a b s t r a c t
In this paper, a compact soft-start scheme is proposed and successfully applied to typical voltage-mode DCDC switching converters. The adaptive current limitation implemented through DAC control will largely reduce the overshoot voltage under a wide range of output current. Proven experimentally by a buck converter implemented in a 0.5 mm CMOS technology, the post-simulation results show that when the converter starts up, the maximum overshoot (2.7% at ILOAD 0 A) by the proposed soft-start scheme is less than that with the conventional scheme by 5% under the same condition. The start-up time can be adaptively adjustable depending on load current and the maximum start-up time is around 760 ms with 22 mF output capacitor. The circuits which realize the soft-start scheme can also be fully integrated into the control chip of DCDC switching converter resulting in low cost. & 2010 Elsevier Ltd. All rights reserved.

1. Introduction DCDC switching converters are widely used in portable electronic device for high efciency and low power consumption [1]. In the DCDC switching converter, during start-up, the large inrush current and the overshoot of the output voltage will damage the inductor and induce stability problem. As a result, soft-start scheme is normally adopted to eliminate the inrush current and reduce the overshoot voltage [24]. There are two types of soft-start implementation, one is through voltage-mode method; the other is by current-mode method. At present, voltage-mode method has been widely used in industrial catalog products for its simplicity [5,6]. However, most voltage-mode soft-start circuits need an external capacitor to regulate the soft-start time and the inrush current cannot be limited directly. It leads to cost increase and potential damagerisk in external components. The current trend of integrating numerous LDOs and switched-mode regulators and controllers on the same system-on-chip PMIC, each with its own start-up and power-up sequencing requirements, necessitates the design of a compact fully integrated soft-start circuit with higher safety requirements for low cost considerations [7]. As a result, the current-mode soft-start method will be more competent because it can directly limit the inrush current and can be fully integrated in the controller chip [8,9]. However, both approaches in [8,9] are

Corresponding author. Tel.: + 86 13545119211. E-mail address: lisizhen@gmail.com (S.Z. Li).

applied in current-mode switching converter and may not be appropriate for the voltage-mode switching converter as there is only one voltage feedback loop in the voltage-mode DCDC converter. Fig. 1 describes the conventional current-mode soft-start scheme applied to a voltage-mode buck converter [10]. When starts up, the divided voltage of the output is much lower than the voltage reference Vref, the error amplier is under unbalanced state. The output voltage of the error amplier is at high voltage level. If there is not any limitation, the converter works under the 100% duty ratio; thus, large inrush current will ow into the output capacitor to generate output voltage overshoot. Current-mode soft-start method senses the current passing through the inductor L1 and limits the inductor peak current (ILpeak) through the current comparator to reduce the inrush current. It will generate potential overshoot of the output voltage under different loads because the current reference is usually set invariably higher than the typical output current. The output voltage Vo and inductor current IL of the converter under the softstart scheme are shown in Fig. 2. It can be obtained that the larger overshoot will be generated at the lighter load and the maximum overshoot occurs at the noload condition. Moreover, the approach of employing the currentmode soft-start scheme suffers from a dissatisfactory operating efciency because of the power dissipated in the current sensor. Besides, the stability problem may also occur if the current limitation cannot be controlled fast. So far, there are very few papers published relating to the overshoot reduction technology of current-mode soft-start scheme for voltage-mode switching

0026-2692/$ - see front matter & 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2010.05.001

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Fig. 1. Conventional current-mode soft-start scheme applied to a voltage-mode buck converter.

the proposed scheme is not limited to buck converter but can be extended to voltage-mode DCDC converter in general. In Section 2, the principle of the scheme and the design of the circuits are presented in detail. The experimental results are discussed in Section 3. Finally, the conclusion is given in Section 4.

2. Proposed soft-start scheme 2.1. Structure and operational principle Based on the principle of the conventional current-mode softstart scheme, an improved soft-start scheme using DAC technique is proposed and applied to a voltage-mode buck converter as described in Fig. 3. The signal NPWM is generated from PWM comparator as shown in Fig. 1. The current reference (IREF) is converted to voltage V1. Different from constant ILpeak control given in Fig. 1, the principle of the proposed soft-start scheme is to have the current reference IREF rise step by step as shown in Fig. 4, and thus the inductor peak current (ILpeak) can be limited by stages. The purpose is to reduce the overshoot voltage under different loads to a great extent. During start-up, the output signal Nsoft of the current comparator and the oscillator output signal CLK are used to lift the output voltage. The upper edge of the signal CLK turns the power transistor M1 on and the upper edge of the signal Nsoft turns M1 off. During normal state, the output signal NPWM of the PWM comparator and the signal CLK are used to realize feedback control to regulate the output voltage. Fig. 4 describes the soft-start key waveforms under full load and no load. EN is the enable signal of the counter. When EN is set to logic high, the soft-start function starts working. The switching frequency of power transistors is fs (fs 1/Ts), which is the same as that of oscillator. The nc-bit counter calculates the switching cycles of power transistors. The high bits of the counter (Qnc 2 Qnc 1 ) are used to generate the output codes D0D1D2, which are the inputs of the DAC. As shown in Fig. 4a, it can be obtained that T1 2nc 2 1Ts , T2 T3 2nc 2 Ts , 1 2

Fig. 2. Waveforms of conventional soft-start scheme using constant inductor peak current (ILpeak) control under: (a) full load; (b) no load.

converter, especially current-mode soft-start scheme with reduced current-sense power consumption and improved stability. In this paper, an improved current-mode soft-start scheme that offers overshoot reduction is proposed. Thanks to the digitalcontrolled current-limitation, the overshoot is largely reduced under a wide range of load currents. An innovative digitalcontrolled current sensor, which features with simplicity is proposed to reduce the power dissipation. Besides, fast comparator with clamping function and the driver with dedicated control contribute to the high stability. The proposed scheme is realized using transistor level. The soft-start circuit is fully integrated and applied to a voltage-mode buck converter in our design. It should also be noted that

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Fig. 3. Simplied schematic of the synchronous voltage-mode buck converter with the proposed soft-start scheme.

and the maximum counting period is TCOUNT T1 T2 T3 3 2nc 2 1Ts : 3

result in voltage overshoot. The overshoot can be estimated by

DV

Q L Q R C

When codes D0D1D2 are 000, 001, 011, 111 in turn, the current passing through the resistor R1 (IREF) rises in steps of 4Ia, 8Ia, 12Ia, 16Ia.Thus, the output V1 is described as V1 Vin IREF R1 : 4

The power transistor M1 works in the deep linear region, the resistance is dened as RON. In our design, the inductor current is sampled through sensing the voltage Vsw, which will be discussed later. Suppose that during sampling, the current passing through the inductor is IL, the output V2 is given by V2 Vin IL RON : Set V1 V2; from Eqs. (4) and (5), it can be derived that ILpeak ILpeak1 IREF R1 RON 5

4Ia R1 , 0 o t ot1 , RON 8Ia R1 ILpeak2 , t1 o t o t2 , RON 12Ia R1 ILpeak3 , t2 o t ot3 , RON 16Ia R1 ILpeak4 , t 4t3 RON

where C is the value of the output capacitor, Q L the charge stored in the inductor, QR the charge transferred to the load. In Eq. (7), Q L is proportional to the predetermined value of ILpeak. In conventional current-mode soft-start scheme, ILpeak is set constant and higher than the full current. Thus, the overshoot will approximately linearly increase as the load current decreases. In our proposed scheme, the ILpeak is set constant at different values under different load current ranges. Therefore, the difference between QL and QR is reduced and the overshoot has been largely reduced. Theoretically, the more the current step is, the less the overshoot will be obtained. However, solution with too many steps will make the circuit implementation complicated and increase the manufacture cost. Thus, the ILpeak is designed in steps of typically ILpeak4/4, ILpeak4/2, 3/4ILpeak4 and then the typical current limit ILpeak4 is 1.6 A in our experiment under which the full-load current is 1.3 A. At 1.25 MHz switching frequency, a 10-bit counter is adopted to ensure the a smooth soft-start [11]. For different applications, the value of ILpeak can be tuned into other value. 2.2. Current sensor Among many current sensing techniques, we propose the digital-controlled current sensor which features with simplicity [12,13]. The circuit is given in Fig. 5. The current-sense function is realized through sensing the voltage Vsw and is controlled by the signal N2 generated from the driver shown in Fig. 3. The voltage signal V2 is the output of the current-sense circuit and the capacitor is used to stabilize the output voltage as illustrated in Fig. 5a. Vsw is controlled by the gate driving signals Vp and Vn, which are the outputs of the driver. The voltage Vsw has large transient change, which may induce large burr in V2. To remove the burr, delays between Vsw and N2 are introduced in our design as described in Fig. 6. In addition, to eliminate the noise of the signal Nsoft, which is the output of the current comparator as described in Fig. 3, feedback is used to control the output voltage V2 of the current-sense circuit. When NsoftN2 is 11 that denotes over-current is detected and current-sense is disabled, the transistor MP4 turns on and quickly steps up the voltage V2 to make the signal Nsoft return to 0. When Nsoft returns to 0, NsoftN2 is 01, MP5 turns on to boost the voltage V2 to Vin waiting for the next sensing time. The simple and delicate design eliminates the potential large burr in V2 and the noise of the signal Nsoft.

From the above discussion, when the sensed inductor current IL reaches the value of ILpeak, the signal Nsoft changes the state from logic low to logic high such that the power transistor M1 turns off. That is, the inductor peak current is limited step by step during soft-start stage. Moreover, we propose the circuit which senses the output voltage Vo. As Vo climbs higher than the typical value Vtyp, the control signal LD goes logic high to set code D0D1D2 to 111 to end the soft-start. As shown in Fig. 4, the start-up time mainly depends on the load current. The lighter the load is, the more charge will transfer to the output capacitor during start-up and Vo will reach to the typical value Vtyp faster. Thus, with the decrease in load current soft-start time is reduced. On the other hand, during soft-start period, the average inductor current higher than the load current is used to enhance the output voltage, and in normal state, the average inductor current equals to the output current. In that case, when transition happens from soft-start phase to normal phase, the extra current will ow to the capacitor to charge and

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Fig. 4. Soft-start key waveforms under: (a) full load and (b) no load.

It ensures the effectiveness of the current sensor with approximate zero DC power consumption. Simulation results as given in Fig. 7 show that the sampling delay td2 is around 10 ns and td1 is around 7 ns, which are adequate to remove the large burr appearing in V2. 2.3. Current comparator The comparator is used to generate the over-current signal. Fast response is needed to increase the control speed of the softstart stage. This comparator, shown in Fig. 8, is implemented by a

differential input stage, a folded cascode stage and a clamping stage [14]. The gain of the differential input stage is given by ! 1 , 8 gmM1,2 R1,2 == gdsM1,2 and the gain of the cascode stage is     1 1 1 : == gmM9 gmbM9 ==R4 gmM5,6 gdsM11 gdsM9 gdsM6

In Eqs. (8) and (9), gm and gds denote transconductance and output conductance of a transistor, respectively. The accuracy of

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Fig. 5. Current-sense circuit (a) the schematic (b) the logic.

V3 VGSM15 . The output stage is used to increase the response of the comparator output signal. The simulation results are shown in Fig. 9. The 3.6 V direct current voltage is put on the input in+. The rectangle pulse with 500 ns width is connected with the input in . For the case without clamping, the voltage V1 varies between 0 and 3.6 V. When the clamping circuit is added, the range of V1 is from 0.7 to 2.7 V. The simulation results show that the delay time has been reduced by 22% when the clamping stage is added. 2.4. Driver In our design, a driver with delicate control is necessary to provide buffer and dead-time control. Buffer and dead-time control are needed to avoid shoot-through current loss, which is one kind of power losses in the switch mode converter [15]. Fig. 10 shows the driver applied in our design. When Q is high, Vn is set to zero, power transistor M2 turns off. Through the feedback signals at Vn and A1, Vp is forced to zero, power transistor M1 turns on. Similarly, when Q is low, Vp is set to increase; power transistor M1 turns off. Through the feedback signals at Vp and A2, Vn is forced to increase; power transistor M2 turns on. The basic principle is to use the feedback signals to control the gate driving signals such that the power transistors M1 and M2 do not turn on simultaneously. The feedback signals at A3, A4, A5, A6 are used to decrease the time needed for the gate voltage of M1 and M2 to rise and fall and to avoid the case that M3, M4 and M5, M6 turn on simultaneously. The simulation results show that the rise and fall times of Vp are only about 5 and 5 ns, respectively, while those of Vn are only about 10 and 20 ns, respectively, and the dead-time is about 30 ns in this design. Moreover, the driver generates the signal N2 to control the current sensor. From the schematic in Fig. 10, delay time exists between N2 and gate driving signals Vp and Vn, which control the voltage Vsw. It results in that td1 and td2 can be observed as shown in Fig. 7. In addition, a signal MNoff is also introduced to turn off M2 at light load to improve efciency, which will be discussed later. 2.5. System implementation
Fig. 7. The simulated results of Nsoft, N2, Vsw and V2.

Fig. 6. The timing of Nsoft, N2 and Vsw.

the comparator is improved through high-gain amplication stage. It will further increase the accuracy of the current sensor. The clamping circuit is adopted to increase the speed of the comparator. When the drain voltage of the transistor M9 increases to the level that can turn on the transistor M16, M16 turns on and the voltage V1 is limited to V2 VSGM16 . When the drain voltage of the transistor M9 decreases to the level that can turn on the transistor M15, M15 turns on and the voltage V1 is clamped to

Fig. 11 shows the overall system. The proposed soft-start circuit and power transistors have been integrated in the control chip of a DCDC voltage-mode buck converter to reduce the cost. During start-up, the controller uses the output signal Nsoft of the soft-start circuit and oscillator output signal CLK to lift the output voltage. As Vo reaches the typical value, soft-start function stops working. During normal state, the signal NPWM and CLK are used to realize feedback control. The divided voltage of Vo (Vfb) is sensed by Error amplier (EA). The output voltage of EA (Ver_out) is compared with saw tooth generators output signal Vramp to

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Fig. 8. Current comparator.

Fig. 9. Waveforms of the comparator (a) without clamping and (b) with clamping.

generate NPWM. The upper edge of the signal CLK turns M1 on and as soon as Vramp exceeds Ver_out, M1 is turned off. Under the control, the output voltage is regulated at a stable value. The bandgap reference and bias circuits are included to generate voltage and current references of the controller chip. Moreover, zero current detector (ZCD) is introduced to prevent inductor current from going negative at the boundary of continuous conduction mode (CCM) and discontinuous conduction mode (DCM). This ZCD function can prevent the output capacitor discharge, which will reduce the efciency of converter. The function of ZCD is to generate the signal MNoff to turn off M2 (M1 is closed already) when IL reaches zero [16].

3. Results and discussions The proposed soft-start circuit has been applied in a synchronous DCDC voltage-mode buck converter with a standard 0.5 mm

CMOS process. Fig. 12 shows the layout of the proposed controller. Its effective die area is 1.38 mm 0.90 mm, including pads and ESD structures. Table 1 summarizes the post-simulation results for the main specications of the proposed converter. All these features show that it is suitable for portable electronic devices, which are powered by battery. The proposed soft-start circuit occupies 0.06 mm2 on silicon, which corresponds to about one twentieth of the total area of controller. Although the soft-start circuit introduces 53.5 mA quiescent current, it adds current-limiting function, which increases the reliability of the system. In order to verify the proposed soft-start technique, experiments have been performed to check the overshoot voltage. The input voltage of the converter is set to nominal value, which is 3.6 V. Fig. 13 shows the post-simulated key waveforms with the proposed soft-start scheme under no load and full load. Signal LD is the internal signal of the soft-start circuit described in Fig. 3.

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Fig. 10. Schematic of the driver.

Fig. 11. Block diagram of overall system.

The results show that during soft-start, the inductor peak current is limited step by step. The clock signal CLK and the output signal Nsoft of the soft-start circuit control the switching of the power transistors to transfer energy to the output. As soon as the output voltage climbs to Vtyp, which is 1.8 V in our design, LD will change from logical low to high to end the soft-start process, and when the converter enters in the normal state, CLK and the output signal NPWM of the PWM comparator control the switching of the power transistors. The results show that the start-up time can be intelligently adjustable by load current. The switch current is

designed in steps of typically ILpeak4/4, ILpeak4/2, 3/4ILpeak4 and then the typical current limit ILpeak4 is 1.6 A. The lighter the load is, the less the start-up time is. The maximum start-up time of the converter is around 760 ms with 22 mF output capacitor under 1.3 A load current. The HSPICE simulation results show that the output voltage can stably start-up until the output voltage sets up. A comparison of start-up process is made using two soft-start methods. Fig. 14 shows the post-simulated output voltage and inductor current of the same voltage-mode buck converter under conventional current-mode soft-start method described in Fig. 1.

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Fig. 12. The layout of the proposed converter.

Table 1 Overall chip performance. Parameters Input voltage range (Vin) Output voltage Maximum output current Efciency External inductance L1 External capacitance C1 External divided resistors Switching frequency Ripple voltage MOSFET model MOSFET sizing Rds (PMOS) Rds (NMOS) Input DC bias current DC bias current of soft-start circuit Results 2.65.5 V 1.8 V 1.3 A 92% (max at Vin 3.6 V, Vo 1.8 V, ILOAD 300 mA) 4.7 mH 22 mF 470 KO for R1; 180 KO for R2 1.25 MHz 30 mv (PWM) BSIM3V3 model (Normal Voltage) 0.60 mm 0.80 mm 0.3 O (at VGS 3.6 V) 0.2 O (at VGS 3.6 V) 350 mA 53.5 mA (16 mA of DAC-controlled current reference; 37.5 mA of current comparator)

As a remark, the typical current limit ILpeak is also set to 1.6 A, which is realized through xing the high bits of the counter (Qnc 2 Qnc 1 ) 11 during the whole soft-start process in our design. The results show that the output voltage can stably start-up under full load. However, when the load current decreases, especially when the load current is zero, output voltage overshoot becomes large. To further verify the improvement in the proposed soft-start technique. A comparison of overshoot is made using two soft-start methods mentioned above. Fig. 15 shows the simulated overshoot of the output voltage as a function of the output current. The overshoot curve a is obtained based on the proposed soft-start scheme. The overshoot curve b is obtained when the conventional current-mode method is applied. The maximum overshoot (2.7% at ILOAD 0 A) by the novel soft-start scheme is less than that with the conventional scheme by 5%. The results show that the overshoot voltage has been largely reduced in a wide range of load currents.

Therefore, experiments are in good agreement with the theoretical analysis that introducing DAC-controlled soft-start circuit can effectively reduce the output voltage overshoot of the converter and ensure smooth output voltage when the converter starts up.

4. Conclusion This paper presents a compact soft-start scheme applied to voltage-mode DCDC converters. Compared to conventional constant ILpeak control, DAC-controlled ILpeak control is adopted to largely reduce the overshoot voltage. The soft-start circuit including low-power current sensor, fast current comparator and driver with delicate control has been designed and fully integrated. The proposed soft-start scheme has been successfully implemented and veried with a buck converter in a 0.5 mm CMOS technology.

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Fig. 13. Post-simulated key waveforms with the proposed soft-start scheme with 22 mF output capacitor: (a) ILOAD 1.3 A and (b) ILOAD 0 A.

Fig. 15. The overshoot of the output voltage by the two soft-start schemes under different output currents.

References
[1] R.W. Erickson, D. Maksimovic, in: Fundamentals of Power Electronics, Kluwer Academic Publishers, New York, 2001, pp. 19. [2] Mengxiong Yang, Ke Jin, Xinbo Ruan, Min Xu, Soft start strategy for bi-directional DCDC converter, IEEE Power Electronics Specialists Conference (PESC) (2007) 161164. [3] S.H. Penzin, W.R. Crain, K.B. Crawford, et al., The SEU pulse width modulation controllers with soft start and shutdown circuits. IEEE Radiation Effects Data Workshop, USA, 1993, pp. 7379. [4] F.Y. Shih, Y.T. Chen, D.Y. Chen, et al.. A pspice-compatible model of PWM IC for switching power converters with soft-start characteristic, in: Proceedings

Fig. 14. Post-simulated Vo and IL with the conventional soft-start scheme with 22 mF output capacitor: (a) ILOAD 0 A and (b) ILOAD 1.3 A.

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[5] [6] [7]

[8]

[9]

[10]

of International Conference on Power Electronics and Drive Systems, Singapore, 1995, pp. 335340. LM3224 Data Sheet, National Semiconductor, Sep. 2005. (Online), available: /http://www.national.com/ds/LM/LM3224.pdfS. Maxim8727 Data Sheet, Maxim, Sep. 2005, (Online), available: /http://datasheets.maxim-ic.com/en/ds/MAX8727.pdfS. Mohammad Al-Shyoukh, Hoi Lee, A compact ramp-based soft-start circuit for voltage regulators, IEEE Transactions on CAS-II: Express Briefs 56 (7) (2009) 535539. J. Yuan Bing, Lai Xinquan,Ye Qiang, Jia Xinzhang. A novel compact soft-start circuit with internal circuitry for DCDC converters, IEEE Seventh International Conference on ASICON 0 07, 2007, pp. 450453. C.R. Young, W.H. Yoo, A new soft-start method with abnormal over current protection function for switching power supplies, IEEE International Conference on Electric Machines and Drives, San Antonio, TX, 2005, pp. 421425. Michael M. Walters, Charles E. Hawkes, et al., DCDC Converter With Inductor Current Sensing and Related Methods, United States Patent, No. 5982160, 1999.

[11] X.Q. Lai, J.P. Guo, A novel digital soft-start circuit for DCDC switching regulator, Sixth International Conference on ASIC Proceedings, Shanghai, China, 2006, pp. 554558. [12] C.F. Lee, P.K.T. Mok, On-chip current sensing technique for CMOS monolithic switch-mode power converters, IEEE International Symposium on Circuits and Systems, Scottsdale, AZ, vol. 5 2002, pp. 265268. [13] C.F. Lee, P.K.T. Mok, A monolithic current-mode CMOS dcdc converter with on-chip current-sensing technique, IEEE Journal of Solid-State Circuits 39 (1) (2004) 314. [14] P.E. Allen, D.R. Holberg, in: CMOS Analog Circuit Design, Oxford University Press, 2002, pp. 372375. [15] C.A. Yoo, CMOS buffer without short-circuit power consumption, IEEE Transactions on Circuits and Systems II 47 (9) (2000) 935937. [16] Wan-Rone Liou, Mei-Ling Yeh, Yueh Lung Kuo, A high efciency dual-mode buck converter IC for portable applications, IEEE Transactions on Power Electronics 23 (2) (2008) 667677.