Lecture 1-1 Brief Overview: For a MOSFET in saturation, DC current is determined by VGS VT (VGST ) .

For long channel MOSFETs :

I D , SAT =

kn W k W . .(VGS Vtn ) 2 = n . .(VD ,SAT ) 2 2 L 2 L kn W . .(VGS Vtn ) 2 .(1 + (VDS VDS , SAT )) 2 L

For short channel devices:

I D , SAT =

Output Impedance is:

ro =

I D , SAT
1 L2 ; ro 2 L V DS , SAT

Triode (Linear) Region For a MOSFET where VGS Vt and VDS VGS Vt , the device acts as a voltage controlled resistor.

I D = kn .

V2 W .((VGS Vt )VDS DS ) L 2 V2 W .((VSG Vtp )VSD SD ) L 2

For a PMOS:

ID = k . p

The resistance for a MOSFET in a triode is:

R 1 =

I D W = k . .(VGS Vt VDS ) p VDS L 1 W .(VGS Vt VDS ) L

Rds =

1 k . p W .(VGS Vt ) L

k . p

Lecture 1-1 Small Signal Models

Linearization around DC operating point.

iD = id + I D = where v gs + VGS = vGS

' kn W (v gs + VGS VT ) 2 2 L

Transconductance This is the voltage-to-current gain in analog circuits. It is an AC small signal parameter.
gm = i D vGS
' = kn I D ,VGS @ biaspo int

W (v gs +VGS VT ) L

' g m = 2k n

W ID L

Steps for small signal analysis:

1. Using DC equations, calculate I D ,VGS , VDS for the transistors. 2

Lecture 1-1

2. Calculate the small signal parameters g m and ro based on DC operating point.

3. Replace MOSFETs with their small signal equivalents and short all DC voltage sources and open all DC current sources.

D G S

g m v gs
S

g mb v SB

ro

OR

g mb =

Vt iD W = kn . .(Vgs Vt )( ) vSB L VSB = g m . 0.1 < < 0.5

g mb v BS

Design Practices for Device Sizing and Biasing: For analog design, we use L of at least 2 x minimum gate length. This is required for good output resistance and matching. For VDS , SAT , common practice is to choose around 5%-10% of VDD . For 2.5V design, around 125mV VDS , SAT is a good design practice. What happens to device parameters with temperature? The parameters that change with temperature are the mobility and threshold voltage.

kn =

n . ox where n is the mobility, ox is the oxide permittivity and tox is the oxide thickness. tox

N D , poly Vtn k ln( ) T q NA

VT kT k ( ) = = 0.085 mV / C T T q q
20 15 For N D 10 and N A 10 ,

Vtn 1mV / C T 3

Lecture 1-1 So Vtn decreases with increasing temperature.

1 Vtn . Vtn temperature co-efficient Vtn T Vtn (T ) = Vtn (To ).(1 + TCVtn .(T To )) TCVtn =

For a short channel device, TC of VTn is -2143 ppm/C. Mobility Degradation with Temperature:

T0 1.5 ) T T => K ' (T ) = K ' (T0 )( 0 )1.5 T

(T ) = (T0 )(

Temperature Co-Efficient of K at temperature To is given by:

' 1 K n (T ) 1.5 TCK n = ' = T K n (T ) T

Current Mirrors in CMOS Processes and Mismatch Mechanisms

Lecture 1-1

Iref

R Io

M1
kn W .( )1.(VGS 1 VT ) 2 .(1 + .(VDS1 VD ,SAT )) 2 L

M2

Vo

I REF =

VDS 1 = VGS1 VDS 1,SAT = VGS1 Vtn

IO =
' kn W ( ) 2 (VGS 1 VT ) 2 (1 + (VDS 2 V DS 1, SAT )) 2 L

IO I REF

(W / L) 2 (1 + (VO VDS 2, SAT ) . (W / L)1 (1 + (VDS 1 VDS1,SAT )

Vtn = 0.8

Mismatch Mechanisms in Current Mirrors:

Lecture 1-1

1. Vt Mismatch

Vt 2 V Vt n 2 = Vtn + t 2 IO 2Vt 2Vt 1 = 1 I REF VGS Vt VDS ,SAT Vt n1 = Vtn

To obtain better matching, higher VD , SAT (Vgs Vt ) is needed. 2. k Mismatch

kn 2 kn kn 2 = kn + 2 ' IO k n 1+ ' I REF kn kn1 = kn

For smaller geometries, k mismatch gets better. 3. VDS Mismatch : The biggest impact on current mismatch.

IO I REF

1 + 2 .Vo 1 + 1.VDS 1

Biasing Current Mirrors The most common methodology is to use a known, robust current mirror to bias the mirrors.

M1

M2

Io Iref
6

Lecture 1-1 Design Examples: MOSFET-only reference:

VDD = VSG 3 + VGS 1 VDD = Vtp + 2 I REF 2 I REF + Vtn + W W k .( )3 kn .( )1 p L L W 10 )1 = L 2

Lets assume that we want to use M3 as a resistor. Lets assign (

Solving for M3 size:

2.20 2.20 + 0.9 + + 0.8 5= W 10 40.( )3 120.( ) L 2 W )3 0.11 L W 10 ( )= L 90 (

Is this supply sensitive? 2 L3 2 L1 (VDD Vtp Vtn )2 = I REF + k'pW3 k'nW1 4 4 4 44 2 4 4 4 4 43 1
K 2

Lecture 1-1

IREF 2.VDD 2(Vtn + Vtp ) = VDD K K IREF = 12 A / V VDD

(around V D =5V, we get a 12nA change in I REF / mV change in V D ) D D