Subhash Patel

Personal Data
Address Email Phone A-2, Aarti Society, Payalnagar Road, Naroda, 382330-Ahmedabad subhash.bvm@gmail.com +91-9408590009

Education
Since October 2011 PhD Student at Gujarat Technological University Field : Automated Analog CMOS Circuit Design Master of Science in Microelectronics & Microsystems Hamburg University of Technology (TUHH), Hamburg, Germany Grade 1.4 (Very good) | Major: Microelectronics Bachelor of Engineering Electronics Sardar Patel University, Vallabhvidyanagar, India Result 81.79% (First class with distinction)

February 2010

June 2006

Work Experience
Since September-2010 April-2009 to February 2010 Assistant Professor in Indus College of Engineering, Ahmedabad Internship and Thesis at IPGEN Rechte GmbH, Bochum, Germany Field :- Analog and Mixed signal integrated circuit design Designed IP of CDR-PLL and Synthesizer PLL (Design, simulation, layout & verication) Optimized area of Resistive DAC Designed Analog multiplexer Engineer at Bombardier Transportation, India Field :- Electronics testing and design
Developed Train control and Management System for Indian Railways Locomotive Involved in testing of traction converter control electronics

July-2006 to July-2007

Master of Science Dissertation (Thesis)

February 2010 A Test-bench driven, automated design approach for high performance PLL for serial communication application
Advisors : Prof. Dr-Ing W Krautschneider (Hamburg University of Technology, Germany) Dipl-Ing. Reimund Wittmann (IPGEN Rechte GmbH, Bochum, Germany)

Designed and implemented CDR-PLL and Synthesizer PLL in 180nm CMOS Technology Developed and veried time ecient automated design approach for both PLLs Developed congurable IP of both PLLs Designed technology independent and congurable layouts of PLL EDA tool used : Mentor Graphics, Eldo simulator, 1STONE design management tool, MATLAB

Computer Skills
Programming Operating systems EDA tools C, C++ ,Verilog, VHDL, Python, AMPLE, MATLAB-script Windows XP & 7, Linux (Ubuntu and Fedora) Cadence IC DFII, Mentor Graphics, Magic VLSI, NG-Spice, Xilinx ISE , Synopsis

Academic Projects
January 2009 Digital control for DC-offset suppression with D/A Converter in biomedical ASIC
Advisor : Dr-Ing D. Schrder (Hamburg University of Technology, Germany)

System level design in MATLAB RTL implementation using Verilog-HDL coding Synthesis and verication of design using Cadence IC DFII, Technology CMOS 350nm Summer 2009 RTL design using Verilog-HDL of Currency coveter ASIC Tool used : Cadence IC DFII, Technology : 350nm UMC Design, simulation and implementation of Two stage Op-amp in 350nm CMOS technology Sun-tracker

Winter 2008 winter 2005

Scholarships, Certicates and Awards

February 2011 April 2008 December 2006 2002-2006 2006 Cleared GTU PhD examination Scholarship for the students with an excellent academic performance at TUHH Gold medal from Sardar Patel university and BVM Engineering college for securing highest rank at end of Bachelor study in Electronics branch 5 Gold/Silver Medals for excellent academic performance during Bachelor study Qualied in GATE Examination

Languages
Gujarati English Hindi German Mother tongue Fluent Fluent Basic Knowledge

Subhash Patel September 30, 2011