Ezdsp F28335: Reference Technical

eZdspTM F28335 Technical Reference
2007
DSP Development Systems
510195-0001 Rev. C November 2007
SPECTRUM DIGITAL, INC. 12502 Exchange Dr., Suite 440 Stafford, TX. 77477 Tel: 281.494.4505 Fax: 281.494.5310 sales@spectrumdigital.com www.spectrumdigital.com
IMPORTANT NOTICE Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any product or service without notice. Customers are advised to obtain the latest version of relevant information to verify data being relied on is current before placing orders. Spectrum Digital, Inc. warrants performance of its products and related software to current specifications in accordance with Spectrum Digitals standard warranty. Testing and other quality control techniques are utilized to the extent deemed necessary to support this warranty. Please be aware, products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant, nor is it liable for, the product described herein to be used in other than a development environment. Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does Spectrum Digital warrant or represent any license, either express or implied, is granted under any patent right, copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any combination, machine, or process in which such Digital Signal Processing development products or services might be or are used. WARNING This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user, at his own expense, will be required to take any measures necessary to correct this interference. TRADEMARKS eZdsp is a trademark of Spectrum Digital, Inc.
Copyright 2007 Spectrum Digital, Inc.
Contents
1 Introduction to the eZdspTM F28335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Provides a description of the eZdspTM F28335, key features, and board outline. 1.0 Overview of the eZdspTM F28335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....................................... 1.1 Key Features of the eZdspTM F28335 1.1.1 Hardware Features .................................................... 1.1.2 Software Features ..................................................... 1.2 Functional Overview of the eZdspTM F28335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 1-3 1-3 1-3 1-4
Operation of the eZdspTM F28335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the eZdspTM F28335. Information is provided on the eZdsps various interfaces. 2.0 The eZdspTM F28335 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1 The eZdspTM F28335 Board 2.1.1 Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2 eZdspTM F28335 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3 eZdspTM F28335 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.3.1 P1, JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.3.2 P2, Expansion Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3.3 P4,P8,P7, I/O Interface ............................................... 2-10 2.3.4 P5,P9, Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.3.5 P6, Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.6 P10 Expansion Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.7 P11, CANA Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.3.8 P12, RS-232 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.9 J11, CANB 5 x 2 Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.10 J12, SCI-B 5 x 2 Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.11 J201, Embedded USB JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.12 Connector Part Numbers ............................................. 2-19 TM F28335 Jumpers 2.4 eZdsp .............................................. 2-19 2.4.1 JP1, ADCREFIN Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.4.2 JR2, XTPD Voltage Select ............................................. 2-20 2.4.3 JR4, Connector P4, P8 Voltage Select .................................. 2-21 2.4.4 JR5, Connector P2, P10 Voltage Select .................................. 2-21 2.4.5 JR6, MUX GPIO22_24 Select ......................................... 2-22 2.4.6 JP7, CANA Termination Resistor Select .................................. 2-22 2.4.7 JP8, CANB Termination Resistor Select .................................. 2-23 2.5 LEDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.6 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.6.1 SW1, Boot Load Option Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.6.2 SW2, Processor Configuration Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.7 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 A eZdspTM F28335 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contains the schematics for the eZdspTM F28335 eZdspTM F28335 Mechanical Information .................................... Contains the mechanical information about the eZdspTM F28335 A-1
B-1
List of Figures Figure 1-1, Photo eZdspTM F28335 ................................... TM ............................ Figure 1-2, Block Diagram eZdsp F28335 TM ........................ Figure 2-1, eZdsp F28335 PCB Outline (Top) ..................... Figure 2-2, eZdspTM F28335 PCB Outline (Bottom) TM F28335 Memory Space .......................... Figure 2-3, eZdsp Figure 2-4, P1 Pin Locations ......................................... Figure 2-5, Connector P2 Pin Locations ................................ Figure 2-6, Connector P4/P8/P7 Connectors .......................... Figure 2-7, Connector P5/P9 Pin Locations ........................... Figure 2-8, Connector P6 Location .................................. TM Figure 2-9, eZdsp F28335 Power Connector ......................... Figure 2-10, Connector P10 Pin Locations ............................. Figure 2-11, P11, DB9 CANA Female Connector ....................... Figure 2-12, P12, DB9 RS-232 Female Connector ..................... Figure 2-13, J11 Pin Locations ...................................... Figure 2-14, J12 Pin Locations ...................................... Figure 2-15, Jumper JP1 ........................................... Figure 2-16, Jumper JR2 ........................................... Figure 2-17, Jumper JR4 ........................................... Figure 2-18, Jumper JR5 ........................................... Figure 2-19, Jumper JR6 ........................................... Figure 2-20, Jumper JP7 ........................................... Figure 2-21, Jumper JP8 ........................................... Figure 2-22, SW1, Boot Load Option Switch ........................... Figure 2-23, SW2, Processor Configuration ........................... Figure 2-24, eZdspTM F28335 Test Points (Bottom) ..................... 1-3 1-4 2-3 2-4 2-6 2-8 2-9 2-10 2-12 2-13 2-13 2-14 2-15 2-16 2-17 2-18 2-20 2-20 2-21 2-21 2-22 2-22 2-23 2-24 2-25 2-26
List of Tables Table 2-1, External Chip Select and Usages ........................... Table 2-2, eZdspTM F28335 Connectors .............................. Table 2-3, P1, JTAG Interface Connector ............................... Table 2-4, P2, Expansion Interface Connector ........................... Table 2-5, P4, I/O Connectors ..................................... Table 2-6, P8, I/O Connectors ..................................... Table 2-7, P7, I/O Connector ....................................... Table 2-8, P5/P9, Analog Interface Connector ......................... Table 2-9, P10, Expansion Interface Connector ....................... Table 2-10, P11, CANA Pinout ...................................... Table 2-11, P12, P12, RS-232 Pinout ................................. Table 2-12, J11, 5 x 2 Pinout ......................................... Table 2-13, J12, 5 x 2 Pinout ........................................ Table 2-14, J201, Embedded USB JTAG Interface ..................... TM Table 2-15, eZdsp F28335 Suggested Connector Part Numbers ...... TM ............................... Table 2-16, eZdsp F28335 Jumpers Table 2-17, JP1, U29, Pin 2 to ADCREFIN Select ...................... Table 2-18, JR2, XTPD Voltage Select .............................. Table 2-19, JR4, Connector P4, P8 Voltage Select ..................... Table 2-20, JR5, Connector P2, P10 Voltage Select .................... Table 2-21, JR6, MUX GPIO22 Select ............................... Table 2-22, JP7, CANA Termination Resistor Select .................... Table 2-23, JP8, CANA Termination Resistor Select .................... Table 2-24, LEDs ................................................ Table 2-25, SW1, Boot Load Option Switch ........................... Table 2-26, SW2, Processor Configuration Switch ..................... Table 2-27, Test Points ............................................ 2-5 2-7 2-8 2-9 2-10 2-11 2-11 2-12 2-14 2-15 2-16 2-17 2-18 2-18 2-19 2-19 2-20 2-20 2-21 2-21 2-22 2-22 2-23 2-23 2-24 2-25 2-25
About This Manual This document describes board level operations of the eZdspTM F28335 based on the Texas Instruments TMS320F28335 Digital Signal Controller (DSC). The eZdspTM F28335 is a stand-alone module permitting engineers and software developers evaluation of certain characteristics of the TMS320F28335 DSC to determine processor applicability to design requirements. Evaluators can create software to execute onboard or expand the system in a variety of ways. Notational Conventions This document uses the following conventions. The eZdspTM F28335 will sometimes be referred to as the eZdsp. eZdsp will include the socketed or unsocket version Program listings, program examples, and interactive displays are shown in a special italic typeface. Here is a sample program listing. equations !rd = !strobe&rw;
Information About Cautions This book may contain cautions. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software, hardware, or other equipment. The information in a caution is provided for your protection. Please read each caution carefully. Related Documents Texas Instruments TMS320F28335 Digital Signal Controllers Data Manual, literature #SPRS439 Texas Instruments TMS320C28x DSP CPU and Instruction Set Reference Guide, literature #SPRU430 Texas Instruments TMS320C28x Assembly Language Tools Users Guide, literature #SPRU513 Texas Instruments TMS320C28x Optimizing C/C++ Compiler Users Guide, literature #SPRU514 Texas Instruments Code Composer Studio Getting Started Guide, literature #SPRU509
Table 1: Manual History Revision A B C Production Release Updated Figures, Text, Schematics Updated Figures, Tables, Text History
Table 2: Board History PWB Revision A B Production Release Updated Silk-screen History
Chapter 1 Introduction to the eZdspTM F28335

This chapter provides a description of the eZdspTM for the TMS320F28335 Digital Signal Controller, key features, and block diagram of the circuit board.
Topic
1.0 1.1 1.1.1 1.1.2 1.2 Overview of the eZdspTM F28335 Key Features of the eZdspTM F28335 Hardware Features Software Features Functional Overview of the eZdspTM F28335
Page
1-2 1-3 1-3 1-3 1-4
1-1
Spectrum Digital, Inc

1.0 Overview of the eZdspTM F28335 The eZdspTM F28335 is a stand-alone card--allowing developers to evaluate the TMS320F28335 digital signal controller (DSC) to determine if it meets their application requirements. Furthermore, the module is an excellent platform to develop and run software for the TMS320F28335 processor. The eZdspTM F28335 is shipped with a TMS320F28335 DSC. The eZdspTM F28335 allows full speed verification of F28335 code. Several expansion connectors are provided for any necessary evaluation circuitry not provided on the as shipped configuration. To simplify code development and shorten debugging time, a C2000 Code Composer StudioTM driver is provided. In addition, an onboard JTAG connector provides interface to emulators, with assembly language and C high level language debug.
Figure 1-1, eZdsp F28335
1-2

1.1 Key Features of the eZdspTM F28335 1.1.1 Hardware Features The eZdspTM F28335 has the following features: TMS320F28335 Digital Signal Controller 150 Mhz. operating speed On chip 32-bit floating point unit 68K bytes on-chip RAM 512K bytes on-chip Flash memory 256K bytes off-chip SRAM memory On chip 12 bit Analog to Digital (A/D) converter with 16 input channels 30 MHz. input clock On board RS-232 connector with line driver On board CAN 2.0 interface with line driver and connector Multiple Expansion Connectors (analog, I/O) On board embedded USB JTAG Controller 5-volt only operation with supplied AC adapter On board IEEE 1149.1 JTAG emulation connector 1.1.2 Software Features TI F28xx Code Composer StudioTM Integrated Development Environment, Version 3.3 Texas Instruments Flash APIs to support the F28335 Texas Instruments F28335 header files and example software
1-3

1.2 Functional Overview of the eZdspTM F28335 Figure 1-1 shows a block diagram of the basic configuration for the eZdspTM F28335. The major interfaces of the eZdsp are the JTAG interface, and expansion interface.
30 Mhz.
U S B P O R T
A N A L O G
XTAL1/OSCIN ANALOG TO DIGITAL CONVERTER

E X P A N S I O N
USB PORT/JTAG CONTROLLER
JTAG
TMS320F28335
EXTERNAL JTAG CAN-A CAN-B RS-232 SCI-B CANA CANB SCIA SCIB XZCS7n 128K x 16 SRAM
I / O E X P A N S I O N
Figure 1-2, BLOCK DIAGRAM eZdspTM F28335
1-4
Chapter 2 Operation of the eZdspTM F28335
This chapter describes the operation of the eZdspTM F28335, key interfaces and includes a circuit board outline.
Topic
2.0 2.1 2.1.1 2.2 2.2.1 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 2.3.10 2.3.11 2.3.12 The eZdspTM F28335 Operation The eZdspTM F28335 Board Power Connector eZdspTM F28335 Memory Memory Map eZdspTM F28335 Connectors P1, JTAG Interface P2, Expansion Interface P4/P8/P7, I/O Interface P5/P9, Analog Interface P6, Power Connector P10, Expansion Interface P11, CANA Connector P12, RS-232 Connector J11, CANB 5 x 2 Header J12, SCIB 5 x 2 Header J201, Embedded USB JTAG Interface Connector Part Numbers
Page
2-3 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-18 2-19
2-1
Spectrum Digital, Inc Topic

2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.5 2.6 2.6.1 2.6.2 2.7 eZdspTM F28335 Jumpers JP1, ADCREFIN Select JR2, XTPD Voltage Select JR4, Connector P4, P8 Voltage Select JR5, Connector P2, P10 Voltage Select JR6, MUX GPIO22_24 Select JP7, CANA Termination Resistor Select JP8, CANB Termination Resistor Select LEDs Switches SW1, Boot Load Option Switch SW2, Processor Configuration Switch Test Points
Page
2-19 2-20 2-20 2-21 2-21 2-22 2-22 2-23 2-23 2-24 2-24 2-25 2-26
2-2

2.0 The eZdspTM F28335 Operation This chapter describes the eZdspTM F28335, key components, and operation. Information on the eZdsps various interfaces is also included. The eZdspTM F28335 consists of four major blocks of logic: Analog Interface Connector I/O Interface Connector On board Memory JTAG Interface Embedded USB JTAG Controller Interface
2.1 The eZdspTM F28335 Board The eZdspTM F28335 is a 5.35 x 3.0 inch, multi-layered printed circuit board, powered by an external 5-Volt only power supply. Figure 2-1 shows the layout of the top side of the F28335 eZdsp. P6 DS1 J201 P1
SW1 SW2 P4 P7 P8 JP1 P5 P9 J11 P2
DS201
P10
J12 JP8 P11 P12 JP7 Figure 2-1, eZdspTM F28335 PCB Outline (Top) 2-3 DS2

Figure 2-2 shows the layout of the bottom side of the F28335 eZdsp.
JR6
JR4
JR5
JR2
Figure 2-2, eZdspTM F28335 PCB Outline (Bottom) 2.1.1 Power Connector The eZdspTM F28335 is powered by a +5 Volt only power supply, included with the unit. The power is supplied via connector P6. If expansion boards are connected to the eZdsp, a higher amperage power supply may be necessary.
2-4

2.2 eZdspTM F28335 Memory The eZdsp includes the following on-chip memory: 256K x 16 Flash 8 blocks of 4K x 16 single access RAM (SARAM) 2 blocks of 8K x 16 SARAM 2 blocks of 1K x 16 SARAM
In addition 128K x 16 off-chip SRAM is provided. The processor on the eZdsp can be configured for boot-loader mode or non-boot-loader mode. The eZdsp can load ram for debug or FLASH ROM can be loaded and run. For larger software projects it is suggested to do a initial debug with on eZdsp F28335 module which supports a total RAM environment. With careful attention to the I/O mapping in the software the application code can easily be ported to the F28335. The table below shows the external chip select signal and its use. Table 1: External Chip Select and Usage Chip Select Signal XZCS0n XZCS6n XZCS7n Use Expansion header Expansion Header External SRAM
2-5

2.2.1 Memory Map The figure below shows the memory map configuration on the eZdspTM F28335.
Figure 2-3, eZdspTM F28335 Memory Space Note: The on-chip flash memory has a security key which can prevent visibility when enabled. 2-6 eZdspTM F28335 Technical Reference

2.3 eZdspTM F28335 Connectors The eZdspTM F28335 has fourteen connectors. The function of each connector is shown in the table below: Table 2: eZdspTM F28335 Connectors Connector P1 P2 P4/P8/P7 P5/P9 P6 P10 P11 P12 J11 J12 J201 Function JTAG Interface Expansion I/O Interface Analog Interface Power Connector Expansion CAN-A SCI-A CAN-B SCI-B Embedded JTAG
2-7

2.3.1 P1, JTAG Interface The eZdspTM F28335 is supplied with a 14-pin header interface, P1. This is the standard interface used by JTAG emulators to interface to Texas Instruments DSPs. The positions of the 14 pins on the P1 connector are shown in the diagram below as viewed from the top of the eZdsp.
P1 13 14 2 1
Fig 2-4, P1 Pin Locations The definition of P1, which has the JTAG signals is shown below. Table 3: P1, JTAG Interface Connector Pin # 1 3 5 7 9 11 13 Signal XTMS XTDI XTPD (+3.3/5V) T_TDO T_TCK RET XTCK T_EMU0 Pin # 2 4 6 8 10 12 14 Signal XTRSTGND no pin USBSEL GND GND T_EMU1
WARNING !
The TMS320F28335 supports +3.3V Input/Output levels which are NOT +5V tolerant. Connecting the eZdsp to a system with +5V Input/Output levels will damage the TMS320F28335. If the eZdsp is connected to another target then the eZdsp must be powered up first and powered down last to prevent lactchup conditions.
2-8

2.3.2 P2, Expansion Interface The positions of the 60 pins on the P2 connector are shown in the figure below.
1 2
P2 Figure 2-5, Connector P2 Pin Locations The definition of P2, which has the I/O signal interface is shown below. Table 4: P2, Expansion Interface Connector
Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 Signal +3.3V/+5V/NC * GPIO79_XD0 GPIO77_XD2 GPIO75_XD4 GPIO73_XD6 GPIO71_XD8 GPIO69_XD10 GPIO67_XD12 GPIO65_XD14 GPIO40_XA0_XWE1n GPIO42_XA2 GPIO44_XA4 GPIO46_XA6 GPIO80_XA8 GPIO82_XA10 GPIO84_XA12 GPIO86_XA14 GND GPIO36_SCIRXDA-XZCS0n GPIO34_ECAP1_XREADY GPIO35_SCIRXDA_XRNW GPIO38_WE0n +3.3V DSP_RSn GND GND GPIO39_XA16 GPIO30_CANRXA_XA18 GPIO15_XHOLDAn_SCIRXDB_MFSXB No connect Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 Signal +3.3/+5V/NC * GPIO78_XD1 GPIO76_XD3 GPIO74_XD5 GPIO72_XD7 GPIO70_XD9 GPIO68_XD11 GPIO66_XD13 GPIO64_XD15 GPIO41_XA1 GPIO43_XA3 GPIO45_XA5 GPIO47_XA7 GPIO81_XA9 GPIO83_XA11 GPIO85_XA13 GPIO87_XA15 GND GPIO37_ECAP2_XZCS7n B_GPIO28_SCIRXDA_XZCS6n 10K Pull-up XRDn No connect XCLKOUT GND GND GPIO31_CANTXA_XA17 GPIO14_TZ3n_XHOLDn_SCITXB_MCLKXB GPIO29_SCITXDA_XA19 No connect
* Default is No Connect (NC). User can jumper to +3.3V or +5V on backside of eZdsp with JR5. 2-9

2.3.3 P4/P8/P7, I/O Interface The connectors P4, P8, and P7 present the I/O signals from the DSC. The layout of these connectors are shown below. P4
2 1 10 20 39 40 20
P8
P7 Figure 2-6, P4/P8/P7 Connectors The pin definition of the P4 connector is shown in the table below. Table 5: P4, I/O Connectors
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Signal +3.3V/+5V/NC * No connect GPIO22_EQEP1S_MCLKRA_SCITXDB GPIO7_EPWM4B_MCLKRA_ECAP2 GPIO23_EQEP1_MFSXA_SCIRXDB GPIO5_EPWM3B_MFSRA_ECAP1 GPIO20_EAEP1A_MXDA_CANTXB GPIO21_EQEP1B_MDRA_CANRXB No connect GND GPIO3_EPWM2B_ECAP5_MCLKRB GPIO1_EPWM1B/ECAP6/MFSRB No connect No connect No connect No connect No connect GPIO14_TZ3n_XHOLD_SCITXDB_MCLKXB GPIO15_TZ4n_XHOLDA_SCIRXDB_MFSXB GND
2-10

The pin definition of the P8 connector is shown in the table below. Table 6: P8, I/O Connectors
Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Signal +3.3V/+5V/NC * MUX_GPIO29_SCITXDA_XA19 GPIO14_TZ3n_XHOLD_SCITXDB_MCLKXB GPIO21_EQEP18_MDRA_CANRXB GPIO0_EPWM1A GPIO2_EPWM2A GPIO4_EPWM3A GPIO27_ECAP4_EQEP2S_MFSXB GPIO13_TZ2N_CANRXB_MDRB GND GPIO7_EPWM4B_MCLKRA_ECAP2 GPIO16_SPISIMOA_CANTXB_TZ5n GPIO18_SPICLKA_SCITXDB_CANRXA _MUX_GPIO31_CANRXA_XA17 MUX_GPIO11_EPWM6B_SCIRXDB_ECAP4 MUX_GPIO9_EPWM5B_SCITXDB_ECAP3 MUX_GPIO22 GPIO26_ECAP3_EQEP21_MCLKXB GPIO12_TZ1N_CANTXB_MDXB GND Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Signal +3.3V/+5V/NC * MUX_GPIO28_SCIRXDA_XZCS6n GPIO20_EAEP1A_MXDA_CANTXB GPIO23_EQEP1_MFSXA_SCIRXDB GPIO1_EPWM1B/ECAP6/MFSRB GPIO3_EPWM2B_ECAP5_MCLKRB GPIO5_EPWM3B_MFSRA_ECAP1 GPIO6_EPWMN4A_EPWMSYNCI/EPWMSYNCO GPIO34_ECAP1_XREADY GND GPIO15TZ4n_XHOLDA_SCIRXDB_MFSXB GPIO17_SPISOMIA_CANRXB_TZ6n GPIO19_SPISTAn_SCIRXDB_CANTXA MUX_GPIO30_CANRXA_XA18 MUX_GPIO8EPWM5A_CANTXB_ADCSOCA0nP3 MUX_GPIO10_EPWM6A_CANRXB_ADCASOCB0n GPIO25_ECAP2_EPEQ2B_MDRB GPIO32_SDAA_EPWMSYNCI_ADCSOCAOn GPIO33_SCLA_EPWNSYNCVO_ADCSOCBOn GND
* Default is No Connect (NC). User can jumper to +3.3V or +5V on backside of eZdsp with JR4. The P7 connector is supplied for backwards compatibility. Signals from other connectors can be wired to this connector to support existing user interfaces. The pin definition of P7 connector is shown in the table below. Table 7: P7, I/O Connector
Pin # 1 2 3 4 5 6 7 8 9 10 Signal No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect Pin # 11 12 13 14 15 16 17 18 19 20 Signal No connect No connect No connect No connect No connect No connect No connect No connect No connect GND
2-11

2.3.4 P5/P9, Analog Interface The position of the 30 pins on the P5/P9 connectors are shown in the diagram below as viewed from the top of the eZdsp.
1 2 1
P9
ANALOG
Figure 2-7, Connector P5/P9 Pin Locations The definition of P5/P9 signals are shown in the table below. Table 8: P5/P9, Analog Interface Connector P5 Pin # 1 2 3 4 5 6 7 8 9 10 Signal ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7 ADCREFM ADCREFP P9 Pin # 1 3 5 7 9 11 13 15 17 19 Signal GND GND GND GND GND GND GND GND GND GND P9 Pin # 2 4 6 8 10 12 14 16 18 20 Signal ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7 ADCLO * No connect
* Connect ADCLO to AGND or ADCLO of target system for proper ADC operation.
2-12
P5
10 20 19

2.3.5 P6, Power Connector Power (5 volts) is brought onto the eZdspTM F28335 via the P6 connector. The connector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. The position of the P6 connector is shown below.
POWER
Figure 2-8, Connector P6 Location
The diagram of P6, which has the input power is shown below.
+5V P6 Ground PC Board Front View Figure 2-9, eZdspTM F28335 Power Connector
P6
2-13

2.3.6 P10, Expansion Interface The positions of the 60 pins on the P10 connector are shown in the figure below.
Pin 2
eZdsp TMS320F28335
P10
EXPANSION
Pin 60
Pin 1
Figure 2-10, Connector P10 Pin Locations The definition of P10, which has the I/O signal interface is shown below. Table 9: P10, Expansion Interface Connector
Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 Signal +3.3V/+5V/NC GPIO63_SCITXDC_XD16 GPIO61_MFSRB_XD18 GPIO59_MFSRA_XD20 GPIO57_SPISTEAn_XD22 GPIO55_SPISOMIA_XD24 GPIO53EQEP1_XD26 GPIO51_EAEP1B_XD28 GPIO49_ECAP6_XD30 No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect No connect GND Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 Signal +3.3V/+5V/NC GPIO62_SCIRXDC_XD17 GPIO60_MCLKRB_XD19 GPIO58_MCLKRA_XD21 GPIO56_SPICLKA_XD23 GPIO54_SPISIMOA_XD25 GPIO52_EQEP1S_XD27 GPIO50_EQEP1A_XD29 GPIO48_ECAP5_XD31 No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect GND
Pin 59
2-14

2.3.7 P11, CANA Connector The eZdsp F28335 has a 9 Pin female D-connector which brings out the CANA transmit and receive signals. This CAN interface uses the SN65HVD235 CAN driver. The pin positions for the P11 connector as viewed from the edge of the printed circuit shown below.
5 9 4 8 3 7 2 6 1
Figure 2-11, P11, DB9 CANA Female Connector The pin numbers and their corresponding signals are shown in the table below. Table 10: P11, CANA Pinout
Pin # 1 2 3 4 5 6 7 8 9 Signal Name No Connect CANLA GND No Connect No Connect No Connect CANHA No Connect No Connect
2-15

2.3.8 P12, RS-232 Connector The eZdsp F28335 has an RS-232 connector which brings out the SCIA transmit and receive signals to be used as UART. This UART uses the MAX3238 RS-232 line driver and is routed to a male 9 pin D-connector, P12. The pin positions for the P10 connector as viewed from the edge of the printed circuit board are shown below.
5 9 4 8 3 7 2 6 1
Figure 2-12, P12, DB9 RS-232 Female Connector The pin numbers and their corresponding signals are shown in the table below. This corresponds to a standard dual row to DB-9 connector interface used on personal computers. Table 11: P12, RS-232 Pinout
Pin # 1 2 3 4 5 6 7 8 9 Signal Name No Connect PCRXDA PCTXDA No Connect GND No Connect No Connect No Connect No Connect N/A Out In Direction
2-16

2.3.9 J11, CANB 5 x 2 Header The CANB signals are routed through the SN65HVD235 CAN driver to a 5 x 2 double row header, J11. The pin numbers for J11 and their corresponding signals are shown in the table below. Table 12: J11, 5 x 2 Pinout
Pin # 1 3 5 7 9 Signal Name No Connect CANLB GND No Connect No Connect Pin # 2 4 6 8 10 Signal Name No Connect CANHB No Connect No Connect No Connect
The location of the pins are shown in the figure below. DSC Socket J11 CAN-B
Pin 1
Pin 2
Figure 2-13, J11 Pin Locations
2-17

2.3.10 J12, SCIB 5 x 2 Header The SCIB signals are routed through the MAX3238 line driver to a 5 x 2 double row header, J10. The pin numbers for J12 and their corresponding signals are shown in the table below. Table 13: J12, 5 x 2 Pinout
Pin # 1 3 5 7 9 Signal Name No Connect PCRXDB PCTXDB No Connect GND N/A Out In Direction Pin # 2 4 6 8 10 Signal Name No Connect No Connect No Connect No Connect No Connect Direction
The location of the pins are shown in the figure below. DSP Socket J12 SCI-B
Pin 1
Pin 2
Figure 2-14, J12 Pin Locations
2.3.11 J201, Embedded USB JTAG Interface The USB connector J201 is used to connect to the host development system which is running the software development suite. The signals on this connector are shown in the table below. Table 14: J201, Embedded USB JTAG Interface
Pin # 1 2 3 4 5 Signal Name USBVDD DD+ NC USBVSS
2-18

2.3.12 Connector Part Numbers The table below shows the part numbers for connectors which can be used on the eZdspTM F28335. Part numbers from other manufacturers may also be used. Table 15: eZdspTM F28335 Suggested Connector Part Numbers Connector P1 P2 Male Part Numbers SAMTEC TSW-1-10-07-G-T SAMTEC TSW-1-20-07-G-T *SSW or SSQ Series can be used Female Part Numbers SAMTEC SSW-1-10-01-G-T SAMTEC SSW-1-20-01-G-T
2.4 eZdspTM F28335 Jumpers The eZdspTM F28335 has 7 jumpers available to the user which determine how features on the eZdspTM F28335 are utilized. The table below lists the jumpers and their function. The following sections describe the use of each jumper. Table 16: eZdspTM F28335 Jumpers Jumper # JP1 JR2 JR4 JR5 JR6 JP7 JP8 Size 1x2 1x3 1x3 1x3 1x3 1x2 1x2 Function U29, Pin 2 to ADCREFIN +3.3/5V to XTPD +5/3.3V to P4, P8 +5/3.3V to P2, P10 MUX GPIO22_24 Select CANA Terminator Resistor CANB Terminator Resistor Position As Shipped From Factory Installed +3.3 volts Not populated Not populated GPIO24 Installed Installed
2-19

2.4.1 JP1, ADCREFIN Select Jumper JP1 is used to connect the output of U29, REF3020 to ADCREFIN. When the jumper is shorted the +2.048 voltage level is routed to the ADCREFIN signal of the DSC. When the jumper is open the ADCREFIN floats.The positions are shown in the table below. Table 17: JP1, U29, Pin 2 to ADCREFIN Select Position
Shorted * Open
Function
Output of U29 (+2.048V) connected to ADCREFIN Use internal reference for ADCREFIN
* as shipped from factory The layout of this jumper is shown in the figure below. DSC JP1 Installed/shorted DSC JP1 Open
Figure 2-15, Jumper JP1 2.4.2 JR2, XTPD Voltage Select Jumper JR2 is a surface mount jumper located on the bottom side of the board. To use a configuration a zero ohm resistor should be used for shorting. This jumper is used to select either +3.3 or +5 volts to be touted to the XTPD pin on the external JTAG header P1, pin 5. In configuration A, +5 volts is routed to XTPD. When configuration B is selected +3.3 volts is routed to XTPD. This is shown below. Table 18: JR2, XTPD Voltage Select Configuration
A * B
Function
+5 volts routed to XTPD +3.3 volts routed to XTPD
* default The layout of this jumper is shown in the figure below. +5V
1 JR2 3 1 JR2
+3.3V
3
Configuration A
Configuration B
Figure 2-16, Jumper JR2 2-20 eZdspTM F28335 Technical Reference

2.4.3 JR4, Connector P4, P8 Voltage Select Jumper JR4 is a surface mount jumper located on the bottom side of the board. To use a configuration a zero ohm resistor should be used for shorting. This jumper allows the user to bring +5 or +3.3 volts to connector P4, pin1, and connector P8, pins 1 and 2. When configuration A is used +5 volts is brought to the connectors. Configuration B routes +3.3 volts to these connectors. These settings are shown below. Table 19: JR4, Connector P4, P8 Voltage Select Configuration
A B
Function
+5 volts routed to P2, pins 1, P8, pins 1,2 +3.3 volts routed to P2, pins 1, P8, pins 1,2
The layout of this jumper is shown in the figure below. +5 volts

1 JR4 3 1 JR4
+3.3 volts
3
Configuration A
Configuration B
Figure 2-17, Jumper JR4
2.4.4 JR5, Connector P2, P10 Voltage Select Jumper JR5 is a surface mount jumper located on the bottom side of the board. To use a configuration a zero ohm resistor should be used for shorting. This jumper allows the user to bring +5 or +3.3 volts to connector P2, pin1 and 2, and connector P10, pins 1 and 2. When configuration A is used +5 volts is brought to the connectors. Configuration B routes +3.3 volts to these connectors. These settings are shown below. Table 20: JR5, Connector P2, P10 Voltage Select Configuration
A B
Function
+5 volts routed to P2, pins 1,2, P10, pins 1,2 +3.3 volts routed to P2, pins 1,2, P10, pins 1,2
The layout of this jumper is shown in the figure below.

3 JR5
+5 volts
1
+3.3 volts
3
JR5 1
Configuration A
Configuration B
Figure 2-18, Jumper JR5
2-21

2.4.5 JR6, MUX GPIO22_24 Select Jumper JR6 is a surface mount jumper located on the bottom side of the board. To use a configuration a zero ohm resistor should be used for shorting. This jumper is used to route the signal GPIO22 or GPIO24 to connector P8, pin 33 (MUX GPIO22). In configuration A GPIO22 is selected. When configuration B is used GPIO24 is selected. These configurations are shown below. Table 21: JR6, MUX GPIO22 Select Configuration
A B *
Function
GPIO22 routed to MUX GPIO22_24 GPIO24 routed to MUX GPIO22_24
* as shipped from factory The layout of this jumper is shown in the figure below.
GPIO22 3 JR6 1 GPIO24 3 JR6 1
Configuration B Configuration A Figure 2-19, Jumper JR6
2.4.6 JP7, CANA Termination Resistor Select Jumper JP7 is used to select the termination resistor on the CANA interface. When installed a termination resistor is placed between pins 2 and 7 of the connector P7. This jumper is installed at the factory. The positions are shown in the table below. Table 22: JP7, CANA Termination Resistor Select Configuration
Installed/shorted Open
Function
Termination resistor installed Termination resistor NOT resistor installed
JP7 Installed/shorted
JP7 Open
Figure 2-20, Jumper JP7
2-22

2.4.7 JP8, CANB Termination Resistor Select Jumper JP8 is used to select the termination resistor on the CANB interface. When installed a termination resistor is placed between pins 3 and 4 of the connector J11. This jumper is installed at the factory. The positions are shown in the table below. Table 23: JP8, CANB Termination Resistor Select Configuration
Installed/shorted Open
Function
Termination resistor installed Termination resistor NOT resistor installed
JP8 JP8 Open Installed/shorted Figure 2-21, Jumper JP8
2.5 LEDs The eZdspTM F28335 has three light-emitting diodes. DS1 indicates the presence of +5 volts and is normally on when power is applied to the board. LED DS2 is under control of the GPIO32 line from the processor. DS201 is connected to the embedded USB emulator and shows the status of the emulation link. These are shown in the table below. Table 24: LEDs LED #
DS1 DS2 DS201
Color
Green Green Green
Controlling Signal
+5 Volts GPIO32 Embedded emulation link status
2-23

2.6 Switches The eZdspTM F28335 has two switches. SW1 is used to select the power on boot load options. SW2 is used to select the processor configuration.
2.6.1 SW1, Boot Load Option Switch Switch SW1 is used to select the boot load option used by the F28335 processor on power up. These selections are shown in the table below. Table 25: SW1, Boot Load Option Switch
PIN 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Position 4 Boot-3 XA15 OFF OFF OFF OFF OFF OFF OFF OFF ON ON ON ON ON ON ON ON Position 3 Boot-2 XA14 OFF OFF OFF OFF ON ON ON ON OFF OFF OFF OFF ON ON ON ON Position 2 Boot-1 XA13 OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON OFF OFF ON ON Position 1 Boot-0 XA12 OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON Boot Mode Jump to Flash SCI-A boot SPI-A boot * I2C-A boot eCAN-A boot McBSP-A boot Jump to XINTX x16 Jump to XINTX x32 Jump to OTP Parallel GPIO I/O boot Parallel XINTF boot Jump to SARAM Branch to check boot mode Branch to Flash, skip ADC CAL Branch to SARAM, skip ADC CAL Branch to SCI, skip ADC CAL
* As shipped from the factory. The figure below shows the layout of SW1.
SW1 BOOT ON 1 2 Raised NIB ON Position
Figure 3-22, SW1, Boot Load Option Switch (default) 2-24 eZdspTM F28335 Technical Reference
3 4

2.6.1 SW2, Processor Configuration Switch Switch SW2 is used to select the processor configuration. The eZdspTM F28335 supports 2 on board SCI ports and 2 on board CAN ports. These ports can be used on board or routed to expansion connectors. Switch SW2 controls this configuration. These selections are shown in the table below. Table 26: SW2, Processor Configuration Switch Position
1 1 2 2 3 3 4 4 5 5 6 6
State
OFF ON * OFF ON * OFF ON * OFF ON * OFF ON * OFF ON *
Value
1 0 1 0 1 0 1 0 1 0 1 0
Function
Select GPIO28, GPIO29, GPIO30, GPIO31 as expansion Select GPIO28, GPIO29, GPIO30, GPIO31 as on board SCI/CAN A Disable MUX U22 Enable MUX U22 Select GPIO8, GPIO9, GPIO10, GPIO11 as expansion Select GPIO8, GPIO9, GPIO10, GPIO11 as on board SCI/CAN B Disable MUX U23 Enable MUX U23 Write protect I2C EEPROM Enable Writes to I2C EEPROM I2C EEPROM lowest address is 1 I2C EEPROM lowest address is 0
* default The figure below shows the layout of SW2.

SW2 ON 1 2 Raised NIB ON Position
Figure 3-23, SW2, Processor Configuration Switch (default)
3 4 5 6 CONFIG
2-25

2.7 Test Points The eZdspTM F28335 has fifteen test points. Their location on the bottom of the board are shown in the figure below.
TP1 TP4 TP3 TP2
Figure 2-24, eZdspTM F28335 Test Points (Bottom)
2-26

The signals each test point is tied to is listed in the table below. Table 27: Test Points Test Point
TP1 TP2 TP3 TP4
Signal
AGND XCLKOUT U8(DSP) Pin 81, TEST1 U8(DSP) Pin 82, TEST2
2-27
2-28
Appendix A eZdspTM F28335 Schematics
The schematics for the eZdspTM F28335 can be found on the CD-ROM that accompanies this board. The schematics were drawn on ORCAD. The schematics are correct for both the socketed and unsocketed version of the eZdspTM.
WARNING !
The TMS320F28335 supports +3.3V Input/Output levels which are NOT +5V tolerant. Connecting the eZdsp to a system with +5V Input/Output levels will damage the TMS320F28335. If the eZdsp is connected to another target then the eZdsp must be powered up first and powered down last to prevent lactchup conditions.
Design Notes: 1. The TMS320F28335 X1/CLKIN pin is +1.8 volt input. The clock input is buffered with a SN74LVC1G14 whose supply is +1.8 volts. This provides +3.3 volts to the +1.8 volt clock translation. Refer to sheet 4 of the schematics.
A-1
A-2
4 3 2 1
REVISIONS REV DESCRIPTION DATE APPROVED
A B PRODUCTION RELEASE 15-Sept-2007

D
ALPHA RELEASE
29-July-2007
SCHEMATIC CONTENTS
SHEET01 SHEET02 SHEET03 SHEET04 SHEET05 SHEET06 SHEET07 SHEET08 SHEET09 SHEET10 SHEET11 SHEET12 SHEET13 SHEET14 JTAG POWER PLACEMENT TOP PLACEMENT BOTTOM TITLE PAGE TMS320F28335 DSP DSP DECOUPLING CAPS BOOT SWITCHES,OSC MEMORY I/O MULTIPLEXING CAN, RS232 EMIF EXPANSION I/O EXPANSION ANALOG EXPANSION
C
The TMS320F28335 EzDSP design is based on preliminary information(SPRS439 June 2007) for the TMS320F28335 device. This schematic is subject to change without notification. Spectrum Digital Inc. assumes no liability for applications assistance, customer product design or infringement of patents described herein.
DWN CHK ENGR A 14 A NEXT ASSY APPLICATION

4
DATE DATE DATE DATE DATE DATE DATE
REVISION STATUS OF SHEETS
REV ENGR-MGR QA MFG USED ON RLSE
SPECTRUM DIGITAL INCORPORATED Title: Page Contents: Size:B Date:

3 2
SH
REV
TMS320F28335 EzDSP Title Block DWG NO 510192-0001 Wednesday, November 07, 2007
1
SH
10
11
12
13
REV 7
Revision: B Sheet 1 of 14
SH
VDD3VFL
VDD IO
VDD
( 3.3V )
( 3.3V )
( 1.8V )
84
9 71 93 107 121 143 159 170 4 15 23 29 61 101 109 117 126 139 146 154 167
U8
VDD3VFL.1
C11 and C12 are 0805 Size use biggest trace allowable with no vias to connect these to processor FLASH - 3.3V VDD I/0 -3.3V VDD CORE - 1.8V-1.9V
10 10 10 10 10 10 10 10
ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7
ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7
42 41 40 39 38 37 36 35 ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7
AGND
VDDIO(3V3).1 VDDIO(3V3).2 VDDIO(3V3).3 VDDIO(3V3).4 VDDIO(3V3).5 VDDIO(3V3).6 VDDIO(3V3).7 VDDIO(3V3).8 VDD(1V8).1 VDD(1V8).2 VDD(1V8).3 VDD(1V8).4 VDD(1V8).5 VDD(1V8).6 VDD(1V8).7 VDD(1V8).8 VDD(1V8).9 VDD(1V8).10 VDD(1V8).11 VDD(1V8).12 VDD(1V8).12
10 10 10 10 10 10 10 10
ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7
ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7
46 47 48 49 50 51 52 53 ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7 ADCREFP ADCREFM 56 55
GPIO40/XA0/XWE1n GPIO41/XA1 GPIO42/XA2 GPIO43/XA3 GPIO44/XA4 GPIO45/XA5 GPIO46/XA6 GPIO47/XA7 GPIO80/XA8 GPIO81/XA9 GPIO82/XA10 GPIO83/XA11 GPIO84/XA12 GPIO85/XA13 GPIO86/XA14 GPIO87/XA15 GPIO39/XA16
151 152 153 156 157 158 161 162 163 164 165 168 169 172 173 174 175
GPIO40_XA0_XWE1n 5,8 GPIO41_XA1 5,8 GPIO42_XA2 5,8 GPIO43_XA3 5,8 GPIO44_XA4 5,8 GPIO45_XA5 5,8 GPIO46_XA6 5,8 GPIO47_XA7 5,8 GPIO80_XA8 5,8 GPIO81_XA9 5,8 GPIO82_XA10 5,8 GPIO83_XA11 5,8 GPIO84_XA12 4,5,8 GPIO85_XA13 4,5,8 GPIO86_XA14 4,5,8 GPIO87_XA15 4,5,8 GPIO39_XA16 5,8
10
ADCREFP
2.2uF CERAMIC LOW ESR
10 ADCREFM
ADCREFP C11 ADCREFM C12
2.2uF CERAMIC LOW ESR R294 22.1K
3 ADCREFIN 10 ADCLO
ADCREFIN ADCLO
57 54 43 ADCRESEXT ADCREFIN ADCLO
GPIO79/XD0 GPIO78/XD1 GPIO77/XD2 GPIO76/XD3 GPIO75/XD4 GPIO74/XD5 GPIO73/XD6 GPIO72/XD7
136 135 134 133 132 131 130 129
XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7
GPIO79_XD0 GPIO78_XD1 GPIO77_XD2 GPIO76_XD3 GPIO75_XD4 GPIO74_XD5 GPIO73_XD6 GPIO72_XD7
5,8 5,8 5,8 5,8 5,8 5,8 5,8 5,8
TMS320F28335 - 176 QFP
GPIO71/XD8 GPIO70/XD9 GPIO69/XD10 GPIO68/XD11 GPIO67/XD12 GPIO66/XD13 GPIO65/XD14 GPIO64/XD15 GPIO35/SCIRXDA/XRnW XRDn GPIO38/XWE0n GPIO36/SCIRXDA/XZCS0n GPIO37/ECAP2/XZCS7n GPIO34/ECAP1/XREADY GPIO28/SCIRXDA/XZCS6n GPIO29/SCITXDA/XA19 GPIO31/CANTXA/XA17 GPIO30/CANRXA/XA18 GPIO14/TZ3n/XHOLDn/SCITXDB/MCLKXB GPIO15/TZ4n/XHOLDAn/SCIRXDB/MFSXB XCLKOUT XRSn
128 127 124 123 122 119 116 115 148 149 137 145 150 142
XD8 XD9 XD10 XD11 XD12 XD13 XD14 XD15 RN2F R N2E RN2D R N2A RN2C R N2B
GPIO71_XD8 5,8 GPIO70_XD9 5,8 GPIO69_XD10 5,8 GPIO68_XD11 5,8 GPIO67_XD12 5,8 GPIO66_XD13 5,8 GPIO65_XD14 5,8 GPIO64_XD15 5,8
9 GPIO0_EPWM1A 9 GPIO1_EPWM1B/ECAP6/MFSRB 9 GPIO2_EPWM2A 9 GPIO3_EPWM2B_ECAP5_MCLKRB 9 GPIO4_EPWM3A 9 GPIO5_EPWM3B_MFSRA_ECAP1 9 GPIO6_EPWM4A_EPWMSYNCI/EPWMSYNCO 9 GPIO7_EPWM4B_MCLKRA_ECAP2 6 GPIO8_EPWM5A_CANTXB_ADCSOCAOnP3 6 GPIO9_EPWM5B_SCITXDB_ECAP3 6 GPIO10_EPWM6A_CANRXB_ADCSOCBOn 6 GPIO11_EPWM6B_SCIRXDB_ECAP4 9 GPIO12_TZ1n_CANTXB_MDXB 9 GPIO13_TZ2N_CANRXB_MDRB
5 6 7 10 11 12 13 16 17 18 19 20 21 24 GPIO0/EPWM1A GPIO1/EPWM1B/ECAP6/MFSRB GPIO2/EPWM2A GPIO3/EPWM2B/ECAP5/MCLKRB GPIO4/EPWM3A GPIO5/EPWM3B/MFSRA/ECAP1 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO GPIO7/EPWM4B/MCLKRA/ECAP2 GPIO8/EPWM5A/CANTXB/ADCSOCAOn GPIO9/EPWM5B/SCITXDB/ECAP3 GPIO10/EPWM6A/CANRXB/ADCSOCBOn GPIO11/EPWM6B/SCIRXDB/ECAP4 GPIO12/TZ1n/CANTXB/MDXB GPIO13/TZ2N/CANRXB/MDRB
6 5 4 1 3 2 141 2 176 1 25 26 138 80 TRSTn TCK TMS TDI TDO EMU0 EMU1 78 87 79 76 77 85 86
R8
A B A B A B A B A B A B
11 33 12 13 16 14 15
33 33 33 33 33
GPIO35_SCIRXDA_XRNW 8 XRDn 5,8 GPIO38_WE0n 5,8 GPIO36_SCIRXDA_XZCS0n 8 GPIO37_ECAP2_XZCS7n 5,8
GPIO34_ECAP1_XREADY 8,9 B_GPIO28_SCIRXDA_XZCS6n 8 GPIO28_SCIRXDA_XZCS6n 6 GPIO29_SCITXDA_XA19 6,8 GPIO31_CANTXA_XA17 6,8 GPIO30_CANRXA_XA18 6,8 GPIO14_TZ3n_XHOLD_SCITXDB_MCLKXB 8,9 GPIO15_TZ4n_XHOLDA_SCIRXDB_MFSXB 8,9 33 TP2 1 TEST POINT XCLKOUT XRSn C28_TRSTn C28_TCK C28_TMS C28_TDI C28_TDO C28_EMU0 C28_EMU1 8 11 11 11 11 11 11 11 11
VDD1A18 1.8V VDD2A18 VSS1AGND VSS2AGND
VDDA2(A3V3) VSSA2(AGND)
VDDAIO(A3V3).1 VSSAIO(AGND)
VSS.1 VSS.2 VSS.3 VSS.4 VSS.5 VSS.6 VSS.7 VSS.8 VSS.9 VSS.10 VSS.11 VSS.12 VSS.13 VSS.14 VSS.15 VSS.16 VSS.17 VSS.18 VSS.19 VSS.19 VSS.20 VSS.21
(NC) TEST2 (NC) TEST1
X1
X2
GPIO16/SPISIMOA/CANTXB/TZ5n GPIO17/SPISOMIA/CANRXB/TZ6n GPIO18/SPICLKA/SCITXDB/CANRXA GPIO19/SPISTEAn/SCIRXDB/CANTXA GPIO20/EQEP1A/MDXA/CANTXB GPIO21/EQEP1B/MDRA/CANRXB GPIO22/EQEP1S/MCLKXA/SCITXDB GPIO23/EQEP1/MFSXA/SCIRXDB GPIO24/ECAP1/EQEP2A/MDXB GPIO25/ECAP2/EQEP2B/MDRB GPIO26/ECAP3/EQEP2I/MCLKXB GPIO27/ECAP4/EQEP2S/MFSXB GPIO32/SDAA/EPWMSYNCI/ADCSOCAOn GPIO33/SCLA/EPWMSYNCO/ADCSOCBOn GPIO48/ECAP5/XD31 GPIO49/ECAP6/XD30 GPIO50/EQEP1A/XD29 GPIO51/EQEP1B/XD28 GPIO52/EQEP1S/XD27 GPIO53/EQEP1/XD26 GPIO54/SPISIMOA/XD25 GPIO55/SPISOMIA/XD24 GPIO56/SPICLKA/XD23 GPIO57/SPISTEAn/XD22 GPIO58/MCLKRA/XD21 GPIO59/MFSRA/XD20 GPIO60/MCLKRB/XD19 GPIO61/MFSRB/XD18 GPIO62/SCIRXDC/XD17 GPIO63/SCITXDC/XD16
ADC
XCLKIN
9 GPIO16_SPISIMOA_CANTXB_TZ5n 9 GPIO17_SPISOMIA_CANRXB_TZ6n 9 GPIO18_SPICLKA_SCITXDB_CANRXA 9 GPIO19_SPISTEAn_SCIRXDB_CANTXA 9 GPIO20_EAEP1A_MDXA_CANTXB 9 GPIO21_EQEP1B_MDRA_CANRXB 9 GPIO22_EQEP1S_MCLKRA_SCITXDB 9 GPIO23_EQEP1_MFSXA_SCIRXDB 9 GPIO24_ECAP1_EQEP2A_MDXB 9 GPIO25_ECAP2_EQEP2B_MDRB 9 GPIO26_ECAP3_EQEP2I_MCLKXB 9 GPIO27_ECAP4_EQEP2S_MFSXB 4,5,9 GPIO32_SDAA_EPWMSYNCI_ADCSOCAOn 5,9 GPIO33_SCLA_EPWNSYNCO_ADCSOCBOn 8 GPIO48_ECAP5_XD31 8 GPIO49_ECAP6_XD30 8 GPIO50_EQEP1A_XD29 8 GPIO51_EAEP1B_XD28 8 GPIO52_EQEP1S_XD27 8 GPIO53_EQEP1_XD26 8 GPIO54_SPISIMOA_XD25 8 GPIO55_SPISOMIA_XD24 8 GPIO56_SPICLKA_XD23 8 GPIO57_SPISTEAn_XD22 8 GPIO58_MCLKRA_XD21 8 GPIO59_MFSRA_XD20 8 GPIO60_MCLKRB_XD19 8 GPIO61_MFSRB_XD18 8 GPIO62_SCIRXDC_XD17 8 GPIO63_SCITXDC_XD16
27 28 62 63 64 65 66 67 68 69 72 73 74 75 88 89 90 91 94 95 96 97 98 99 100 110 111 112 113 114 31 59 32 58 34 33 45 44

TMS320F28335GF VDDA_1V8
3 8 14 22 30 60 70 83 92 103 106 108 118 120 125 140 144 147 155 160 166 171
82 81
104
102
VDDA_1V8
105
SPECTRUM DIGITAL INCORPORATED Title:

SINGLE POINT CONNECTION
( 1.8V )
VDDA_1V8 VDDA_1V8 VDDA_3V3 VDDA_3V3
4
( 1.8V )
TMS320F28335 EzDSP XCLKIN X2 X1

AGND
VDDA_3V3
( 3.3V )
4 4 4
Page Contents:
TMS320F28335
1 1
3
VDDA_3V3
( 3.3V )
TP3 TEST POINT TP4 TEST POINT

2
Size:B Date:
DWG NO
510192-0001 Wednesday, November 07, 2007

1
Revision: A Sheet 2 of 14
A-3
A-4
4 3 2 1
VDD
These caps go with U8

+
CT6 22uF
CT5 22uF
C19 0.1uF
C18 0.1uF
C5 0.1uF
C8 0.1uF
C21 0.1uF
C41 0.1uF
C40 0.1uF
C61 0.1uF
C59 0.1uF
D
VDDIO

C20 0.1uF C6 0.1uF C9 0.1uF C39 0.1uF C60 0.1uF
CT1 22uF
LOCATE NEAR DSP -- U8
VDDA_1V8 L4 VDDA_1V8 BLM21P221SN C2 1uF C58 0.1uF C56 0.001uF
1.9V
( 1.8V )
AGND
3.3V L3 VDDA_3V3 BLM21P221SN C3 1uF C38 0.1uF C37 ( 0.001uF VDDA_3V3

B
3.3V )
AGND
Tie in one point on the Ground plane

R25
VDDA_3V3 U29
AGND
TP1 1 TEST POINT
1 IN GND OUT
REF3020
AGND
2
C57 0.47uF JP1
SPECTRUM DIGITAL INCORPORATED
AGND
1 A B
JMP-2MM
ADCREFIN
ADCREFIN
Title: Page Contents: Size:B Date:
TMS320F28335 EzDSP DSP Decoupling Capacitors DWG NO 510192-0001 Wednesday, November 07, 2007
3 2 1

4
3.3V
PIN
BOOT-3 XA15 BOOT-2 XA14 BOOT-1 XA13 BOOT-0 XA12 MODE
R42 20K
0001 ON ON OFF ON OFF ON ON OFF OFF OFF ON OFF OFF ON ON OFF ON ON OFF OFF ON OFF ON OFF ON ON OFF OFF ON ON OFF OFF ON ON ON ON ON ON ON OFF 0010
R31 20K
R39 20K
R40 20K
0000 ON ON ON ON
Branch to SCI, skip ADC CAL

D
Branch to SARAM, skip ADC CAL Branch to Flash, skip ADC CAL Branch to check boot mode Jump to SARAM Parallel XINTF boot Parallel GPIO I/O boot Jump to OTP Jump to XINTF x32
C
SW1
R41 R15 R36 R37
2.2K 2.2K 2.2K 2.2K
1 2 3 4
GPIO84_XA12 GPIO85_XA13 GPIO86_XA14 GPIO87_XA15
0011 0100 0101
8 7 6 5
2,5,8 2,5,8 2,5,8 2,5,8 SW DIP-4/SM
XA12 XA13 XA14 XA15
3.3V L1
0110 0111
BLM21P221SN C43 0.1uF U11

1000
4 VCC OFFn
1001
1 2
1010
2 XCLKIN C42 NO-POP SMT/4PIN DIP

WHEN CRYSTAL IS USED POPULATE C42 WITH 0 OHM RESISTOR
R29
100
3 CLK
30MHz
Jump to XINTF x16 McBSP-A boot
GND
1011 1100 1101 1110
OFF OFF OFF OFF 1111 OFF
ON OFF OFF OFF OFF
OFF ON ON OFF OFF
OFF ON OFF ON OFF
eCAN-A boot I2C-A boot SPI-A boot SCI-A boot Jump to Flash
X1
2 R30 NO-POP
X2
2
Y2 C27 NO-POP
18 pF NOT POPULATED WHEN OSCILLATOR IS USED POPULATE R32 WITH 0 OHM RESISTOR 18 pF 30MHz
1
NO-POP C28 NO-POP R32 0
3.3V 3.3V
2
DS2 LTST-C150GKT GREEN R43
U12
C62 0.1uF
2,5,9 GPIO32_SDAA_EPWMSYNCI_ADCSOCAOn XF
2 1 3
SN74AHC1G14
4
220 Title: Page Contents: Size:B Date:
4 3 2
SPECTRUM DIGITAL INCORPORATED TMS320F28335 EzDSP Boot Switches/ OSC DWG NO 510192-0001 Wednesday, November 07, 2007
1
A-5
11 33
VDD1 VDD2
12 34
IS61LV6416-12T
VSS1 VSS2
A-6
4 3 2 1
3.3V
R9 10K
R10 10K
3.3V
6 I2C_ROM_WP R4 4.99K R3 4.99K
U21 6 I2C_ROM_ADD SCLA SDAA GPIO33_SCLA_EPWNSYNCO_ADCSOCBOn 2,9 GPIO32_SDAA_EPWMSYNCI_ADCSOCAOn 2,4,9 I2C_ROM_ADD
3.3V
1 2 3 4 A0 A1 NC1 VSS
24WC256
VCC WP SCL SDA
8 7 6 5
DSP
3.3V
C22 0.1uF
C10 0.1uF
ASRAM
U4
2,8 GPIO40_XA0_XWE1n 2,8 GPIO41_XA1 2,8 GPIO42_XA2 2,8 GPIO43_XA3 2,8 GPIO44_XA4 2,8 GPIO45_XA5 2,8 GPIO46_XA6 2,8 GPIO47_XA7 2,8 GPIO80_XA8 2,8 GPIO81_XA9 2,8 GPIO82_XA10 2,8 GPIO83_XA11 2,4,8 GPIO84_XA12 2,4,8 GPIO85_XA13 2,4,8 GPIO86_XA14 2,4,8 GPIO87_XA15 2,8 GPIO39_XA16
1 2 3 4 5 18 19 20 21 24 25 26 27 42 43 44 22 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 A11 A12 A13 A14 A15 A16 A17 A9 A10 NC CS WE OE BHE BLE 28
64Kx16, 128Kx 16 and 256Kx 16 Compatible
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
7 8 9 10 13 14 15 16 29 30 31 32 35 36 37 38
GPIO79_XD0 2,8 GPIO78_XD1 2,8 GPIO77_XD2 2,8 GPIO76_XD3 2,8 GPIO75_XD4 2,8 GPIO74_XD5 2,8 GPIO73_XD6 2,8 GPIO72_XD7 2,8 GPIO71_XD8 2,8 GPIO70_XD9 2,8 GPIO69_XD10 2,8 GPIO68_XD11 2,8 GPIO67_XD12 2,8 GPIO66_XD13 2,8 GPIO65_XD14 2,8 GPIO64_XD15 2,8
XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 XD8 XD9 XD10 XD11 XD12 XD13 XD14 XD15
2,8 GPIO37_ECAP2_XZCS7n 2,8 GPIO38_WE0n 2,8 XRDn
6 17 41 40 39
SPECTRUM DIGITAL INCORPORATED Title: Page Contents: Size: B Date:

4 3 2
TMS320F28335 EzDSP SRAM/SPI EEPROM DWG NO 510192-0001 Wednesday, November 07, 2007
1
Switch Position Function Select GPIO28,GPIO29,GPIO30,GPIO31 as expansion Select GPIO28,GPIO29,GPIO30,GPIO31 as on board SCI/CAN A
3.3V
Value
SW2-1
OFF
SW2-1 Disable Mux U22 Enable Mux U22

C25 0.1uF U22
ON
SW2-2
OFF
SW2-2 Select GPIO8,GPIO9,GPIO10,GPIO11 as expansion

2,8 GPIO29_SCITXDA_XA19
ON
16 VCC 1A 2A 9 12 8 3A 4A GND 4 7
SW2-3 Select GPIO8,GPIO9,GPIO10,GPIO11 as on board SCI/CAN B

2 GPIO28_SCIRXDA_XZCS6n 2,8 GPIO31_CANTXA_XA17 2,8 GPIO30_CANRXA_XA18
OFF
UART_TXDA 7 MUX_GPIO29_SCITXDA_XA19 9 UART_RXDA 7 MUX_GPIO28_SCIRXDA_XZCS6n 9 CAN_TXA 7 MUX_GPIO31_CANRXA_XA17 9 CAN_RXA 7 MUX_GPIO30_CANRXA_XA18 9
SW2-3 Disable Mux U23 Enable Mux U23 Write Protect I2C EEPROM Enable Writes to I2C EEPROM I2C EEPROM lowest address is 1 I2C EEPROM lowest address is 0
3.3V
ON
SW2-4
OFF
1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 S OE
2 3 5 6 11 10 14 13 1 15
SN74CBTLV3257PW
SW2-4
ON
SW2-5
OFF
SW2-5
ON
SW2-6
OFF
SW2-6
ON
C26 0.1uF
U23
16
2 GPIO9_EPWM5B_SCITXDB_ECAP3 3.3V 2 GPIO11_EPWM6B_SCIRXDB_ECAP4 2 GPIO8_EPWM5A_CANTXB_ADCSOCAOnP3 2 GPIO10_EPWM6A_CANRXB_ADCSOCBOn
VCC 4 7 9 12 8 1A 2A 3A 4A
UART_TXDB 7 MUX_GPIO9_EPWM5B_SCITXDB_ECAP3 9 UART_RXDB 7 MUX_GPIO11_EPWM6B_SCIRXDB_ECAP4 9 CAN_TXB 7 MUX_GPIO8_EPWM5A_CANTXB_ADCSOCAOnP3 9 CAN_RXB 7 MUX_GPIO10_EPWM6A_CANRXB_ADCSOCBOn 9

B
1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2
2 3 5 6 11 10 14 13 S 1 GND OE 15 SN74CBTLV3257PW
RN3 RN10K
SW2
1 2 3 4 5 6
SW DIP-6/SM
12 11 10 9 8 7
5 6 7 8
4 3 2 1
I2C_ROM_WP 5 I2 C_ROM_ADD 5 Title: Page Contents: Size:B Date:

4 3 2
SPECTRUM DIGITAL INCORPORATED TMS320F28335 EzDSP I/O MULTIPLEXING DWG NO 510192-0001 Wednesday, November 07, 2007
1
A-7
4 3 2 1
10
5 6 7 8
11
4 3 2 1
10
5 6 7 8
11
A-8
4 3 2 1
3.3V
RN9 RN10K U1
IDC SCI-A 2 3 4 7 3 6 8 4 7 8 9 10 9 5 2 6 1 1 DSUB-F
PCRXDA PCTXDA
24 23 22 19 17 DIN1 DIN2 DIN3 DIN4 DIN5 RIN1 RIN2 RIN3

P12 D B9F
5
6 UART_TXDA 6 UART_RXDA
DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 8 9 11 15

3.3V J12
5 6 7 10 12
6 UART_TXDB 6 UART_RXDB
21 20 18 16 ROUT1 ROUT2 ROUT3 ROUT1B INVALIDn FORCEON FORCEOFFn C1+ C10.1uF
1 6 2 7 3 8 4 9 5
13 14 28 25 VCC GND V+
C16 0.1uF C14 0.1uF
26 2 27
HEADER 5X2 PCRXDB PCTXDB
C13
1 3 C2+ C2VMAX3238CPW C17 0.1uF
1 3 5 7 9
2 4 6 8 10
4
C15 0.1uF
3.3V 3.3V
IDC 1 2 3 4 5 6 8 7 3 6 2 DSUB-F 1
RN10 RN10K U2
C23 0.1uF
5 AB TXD RXD
JMP-2MM
VCC CANH CANL GND 2 6

CANLA
3
JP7 CAN HA R23 120
CAN_TXA
1 B A 4 8 RS
SN65HVD235
1 6 2 7 3 8 4 9 5
P11 DB9F
CAN_RXA
7 8 9 10 9
3.3V
C24 0.1uF JP8
U3
5 AB TXD RXD RS
SN65HVD235
VCC CANH CANL GND 2 6

CANLB
3 7
CAN HB
R24
120
B A
1
JMP-2MM
1 3 5 7 9
2 4 6 8 10
J11 HEADER 5X2 Title: Page Contents: Size: B Date: TMS320F28335 EzDSP RS232/CAN DWG NO 510192-0001 Wednesday, November 07, 2007 Sheet 7 of Revision: A 14 SPECTRUM DIGITAL INCORPORATED
A
CAN_TXB
1 4 8
CAN_RXB

4 3
3.3V JR5
+5V
Make a solder connection on JR5 to the appropriate power supply. Note JR4 also can power domains so this jumper should be set accordingly.
C B 2
NO-POP
3 A
P2 GPIO79_XD0 GPIO77_XD2 GPIO75_XD4 GPIO73_XD6 GPIO71_XD8 GPIO69_XD10 GPIO67_XD12 GPIO65_XD14 2 2 2 2 2 2 2 2 GPIO63_SCITXDC_XD16 GPIO61_MFSRB_XD18 GPIO59_MFSRA_XD20 GPIO57_SPISTEAn_XD22 GPIO55_SPISOMIA_XD24 GPIO53_EQEP1_XD26 GPIO51_EAEP1B_XD28 GPIO49_ECAP6_XD30 GPIO78_XD1 GPIO76_XD3 GPIO74_XD5 GPIO72_XD7 GPIO70_XD9 GPIO68_XD11 GPIO66_XD13 GPIO64_XD15
P10 GPIO62_SCIRXDC_XD17 GPIO60_MCLKRB_XD19 GPIO58_MCLKRA_XD21 GPIO56_SPICLKA_XD23 GPIO54_SPISIMOA_XD25 GPIO52_EQEP1S_XD27 GPIO50_EQEP1A_XD29 GPIO48_ECAP5_XD31 2 2 2 2 2 2 2 2
3.3V
2,5 GPIO79_XD0 2,5 GPIO77_XD2 2,5 GPIO75_XD4 2,5 GPIO73_XD6 2,5 GPIO71_XD8 2,5 GPIO69_XD10 2,5 GPIO67_XD12 2,5 GPIO65_XD14 2,5 GPIO40_XA0_XWE1n 2,5 GPIO42_XA2 2,5 GPIO44_XA4 2,5 GPIO46_XA6 2,5 GPIO80_XA8 2,5 GPIO82_XA10 2,4,5 GPIO84_XA12 2,4,5 GPIO86_XA14 3.3V GPIO37_ECAP2_XZCS7n 2,5 B_GPIO28_SCIRXDA_XZCS6n 2 R5 10K XRDn XCLKOUT XCLKOUT 2
XA17 XA19
GPIO78_XD1 2,5 GPIO76_XD3 2,5 GPIO74_XD5 2,5 GPIO72_XD7 2,5 GPIO70_XD9 2,5 GPIO68_XD11 2,5 GPIO66_XD13 2,5 GPIO64_XD15 2,5 GPIO41_XA1 2,5 GPIO43_XA3 2,5 GPIO45_XA5 2,5 GPIO47_XA7 2,5 GPIO81_XA9 2,5 GPIO83_XA11 2,5 GPIO85_XA13 2,4,5 GPIO87_XA15 2,4,5
2 GPIO36_SCIRXDA_XZCS0n 2,9 GPIO34_ECAP1_XREADY 2 GPIO35_SCIRXDA_XRNW 2,5 GPIO38_WE0n 2,5 11 XA16 GPIO31_CANTXA_XA17 2,6 GPIO14_TZ3n_XHOLD_SCITXDB_MCLKXB 2,9 GPIO29_SCITXDA_XA19 2,6 DSP_RSn DSP_RSn
Tie off unused F24xx compatible signals.
2,5 GPIO39_XA16 2,6 GPIO30_CANRXA_XA18 2,9 GPIO15_TZ4n_XHOLDA_SCIRXDB_MFSXB

XA18
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
NO-POP
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
NO-POP
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
TMS320F28335 supports 3.3V input/output levels which are NOT 5V tolerant. Connecting the eZdsp to a system with 5V input/output levels will damage the TMS320F28335. If the eZdsp is connected to another target then the eZdsp must be powered up first and powered down last to prevent latchup conditions.
4 3 2 A
TMS320F28335 EzDSP EMIF EXPANSION CONNECTORS DWG NO 510192-0001 Wednesday, November 07, 2007
1
A-9
C B 2
NO-POP
2 GPIO24_ECAP1_EQEP2A_MDXB
A-10
7 6 5 4 3 2 1
3.3V +5V
JR4
3 A
Make a solder connection on JR4 to the appropriate power supply. Note JR5 also can power domains so this jumper should be set accordingly.
P4
P8
P7
2 GPIO22_EQEP1S_MCLKRA_SCITXDB 2 GPIO7_EPWM4B_MCLKRA_ECAP2 2 GPIO23_EQEP1_MFSXA_SCIRXDB 2 GPIO5_EPWM3B_MFSRA_ECAP1 2 GPIO20_EAEP1A_MDXA_CANTXB 2 GPIO21_EQEP1B_MDRA_CANRXB 2 GPIO7_EPWM4B_MCLKRA_ECAP2 2 GPIO16_SPISIMOA_CANTXB_TZ5n 2 GPIO18_SPICLKA_SCITXDB_CANRXA 6 MUX_GPIO31_CANRXA_XA17 6 MUX_GPIO11_EPWM6B_SCIRXDB_ECAP4 6 MUX_GPIO9_EPWM5B_SCITXDB_ECAP3 2 GPIO26_ECAP3_EQEP2I_MCLKXB 2 GPIO12_TZ1n_CANTXB_MDXB
6 MUX_GPIO29_SCITXDA_XA19 2,8 GPIO14_TZ3n_XHOLD_SCITXDB_MCLKXB 2 GPIO21_EQEP1B_MDRA_CANRXB 2 GPIO0_EPWM1A 2 GPIO2_EPWM2A 2 GPIO4_EPWM3A 2 GPIO27_ECAP4_EQEP2S_MFSXB 2 GPIO13_TZ2N_CANRXB_MDRB
MUX_GPIO28_SCIRXDA_XZCS6n 6 GPIO20_EAEP1A_MDXA_CANTXB 2 GPIO23_EQEP1_MFSXA_SCIRXDB 2 GPIO1_EPWM1B/ECAP6/MFSRB 2 GPIO3_EPWM2B_ECAP5_MCLKRB 2 GPIO5_EPWM3B_MFSRA_ECAP1 2 GPIO6_EPWM4A_EPWMSYNCI/EPWMSYNCO 2 GPIO34_ECAP1_XREADY 2,8
2 GPIO3_EPWM2B_ECAP5_MCLKRB 2 GPIO1_EPWM1B/ECAP6/MFSRB
2,8 GPIO14_TZ3n_XHOLD_SCITXDB_MCLKXB 2,8 GPIO15_TZ4n_XHOLDA_SCIRXDB_MFSXB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
GPIO15_TZ4n_XHOLDA_SCIRXDB_MFSXB 2,8 GPIO17_SPISOMIA_CANRXB_TZ6n 2 GPIO19_SPISTEAn_SCIRXDB_CANTXA 2 MUX_GPIO30_CANRXA_XA18 6 MUX_GPIO8_EPWM5A_CANTXB_ADCSOCAOnP3 6 MUX_GPIO10_EPWM6A_CANRXB_ADCSOCBOn 6 GPIO25_ECAP2_EQEP2B_MDRB 2 GPIO32_SDAA_EPWMSYNCI_ADCSOCAOn 2,4,5 GPIO33_SCLA_EPWNSYNCO_ADCSOCBOn 2,5
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
2 GPIO22_EQEP1S_MCLKRA_SCITXDB
JR6 JUMPER3_SMT
MUX_GPIO22
TMS320F28335 supports 3.3V input/output levels which are NOT 5V tolerant. Connecting the eZdsp to a system with 5V input/output levels will damage the TMS320F28335. If the eZdsp is connected to another target then the eZdsp must be powered up first and powered down last to prevent latchup conditions.
SPECTRUM DIGITAL INCORPORATED Title: Page Contents: Size: B Date:
7 6 5 4 3 2 A
TMS320F28335 EzDSP I/O EXPANSION CONNECTORS DWG NO 510192-0001 Wednesday, November 07, 2007 Sheet
1
Revision: A 9 of 14
P9
1 3 5 7 9 11 13 15 17 19 1 3 5 7 9 11 13 15 17 19
R1 ADCLO 2 0
2 4 6 8 10 12 14 16 18 20
2 4 6 8 10 12 14 16 18 20
ADCINA0 ADCINA1 ADCINA2 ADCINA3 ADCINA4 ADCINA5 ADCINA6 ADCINA7 2 2 2 2 2 2 2 2
AGND
R6 0
Connect ADCLO to AGND or to ADCLO of target system for proper ADC operation.
AGND
PLACE R6 AS CLOSE TO DSP AS POSSIBLE
P5
1 2 3 4 5 6 7 8 9 10
ADCREFM 2 ADCREFP 2
1 2 3 4 5 6 7 8 9 10
ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7 2 2 2 2 2 2 2 2

4 3 2
TMS320F28335 EzDSP Analog Expansion DWG NO 510192-0001 Wednesday, November 07, 2007
1
Revision: A Sheet 10 o f 14
A-11
XTPD
2 B C 3
JUMPER3_SMT JR2 3.3V R13 10K 3.3V
2 4 6 8 10 12 14 2 4 6 8 10 12 14 A
R16 10K R14 10K 10K
1 3 5 7 9 11 13
1 3 5 7 9 11 13
HEADER 7X2
U19 XTRSTn T_TRSTn XTMS T_TMS XTDI T_TDI XTCK T_TCK Locate R7,R54, C70 at the DSP XRSn pin for best EMI/ESD noise immunity.
R22
VCC 1A 2A 3A 4A GND 8 12 9 7 4
16
SN74LVC1G32 USB1 R18 33
A-12
4 3 2 1
+5V R80 XDS_4.1V +5V C80 0.1uF D2 1.5K
3
LM4040DCIM3-4.1
D
P1
C28_TRSTn 2 C28_TMS C28_TDI C28_TCK 2

C
3.3V
To/from expansion header
2 3 5 6 11 10 14 13 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 S OE 1 15

SN74CBT3257PW
2 2
XRSn is logical AND of PONRSnIN and emulator controlled reset. Power on default is PONRnIN controls XRSn. USBSEL 3.3V R54 XRSn
USBSEL - HIGH, SELECT USB EMULATION
R7 1.5K 100 2 10K

USBSEL - LOW, SELECT XDS EMULATION IF U13 IS INSTALLED THEN REMOVE R49 AND R48.
R20 100 C4 22pF
8 C70 22nF
DSP_RSn
R17
3.3V U26
1 4 2
Locate near DSP TCK pin
B
DSP_RS_OUT_ODn
+5V
3.3V
3.3V 5V
G ND T_TCK_RET T_TDO T_EMU0 T_EMU1
R19
33 C28_TDO 2 C28_EMU0 2
GND
T_TRSTn T_TMS T_TDI T_TCK T_TCK_RET T_TDO T_EMU0 T_EMU1
RESET_INn
PONRSnIN 12 R11 R12 10K 10K
3.3V
C28_EMU1 2
SPECTRUM DIGITAL INCORPORATED Embedded_USB Title: Page Contents: Size:B Date:

4 3 2
TMS320F28335 EzDSP EMULATION INTERFACE DWG NO 510192-0001 Wednesday, November 07, 2007
1
+5V 18.2K 1.899V U9
P6
5 6
+
CENTER SHUNT SLEEVE

C66 1.8VONn
1INA 1INB
VDD
1RESET
28
16.9K 1.848V 15.0K 1.773V 13.7K 1.722V
1.9V
RASM712 0.1uF
R44 220
CT2 47uF
4 1EN 1GND
0.1uF VDDIO R45 30.1K, 1% R35 NO-POP
+
2 2
+5V Max
3 22
1OUTA 1OUTB 1FB/SENSE

R33 18.2K, 1% C64 CT3 22uF
23 24 25
DS1 LTST-C150GKT GREEN
11 12
C65
2INA 2INB 2EN 2GND

+
2RESET
3.3V
10
0.1uF
9
CT4 22uF 0.1uF R46 0 R53 0
2OUTA 2OUTB 2SENSE

C63
17 18 19
VDD3VFL
R52 3.3V
0
C
NC1 NC2 NC3 NC4 NC5 NC6 29

TPS767D301
THERMAL_PAD
1 2 7 8 13 14 NC12 NC11 NC10 NC9 NC8 NC7
15 16 20 21 26 27
C1 1uF
C7 0.1uF
R2 10K TIE TPS767D301 POWER PAD TO GND PLANE (TI-SLMA002) PONRSnIN PONRSnIN
J2 NO-POP
B

4 3 2
TMS320F28335 EzDSP POWER SUPPLIES DWG NO 510192-0001 Wednesday, November 07, 2007
1
A-13
U4 A1 2
DS201
USB, 90-OHM, KEEP OUT
A14 1
J12
U21 44 P4 P8 P7 P5 P9 1 2 1 88
U207 1 D208
DS1
2
JP8
J11
A-14
4 3 2 1 D
INCHES 3
P1 P10
DS2
1 2 U12 2 1 2 1 P2 U19 132 P12

RN202 RN201
J204
L207
U202 U203 U8 SW1 D209 2 U210 SW2 J205 1
P11 1
B
P6
U9
1 2 1 1
JP7
5.5
INCHES
SPECTRUM DIGITAL INCORPORATED Title: TMS320F28335 EzDSP
ANALOG KEEP OUT AREA
Page Contents: Size:B Date:
PLACEMENT TOP DWG NO 510192-0001 Wednesday, November 07, 2007

3 2 1

4
PLACEMENT ON BOTTOM IS LOOKING THROUGH THE BOARD
INCHES 3
P1 P10 P2 JR5 J12
1 2 2 1 2 1
JR2
P12
U205
U1
1
C
U11 Y2 U2 U3 U26 P5 P9
JR4 P4 P8 P7 1 2 1 1
JR6 1 2 1
2
JP8
J11
P11 1
B
JP7
5.5
INCHES
SPECTRUM DIGITAL INCORPORATED
ANALOG KEEP OUT AREA
Title: Page Contents: Size:B Date:
TMS320F28335 EzDSP PLACEMENT BOTTOM DWG NO 510192-0001 Wednesday, November 07, 2007 Sheet 14 o f Revision: A 14
A-15
A-16
Appendix B eZdspTM F28335 MechanicaI Information
This appendix contains the mechanical information about the socketed and unsocketed versions of the eZdspTM F28335
B-1
B-2
This drawing is not to scale
B-3
B-4
Printed in U.S.A., November 2007 510195-0001 Rev. C

Ezdsp F28335: Reference Technical

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eZdspTM F28335 Technical Reference

DSP Development Systems

eZdspTM F28335 Technical Reference

510195-0001 Rev. C November 2007

Copyright 2007 Spectrum Digital, Inc.

Chapter 1 Introduction to the eZdspTM F28335

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Figure 1-1, eZdsp F28335

eZdspTM F28335 Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

XTAL1/OSCIN ANALOG TO DIGITAL CONVERTER

USB PORT/JTAG CONTROLLER

Figure 1-2, BLOCK DIAGRAM eZdspTM F28335

eZdspTM F28335 Technical Reference

Chapter 2 Operation of the eZdspTM F28335

Spectrum Digital, Inc Topic

eZdspTM F28335 Technical Reference

Spectrum Digital, Inc

SW1 SW2 P4 P7 P8 JP1 P5 P9 J11 P2

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eZdspTM F28335 Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

Spectrum Digital, Inc

Spectrum Digital, Inc

eZdspTM F28335 Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

eZdspTM F28335 Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

eZdspTM F28335 Technical Reference

Spectrum Digital, Inc

Figure 2-8, Connector P6 Location

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eZdspTM F28335 Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

eZdspTM F28335 Technical Reference

Spectrum Digital, Inc

Figure 2-13, J11 Pin Locations

Spectrum Digital, Inc

Figure 2-14, J12 Pin Locations

eZdspTM F28335 Technical Reference

Spectrum Digital, Inc

Spectrum Digital, Inc

Figure 2-16, Jumper JR2 2-20 eZdspTM F28335 Technical Reference

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The layout of this jumper is shown in the figure below. +5 volts

Figure 2-17, Jumper JR4

The layout of this jumper is shown in the figure below.

Figure 2-18, Jumper JR5

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Configuration B Configuration A Figure 2-19, Jumper JR6

The layout of this jumper is shown in the figure below.

Figure 2-20, Jumper JP7

eZdspTM F28335 Technical Reference

Spectrum Digital, Inc

The layout of this jumper is shown in the figure below.

JP8 JP8 Open Installed/shorted Figure 2-21, Jumper JP8

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