Flip-Flops: The Building Block Sequential Logic

Counters

Asynchronous Counters
async = events that DO NOT occur at the
same time

Asynchronous Counters
async = events that DO NOT occur at the
same time

async counter = FFs within the counter

DO NOT have a common clock pulse

async counter = FFs within the counter

DO NOT have a common clock pulse

Asynchronous Counters
async = events that DO NOT occur at the
same time

2-bit Asynchronous Binary Counter

async counter = FFs within the counter

DO NOT have a common clock pulse

2-bit Asynchronous Binary Counter

2-bit Asynchronous Binary Counter

0 0

1 0

0 1

1 1

3-bit Async Bin Counter

3-bit Async Bin Counter

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3-bit Async Bin Counter Asynchronous Counter a.k.a. Ripple Counter

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Propagational Delay
m d disa ajor v

age! ant

Calculate the delay

Bew are

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Asynchronous Decade Counters

Binary counters count from 0 to 2 (n=no. of FFs) What if ... you need to count just from 0 to 9?
n-1

The Answer
Do partial decoding

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BCD Decade Counters

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(4-bit asynchronous binary counter)

74LS93

(4-bit asynchronous binary counter)

74LS93

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(4-bit asynchronous binary counter)

74LS93
C C CTR DIV 12

CLK A CLK B RO(1) RO(2)

That was async...

Q0 Q1 Q2 Q3

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Synchronous Counter Now, its time for Synchronous counters

FFs in the counter are clocked at the same
time by a common clock pulse. counter...

Lets begin with a 2-bit synchronous binary

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2-bit Synchronous Binary Counter

Whats going on?

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What would we get?

3-bit Synchronous Binary Counter

delay is neglected for simplicity

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4-Bit Sync Bin Counter

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4-bit Synchronous Decade Counter

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Up/Down Sync Counters

Lets make one (3-bit counter)

progressing in either direction (up/down) may be called a bidirectional counter

0 1 2 3 4 5 4 3 2 3 4 5 6 7 6 5 etc... up dn up dn Q0: J0 = K0 = 1 Q1: J1 = K1 = (Q0 UP) + (Q0 DN) Q2: J2 = K2 = (Q0 Q1 UP) + (Q0 Q1 DN)
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Lets make one (3-bit counter)

Lets make one (3-bit counter)

Q0: J0 = K0 = 1 Q2: J2 = K2 = (Q0 Q1 UP) + (Q0 Q1 DN)

Q0: J0 = K0 = 1 Q1: J1 = K1 = (Q0 UP) + (Q0 DN) Q2: J2 = K2 = (Q0 Q1 UP) + (Q0 Q1 DN)
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Q1: J1 = K1 = (Q0 UP) + (Q0 DN)

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General Model of a Sequential Circuit

Design of Synchronous Counters

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Step 1: State Diagram

Step 2: Next-state Table

3-bit Gray code counter

The next state is the state that the counter goes to from its present state upon the application of a clock pulse.
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Step 3: Flip-op Transition Table

Step 4: Karnaugh Maps

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Step 4: Karnaugh Maps

Step 5: Logic Expressions for FF Inputs

J0 = Q2Q1+Q2Q1 = Q2 Q1 K0 = Q2Q1+Q2Q1 = Q2 Q1 J1 = Q2Q0 K1 = Q2Q0 K2 = Q1Q0

_ _ _ _

_ J2 = Q1Q0 _ _

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Step 6: Counter Implementation

K0 = Q2Q1+Q2Q1 = Q2 Q1

_ _ J0 = Q2Q1+Q2Q1 = Q2 Q1 _ _

J1 = Q2Q0 K1 = Q2Q0

J2 = Q1Q0 _ _ K2 = Q1Q0

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