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A Low-power Truly-modular1.8GHz Programmable Divider in Standard CMOS Technology

Cicero Vaucher and Zhenhua Wang Philips Research Labs Eindhoven, Philips Semiconductors Zurich cicero @natlab.research.philips.com, Z. Wang @zrh.sc.philips.com

Abstract
We present a modular and scalable divider architecture that is especially suited for low power applications. The implementation of the divider cells in SCL is described, and a new design method for power dissipation optimization, based on an AC simulation technique, is introduced. An 18bit implementation of the architecture in a conservative 0.3Spm bulk CMOS technology is described, which achieved state-of-the-art power eficiency and input sensitivity for CMOS silicon technologjes.

tecture is presented in section 11. Section I11 describes the logic andcircuit implementation of the divider cells. Section IV presents the power dissipation optimization technique, and sectionV discusses the input amplifier design. Section VI presents measured results on the 18bit divider test chip.

2. Modular Scalable and Programmable Divider Architecture

Programmable dividers have to operate at the highest VCO frequency, so power dissipation is the first consideration when defining their architecture. Furthermore, cir1. Introduction cuits which are robust w.r.t. scaling of CMOS technologies should have complicated delayloops. Scaling imno The feasibility of RF functions implemented CMOS in plies a variation of nominal gate delays, and in order to technology has been demonstrated by a.0. the work preattain full advantage of scaling the architecture should be sented in [ 11 [2]. They show that the scaling of CMOS transparent and delay insensitive. Therefore, the chosen technologies to deep sub-micron has made CMOS a vi-. architecture should provide easy optimization of power able option the low GHz range, and may be expected for it dissipation, fast designtimeandeasylayoutwork. In that CMOS is eventually going to replace bipolar in 'traother words, the architecture should be modular, based on ditional' RF building blocks: the,LNA, the mixer and the flexible and reusable building blocks. frequency synthesizer. Thedivider architecture based on a dual-modulus Complying to the miniaturisation and long battery life prescaler does not comply with these requirements; it is time trends requires CMOS building blocks with excelnot modular, because it requires two additional counters lentEMC characteristicsand low powerproperties. A and control circuits to provide desired division range; the critical RF buildingblockinthis context is the digital and it is not delay-insensitive, because the combination of programmablefrequencydivider. We describe a prothe dual-modulus prescaler with the counters comprises grammable dividerarchitecture especially suited for low complex delay loops, that have to respected at the highbe power applications. It is modular and scalable, and conest operating frequency.These delay loops have to be retains no complex delay loops. considered for every ney product, application or process Optimizing the power dissipation frequency dividers of scaling. So several different blocks have tobe designed, is a time consuming task. We devised an AC optimizaand, in order to be optimally tuned to the application, retion method that readily predicts the maximum toggling optimized each time. frequency of prescalers implemented in Source Coupled Logic ( S C L ) . An architecture complying with the objectives set in Achieving overall low power performance within the the first paragraph was described in [4], ind is depicted frequency synthesizer requires actions on several aspects on the left sideof figure 1. It consists of a chain of 2/3 diof the programmable divider design: not only the power vider cells connected likea ripple counter. Feedback lines dissipation ofthe divider is of importance, but also its are only present between two adjacent cells. The maxiinput sensitivity, which is mainly determined by the dimum delay between the MOD signal and the clock signal vider's input amplifier. We present here a programmable in a given cell that still allows correct operationequal to is divider circuit and its input amplifier, implemented in a tmnr 1.5 * T i n , Tin being the periodof the cell's input = standard 0.35pm bulk CMOS,The input sensitivityof the signal. As the input frequency each cellis scaled down for divider is the highest ever reported for CMOS implemen- each time, power optimization can performed by direct be tations. downscaling of the currents. The modular structure perThe low-power modular programmable divider archimits an existing design to be easily adapted for changes

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-In

I .

Po

Pn-2 P1

Pn-3

Figure 1. Modular programmable divider architecture

in input frequencyor division range, simply adding or by removing cells from the chain. The basic structure of n cells providesa minimum division ratio of 2", if their programming inputs are all set to zero. Each cell that has its programming input set to 1 divides by 3 once in a division cycle, at the moment the feedback signal mod becomes active. In this way it is possible to realize all integer division ratios from 2" to 2"+l - 1, roughly a factor two between minimum and maximumdivisionratios,for a fixedlength n Though this rangewould suffice for most narrow-band systems, it is not large enough for wide-band (TV-sat. reception) or multi-band (GSM-DCS1800) applications. We expanded the division range adjusting theefsecby live length n' of the chain to the required division ratio. A very convenient property of the structure is the direct relation between the performed division range bus and the programmed division word p,,, p,,-1, ... ,p1, po. It turns out that the required efsective length n' of the chain corresponds to the index of the MSB of the division word. Furthermore, setting the MOD input of a certain cell on the chain to the active level disables cells to the right all of that point, so that n can be easily set. Only a few ex' tra OR gates are required to adapt n to the programmed ' division word, as depicted on the right side of figure 1. With the additionallogic the division range becomes:

logic

Rout

MOD-out

_iy ,
I

e;+c n ye - l o
I

MOD-in
I

Figure 2. 2/3 cell functional blocks

The use of standard CMOS logic techniques difficult with the integration of digital functions sensitive RF signal processing blocks, due to the generation of large supply and substrate disturbances during transitions. Source logic Coupled Logic (SCL) has better EMC properties, operating with constant supply currents and differential voltage switching 131. Therefore, S C L is an obvious &didate for the implementationof logic functions meantto share the same substratewith sensitive receiver parts. The prescaler and end-of-cycle blocks have been implemented with the SCL circuit presented in figure 3. The logic tree combines an AND gate with a latch function 0 Minimum division ratio: 2 : "t n (ANDlatch). Each functional block requires two AND0 Maximum division ratio: 2"+l - 1 latchs, so each 2/3 cellcomprises 4 tail-currents.The nominal voltage swing set to SOOmVp, which is genwas Now the minimum and maximum division ratios can be erated by the tail current Id combined with the load resisindependently setby choice of nLin and n, respectively. tors Rd. CMOS technology enables direct coupling of the Q 3. Implementation of the Divider Cells output of a SCL gateto the ck input of another one, without the necessity of level shifters - the standard situaA 2/3 divider cell comprisestwo functional blocks,as tion of CML circuits implementedin bipolar technologies. depicted in figure 2. The prescaler logic block divides, The absence of level shiftersevidently decreases the comupon control by the end-ofcycle logic, the frequency of plexity of SCL gates and the power dissipation of logic the ckin input signal either 2 or by 3, and outputsthe by functions implemented with SCL logic. divided clock signal to the next cell chain.The endin the of-cycle logic controls the momentaneous division ratio 4. AC SimulationMethod for PowerDissiof the cell, depending on the state of its MODin and P inputs, and outputs the MOD-out signal to the preceding pation Optimizationof the Divider Cells 2/3 cell in the chain. The main objective of the programmable divider test 'In principle, it is also possible to divide by 3?, but the gap between chip was to achieve the highest power efficiency possithis value and the continuous division range makes it useless in standard synthesizer applications. ble, to be discussed further in Section using a standard 6,

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Wd

Figure 3. Circuit implementation of AND gate combined with latch function

Figure 5. Bandwidth of the prescaler cell for several values of tail current

cell's input frequency. CMOS process. As the operating frequency of each cell Transient simulations were done to check the relation is the input frequency of the previous one divided by 2, between the OdB frequencies found with the AC model the speed (gate-delay) requirement put on each 213 cell and the maximum toggling frequencies the prescalers. of is well known. Furthermore, the observation that logical The values were found to be in good agreement (within functions implemented with fully differential techniques 10%). behave in a fairly analog wayat high frequencies - frequencies comparable to the bandwidth ofthe digitalfunclions, when the logic inputs are in equilibrium -, enabled us to devise an method for optimization of gateAC delay/power dissipation trade-off. The implementation of the prescaler function is done with two ANDlatch functions (see figure 3). In a small signal analysis carried out with the ck input in balanced state, the latches may be seen as two differential ampliFigure 6. Circuit diagramof the input amplifier fiers in cascade. The gate-delays and maximum toggling frequency of the digital function will vary inversely to the open-loop bandwidth of this equivalent "analog system", 5. InputAmplifierDesign and consequently circuits having larger bandwidths will operate at higher frequencies. A flexible frequency divider design relies on the presfeedback loop cut here

Vin

Figure 4. Optimization of bandwidth vs. power dissipation withthe AC open loop technique

The simulation technique illustrated in figure 4. Vin is is is the small signal input source, hence VoutNin the AC small signal transfer of the cascade of two ANDlatchs. The 'load block' is used to generate the nominal loading conditions to AL2, compensating e.g. for the open loop's smaller loading of AL2's Q output. The result is given in figure 5, showing the bandwidth and small-signal gain L Vout/Vin for several values of tail currents in A l and AL2. Note that we are optimizing the output circuitryof the prescaler cell. So, due to the nature of division by 2, we have tomultiply.the resultsby two to refer them to the

ence of an input amplifier, to interface the VCO to the first digital cell. Figure 6 presents the chosen circuit topology. The required amplification set sensitivity requirements by has been split into differential stages.The circuit may two beeithersingle-endedordifferentiallydriven.Inboth cases the output of the amplifier delivers a differential signal to the divider with the correct DC level. The negative feedback implemented with the Rfb resistances provides DC biasing of the first stage, allowing coupling of the AC VCO signal to the first differential pair. Furthermore, the negative feedback eliminates the risk that offset voltages amplified in the differential stages will cause imbalance in the differential output voltage, thus decreasing the input sensitivity the device at high frequencies, where the of amplifier's AC gain is much smaller than its DC gain.

6. Implementation Measurements and of the 18bit Fully Programmable Divider in 0.35p.m CMOS
The divider test chip was implemented in a standard 0.35pmCMOS process. It contains a total 18 2/3cells, of with division ratio ranging from 512 to 524287.The lay-

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freq (GHz)

Figure 7. Measured sensitivity curves of the divider, for a few divider and amplifier current settings

out of the high frequency cells was optimized by hand, and simulation including all extracted parasitics revealed a reduction of about 30% in speed. The input amplifier 0.7 I O* current (lamp) the divider cells current(lamp) be and can independently setby external current sources, for evaluation purposes. Figure 7 presents measured sensitivity curves the diof vider test chip, for different current settings in the divider and input amplifier. The flat portion of the curves show [71 2 0.2 that the circuit is highly sensitive over a large frequency range (> lGHz), and hence very flexible w.r.t. application. 0 Furthermore, one can readily trade-off the input amplifier 0 0.1 1 1.6 1.2 1.4 2 2.2 2.4 2.6 power dissipation vs. the sensitivity on the flat portion of frequency (GHz) the curve, and the divider high frequency performance vs. its power dissipation. This flexibility increases the added- Figure 8. Comparison of power efficiency (GHz/mW) value of the building block for low-power applications. and discussed measurement results. Figure 8 presents the power efficiency (GHdmW) of this 18bit fully programmable divider, in comparison to recent publicationson low power dividers and tuning sys- 8. Acknowledgements tems. Three frequency points are plotted, corresponding The authors wish to thank J. de Haas, M. Locher, G. to the circles in figure 7. The power efficiency is calcuvan Veenendaal and U. Vaegeli for their contributions to lated with the respective currents for each curve, and a this work. supply voltage of 2V. [2] and [3] are bulk CMOS implementations of prescalers. [7] proposes a new synthesizer References architecture (implementedin bulk CMOS), where the divider is powered-down after lock has been achieved. [5] [ I ] S . Wu and B. Razavi, A 900MHU1.8GHz CMOS Receiver for is a bipolar implementation of a dual-modulus prescaler, Dual-Band Applications, IEEE ISSC, December 1998. and [6] isaprogrammabledividerimplemented inan [2] J. Craninckx and M. Steyaert, A Fully Integrated CMOS DCSultrathin-film CMOS/SIMOX process. achieved a sigWe 1800 Frequency Synthesizer, lEEE JSSC, December 1998. nificant power efficiency improvement w.r.t bulk CMOS, [3] F. piazza and Q.Huang, A Low Power CMOS Dual Modulus equaled the CMOS/SIMOX performance and approached Frescaler for Frequency Synthesizers, IEICE Transactionson the bipolar implementation (please observe that we are Electronics, February 1997. comparingafullyprogrammabledividerwithadual[4] C. Vaucher and D. Kasperkovitz, A Wide-Band Tuning System modulus prescaler).
O3I
1.1

0.9

fof Fully Integrated Satellite receivers, IEEEJSSC, July 1998.

7. Conclusions
We presented a modular and scalable divider architecture. The implementationof the divider cellsin SCL was described. A new design method for optimizing the power dissipation of the divider cells was introduced, which is basedonan AC simulationtechnique.Finally, we described .the circuit implementation of the input amplifier

[5] T. Seneff et al., A Sub-lmA I.5GHz Silicon Bipolar Dual Modulus Prescaler, IEEEJSSC, October 1994. [6] Y. Kado et al., An Ultralow CMOSlSIMOX Power grammable Counter LSI, IEEEJSSC, October 1997.

Pro-

[7] A.R. Shahani et al., Low-Power Dividerless FrequencySynthesis Using Aperture Phase Detection, IEEEJSSC, December 1998.