Expt. No.

1: Date :

STUDY OF LOGIC GATES

AIM: To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR gates. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate NAND gate NOR gate EX-OR gate Connecting wires IC 7408 IC 7432 IC 7404 IC 7400 IC 7402 IC 7486 As required Specification Quantity 1 1 1 1 1 1 1

THEORY: a. AND gate: An AND gate is the physical realization of logical multiplication operation. It is an electronic circuit which generates an output signal of 1 only if all the input signals are 1. b. OR gate: An OR gate is the physical realization of the logical addition operation. It is an electronic circuit which generates an output signal of 1 if any of the input signal is 1. c. NOT gate: A NOT gate is the physical realization of the complementation operation. It is an electronic circuit which generates an output signal which is the reverse of the input signal. A NOT gate is also known as an inverter because it inverts the input.

AND GATE
1

LOGIC DIAGRAM:

TRUTH TABLE: S.No 1. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A.B 0 0 0 1

PIN DIAGRAM OF IC 7408:

2. 3. 4.

OR GATE LOGIC DIAGRAM: TRUTH TABLE: INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A+B 0 1 1 1

S.No 1. 2. 3. 4.

PIN DIAGRAM OF IC 7432:

d. NAND gate:
2

A NAND gate is a complemented AND gate. The output of the NAND gate will be 0 if all the input signals are 1 and will be 1 if any one of the input signal is 0. e. NOR gate: A NOR gate is a complemented OR gate. The output of the OR gate will be 1 if all the inputs are 0 and will be 0 if any one of the input signal is 1. f. EX-OR gate: An Ex-OR gate performs the following Boolean function, A B = ( A . B ) + ( A . B )

It is similar to OR gate but excludes the combination of both A and B being equal to one. The exclusive OR is a function that give an output signal 0 when the two input signals are equal either 0 or 1.

PROCEDURE: 1. Connections are given as per the circuit diagram

2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.

3. Apply the inputs and verify the truth table for all gates.

NOT GATE
3

LOGIC DIAGRAM:

TRUTH TABLE: S.No 1. INPUT A 0 1 OUTPUT Y = A 1 0

PIN DIAGRAM OF IC 7404:

2.

NAND GATE: LOGIC DIAGRAM: TRUTH TABLE: S.No 1. PIN DIAGRAM OF IC 7400: 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y = (A. B) 1 1 1 0

NOR GATE LOGIC DIAGRAM: TRUTH TABLE:

S.No 1. 2. 3. 4.

INPUT A 0 0 1 1 B 0 1 0 1

OUTPUT Y = (A + B) 1 0 0 0

PIN DIAGRAM OF IC 7402:

EX-OR GATE LOGIC DIAGRAM: TRUTH TABLE: S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT Y=A 0 1 1 0 B

PIN DIAGRAM OF IC 7486:

RESULT: Thus the truth table of all the basic digital ICs was verified. HALF ADDER CIRCUIT DIAGRAM: TRUTH TABLE:

S.No 1. 2. 3. 4.

INPUT A 0 0 1 1 B 0 1 0 1

OUTPUT S 0 1 1 0 C 0 0 0 1

K Map for SUM:

K Map for CARRY:

FULL ADDER: CIRCUIT DIAGRAM:

Expt. No.2: Date :

DESIGN OF ADDER AND SUBTRACTOR

AIM: To design and verify the truth table of the Half Adder, half subtractor, Full Adder & full subtractor, circuits. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. Name of the Apparatus Digital IC trainer kit AND gate OR gate NOT gate EX-OR gate Connecting wires IC 7408 IC 7432 IC 7404 IC 7486 Range Quantity 1 1 1 1 1 As required

THEORY: The most basic arithmetic operation is the addition of two binary digits. There are four possible elementary operations, namely, 0+0=0 0+1=1 1+0=1 1 + 1 = 102 The first three operations produce a sum of whose length is one digit, but when the last operation is performed the sum is two digits. The higher significant bit of this result is called a carry and lower significant bit is called the sum. HALF ADDER: A combinational circuit which performs the addition of two bits is called half adder. The input variables designate the augends and the addend bit, whereas the output variables produce the sum and carry bits. TRUTH TABLE: K Map for SUM:

INPUT S.N o A B C 1. 2. 3. 4. 5. 6. 7. 8. 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1

OUTPUT SUM 0 1 1 0 1 0 0 1 CARRY 0 0 0 1 0 1 1 1 SUM = ABC + ABC + ABC + ABC = A K Map for CARRY: B C

CARRY = AB + AC + BC

HALF SUBTRACTOR CIRCUIT DIAGRAM: TRUTH TABLE: S.No 1. 2. 3. 4. INPUT A 0 0 1 1 B 0 1 0 1 OUTPUT DIFF BORR 0 1 1 0 0 1 0 0

FULL ADDER:
10

A combinational circuit which performs the arithmetic sum of three input bits is called full adder. The three input bits include two significant bits and a previous carry bit. A full adder circuit can be implemented with two half adders and one OR gate. HALF SUBTRACTOR: A combinational circuit which performs the subtraction of two bits is called half subtractor. The input variables designate the minuend and the subtrahend bit, whereas the output variables produce the difference and borrow bits. FULL SUBTRACTOR: A combinational circuit which performs the subtraction of three input bits is called full subtractor. The three input bits include two significant bits and a previous borrow bit. A full subtractor circuit can be implemented with two half subtractors and one OR gate.

PROCEDURE:

1. Connections are given as per the circuit diagrams.

2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.

3. Apply the inputs and verify the truth table for the half subtractor and full subtractor circuits.

FULL SUBTRACTOR:
11

CIRCUIT DIAGRAM:

TRUTH TABLE: S. No 1. 2. 3. 4. 5. 6. 7. 8. INPUT OUTPUT

K Map for DIFFERENCE

A B C DIFF BORR 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 0 1 1 1 0 0 0 1 DIFF = ABC + ABC + ABC + ABC = A K Map for BORROW B C

BORR = AB + AC + BC

12

RESULT:

The design of the half subtractor and full subtractor circuits was done and their truth tables were verified.

LOGIC DIAGRAM OF INVERTING AMPLIFIER:

13

PIN DIAGRAM:

TABULATION OF INVERTING AMPLIFIER: Theoretical Gain Rf Vin Vo Rf Ri Gain = Vo Vin

Expt. No. :3

INVERTING AND NONINVERTING AMPLIFIER

14

Date AIM:

1. To design an amplifier with a gain of -10 and input resistance equal to 100K.

2. To design an amplifier with a gain of +5 using an op-amp. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. Name of the Apparatus Function Generator IC Trainer Kit CRO Dual RPS Op-Amp Bread Board Resistors Connecting wires and probes Range 3 MHz 30 MHz 0 30 V IC 741 10K,100K, 40K As required Quantity 1 1 1 1 1 1 1

INVERTING AMPLIFIER: An inverting amplifier uses negative feedback to invert (i.e., negate) and amplify a voltage. In particular, the RinRf resistor network acts as an electronic seesaw (i.e., a class-1 lever) where the inverting (i.e., ) input of the operational amplifier is like a fulcrum about which the seesaw pivots. That is, because the operational amplifier is in a negative-feedback configuration, its internal high gain effectively fixes the inverting (i.e., ) input at the same 0 V (ground) voltage of the noninverting (i.e., +) input, which is similar to the stiff mechanical support provided by the fulcrum of the seesaw. Continuing the analogy,

15

Just as the movement of one end of the seesaw is opposite the movement of the other end of the seesaw, positive movement away from 0 V at the input of the RinRf network is matched by negative movement away from 0 V at the output of the network; thus, the amplifier is said to be inverting. WAVEFORM OF INVERTING AMPLIFIER:

LOGIC DIAGRAM OF NON INVERTING AMPLIFIER:

TABULATION OF NON INVERTING AMPLIFIER: Theoretical Gain Rf Vin Vo 1+ Rf Ri

16

Gain =

Vo Vin

In the seesaw analogy, the mechanical moment or torque from the force on one side of the fulcrum is balanced exactly by the force on the other side of the fulcrum; consequently, asymmetric lengths in the seesaw allow for small forces on one side of the seesaw to generate large forces on the other side of the seesaw. In the inverting amplifier, electrical current, like torque, is conserved across the RinRf network and relative differences between the Rin and Rf resistors allow small voltages on one side of the network to generate large voltages (with opposite sign) on the other side of the network. Thus, the device amplifies (and inverts) the input voltage. However, in this analogy, it is the reciprocals of the resistances (i.e., the conductances or admittances) that play the role of lengths in the seesaw. Hence, the amplifier output is related to the input as in

. So the voltage gain of the amplifier is A = Rf / Rin where the negative sign is a convention indicating that the output is negated. For example, if Rf is 10 k and Rin is 1 k, then the gain is 10 k/1 k, or 10 (or 10 V/V).[2] Moreover, the input impedance of the device is Rin because the operational amplifier's inverting (i.e., ) input is a virtual ground. NON INVERTING AMPLIFIER: Amplifies a voltage (multiplies by a constant greater than 1)

Input impedance The input impedance is at least the impedance between non-inverting ( + ) and inverting () inputs, which is typically 1 M to 10 T, plus the impedance of the path from the inverting ( ) input to ground (i.e., R1 in parallel with R2). Because negative feedback ensures that the non-inverting and inverting inputs match, the input impedance is actually much higher. Although this circuit has a large input impedance, it suffers from error of input bias current. The non-inverting ( + ) and inverting ( ) inputs draw small leakage currents into the operational amplifier. These input currents generate voltages that act like unmodeled input offsets. These unmodeled effects can lead to noise on the output (e.g., offsets or drift).

17

Assuming that the two leaking currents are matched, their effect can be mitigated by ensuring the DC impedance looking out of each input is the same. The voltage produced by each bias current is equal to the product of the bias current with the equivalent DC impedance looking out of each input. Making those impedances equal

WAVEFORM OF NON INVERTING AMPLIFIER:

18

makes the offset voltage at each input equal, and so the non-zero bias currents will have no impact on the difference between the two inputs.

A resistor of value

which is the equivalent resistance of R1 in parallel with R2, between the Vin source and the non-inverting ( + ) input will ensure the impedances looking out of each input will be matched. The matched bias currents will then generate matched offset voltages, and their effect will be hidden to the operational amplifier (which acts on the difference between its inputs) so long as the CMRR is good. Very often, the input currents are not matched. Most operational amplifiers provide some method of balancing the two input currents (e.g., by way of an external potentiometer). Alternatively, an external offset can be added to the operational amplifier input to nullify the effect. Another solution is to insert a variable resistor between the Vin source and the non-inverting ( + ) input. The resistance can be tuned until the offset voltages at each input are matched.

PROCEDURE: INVERTING AMPLIFIER: 1. 2. 3. 4. 5. Make the connections as per the circuit diagram. Apply the input signal of desired amplitude to the inverting input terminal. Measure the output signal at the output terminal of the Op-Amp. Note the change in phase between the input and the output signal. Calculate the gain and plot the waveform.

NON INVERTING AMPLIFIER: 1. 2. 3. 4. 5. Make the connections as per the circuit diagram. Apply the input signal of desired amplitude to the Non inverting input terminal. Measure the output signal at the output terminal of the Op-Amp. Note the change in phase between the input and the output signal. Calculate the gain and plot the waveform.

RESULT:
19

Thus the Inverting and Non Inverting Amplifier were designed and gain values were calculated. LOGIC DIAGRAM OF BINARY TO GRAY CODE

K Map for G3

K Map for G2

Equation for G3= B3

Equation for G2= B3 B2 + B3 B2= B3 XOR B2

K Map for G1

K Map for G0

20

Expt. No. :4 Date AIM: :

DESIGN AND IMPLEMENTATION OF CODE CONVERTERS

To design and verify the truth table of a four bit

a) Binary to gray code converter. b) Gray to binary code converter

c) BCD to Excess-3 code converter

d) Excess-3 to BCD code converter.

APPARATUS REQUIRED: S.No 1 . 2 . 3 . 4 . 5 Name of the Apparatus Digital IC trainer kit 1 EX-OR gate IC 7486 1 Range Quantity

AND gate

IC7408

OR gate

IC 7432

NOT gate

IC 7404

1
21

6 .

Connecting wires

As required

THEORY: Code converter is a circuit that makes two systems compatible even though each uses different binary codes. There is a wide variety of binary codes used in digital systems. Some of these codes are Binary Coded Decimal, Gray code, Excess- 3 code , ASCII code, etc. A combinational circuit performs the transformation of a three bit binary to gray code converter by means of logic gates. The input variables are binary bits named as A,B,C with A as the MSB and C as the LSB. The Gray code output bits are termed as X,Y,Zwith X as the MSB and Z as the LSB. The Gray code is also called as reflective code. The gray coded number corresponding to the decimal number 2n 1, for any n, differs from gray coded 0 (0000) in one bit position only. TRUTH TABLE FOR BINARY TO GRAY CONVERSION: Binary Input Gray Input B3 0 0 0 0 0 0 0 0 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 B1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 G3 0 0 0 0 0 0 0 0 1 1 1 1 G2 0 0 0 0 1 1 1 1 1 1 1 1 G1 0 0 1 1 1 1 0 0 0 0 1 1 G0 0 1 1 0 0 1 1 0 0 1 1 0
22

1 1 1 1

1 1 1 1

0 0 1 1

0 1 0 1

1 1 1 1

0 0 0 0

1 1 0 0

0 1 1 0

GRAY TO BINARY CODE CONVERTER:

BINARY TO GRAY The MSB of the binary code alone remains unchanged in the Gray code. The remaining bits in the gray are obtained by EX-OR ing the corresponding gray code bit and previous bit in the binary code. The gray code is often used in digital systems because it has the advantage that only one bit in the numerical representation changes between successive numbers. GRAY TO BINARY The MSB of the Gray code remains unchanged in the binary code the remaining bits are obtained by EX OR ing the corresponding gray code bit and the previous output binary bit. PROCEDURE: 1. Connections are made as per the circuit diagram. 2. Logical inputs were given as per the truth table. 3. Observe the logical output and verify the truth table.

23

TRUTH TABLE FOR GRAY TO BINARY CONVERSION: Gray Input G3 0 0 0 0 0 0 0 0 1 1 G2 0 0 0 0 1 1 1 1 0 0 G1 0 0 1 1 0 0 1 1 0 0 G0 0 1 0 1 0 1 0 1 0 1 B3 0 0 0 0 0 0 0 0 1 1 Binary Output B2 0 0 0 0 1 1 1 1 1 1 B1 0 0 1 1 1 1 0 0 1 1 B0 0 1 1 0 1 0 0 1 1 0
24

1 1 1 1 1 1

0 0 1 1 1 1

1 1 0 0 1 1

0 1 0 1 0 1

1 1 1 1 1 1

1 1 0 0 0 0

0 0 0 0 1 1

0 1 0 1 1 0

BCD TO EXCESS 3 CONVERTERS:

25

TRUTH TABLE: BCD Input B3 0 0 0 0 0 0 0 0 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 B1 0 0 1 1 0 0 1 1 0 0 1 B0 0 1 0 1 0 1 0 1 0 1 0 EXCESS-3 Output E3 0 0 0 0 0 1 1 1 1 1 1 E2 0 1 1 1 1 0 0 0 0 1 1 E1 1 0 0 1 1 0 0 1 1 0 0 E0 1 0 1 0 1 0 1 0 1 0 1

26

1 1 1 1 1

0 1 1 1 1

1 0 0 1 1

1 0 1 0 1

1 1 0 0 0

1 1 0 0 0

1 1 0 0 1

0 1 0 1 0

EXCESS-3 TO BCD CONVERTER:

27

TRUTH TABLE:
28

EXCESS 3 Input X1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A x x x 0 0 0 0 0 0 0 0 1 1 x x x

BCD Output B x x x 0 0 0 0 1 1 1 1 0 0 x x x C x x x 0 0 1 1 0 0 1 1 0 0 x x x D x x x 0 1 0 1 0 1 0 1 0 1 x x x

29

RESULT: Thus the 4-bit binary to gray converter, gray to binary converter, BCD to Excess-3 code converter and Excess 3 to BCD converter were designed and implemented.

LOGIC DIAGRAM FOR ENCODER:

30

TRUTH TABLE OF ENCODER: INPUTS Y1 1 0 0 0 0 0 0 Expt. No. :5 Date :

31

OUTPUTS Y5 0 0 0 0 1 0 0 Y5 0 0 0 0 0 1 0 Y7 0 0 0 0 0 0 1 A 0 0 0 1 1 1 1 B 0 1 1 0 0 1 1 C 1 0 1 0 1 0 1

Y2 0 1 0 0 0 0 0

Y3 0 0 1 0 0 0 0

Y4 0 0 0 1 0 0 0

DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

AIM: To design and Implement encoder and decoder using gates and study of IC 7445 and IC 74147. APPARATUS REQUIRED: SI .NO 1 2 3 4 5 Components 3 I/P NAND gate OR gate NOT gate Patch cards IC Trainer Kit Specification IC 7410 IC7432 IC 7404 Quantity 2 3 1 Few 1

THEORY : ENCODER : An encoder is a digital circuit that perform inverse operation of a decoder .An encoder has 2n I/P lines and n O/P lines . In encoder the O/P lines generates the binary code corresponding to the input value . in octal to binary encoder it has eight I/P s one for each octal digit and 3 O/P that generate the corresponding binary code .In encoder it is assumed that only one I/P has a value of one at any given time otherwise the circuit is meaningless. It has an ambiguity that when all inputs are zero the outputs are zero. The zero outputs can also be generated when D0 = 1. DECODER: A decoder is a multiple input and multiple output logic circuits which converts input and output codes are different .The input code generally has few ever bits than the output code .Each input code word produces a different output code word (i.e. )there is one to one mapping can be expressed in truth table .In the block diagram of decoder circuit the encoded information is present as n input producing 2n possible outputs. 2n output values are from 0 through out 2n-1 .

LOGIC DIAGRAM FOR DECODER

32

TRUTH TABLE OF DECODER: INPUT E 1 0 0 0 0 A 0 0 0 1 1 B 0 0 1 0 1 D0 1 0 1 1 1 D1 1 1 0 1 1 OUTPUT D2 1 1 1 0 1 D3 1 1 1 1 0

33

PROCEDURE: Connections are made as per circuit diagram. Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.

RESULT: Thus the encoder decoder using logic gates were designed and implemented and IC 7445 and IC 74147were studied.
34

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

LOGIC DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE: S1 0 0 1 1 S2 0 1 0 1 Y=Output D0 D1 D2 D3

35

Expt. No. :6

DESIGN AND IMPLEMENT OF MULTIPLEXER & DEMULTIPLEXER

Date AIM:

To design and implement multiplexer & demultiplexer using logic gates and study of IC 74150 and IC 74154. APPARATUS REQUIRED: SI.NO 1 2 3 4 5 THEORY: MULTIPLEXER: Multiplexer means transmitting a large number of information units over a smaller number of channels or lines . A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line .The selection of a particular input line is controlled by a set of selection lines. Normally there are n selection lines whose bit combination determines which input is selected. DEMULTIPLEXER: The function of demultiplexer is in contrast to multiplexer function. It takes information from one line and distributes it to a given number of O/P lines. For this reason, the demultiplexer is also as a data distributor. Decoder can also be used as a demultiplexer. In the 1:4 demultiplexer ckt, the data I/P line goes to all of the AND gates. The data select the lines enable only one gate at a time the data on the data I/P line will pass through the selected gate to the associated data O/P line. BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:
36

Components 3 I/P AND gate OR gate NOT gate IC Trainer kit Connecting wires

Specifications IC 7411 IC7432 IC 7404 -

QTY 2 1 1 1 Few

LOGIC DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE: S1 0 0 1 1 S2 0 1 0 1 Y=Output D0 D1 D2 D3

FUNCTION TABLE OF MULTIPLUXER:

37

S1

S2

INPUTS Y

D0 D0 S1' S0'

D1 D1 S1' S0

D2 D2 S1 S0'

D3 D3 S1 S0

Y= D0 S1' S0' + D1 S1' S0+ D2 S1 S0'+ D3 S1 S0 FUNCTION TABLE OF DEMULTIPLUXER:

S1

S2

INPUTS Y xD0 = S1' S0'

xD1 = S1' S0

xD2 = S1 S0'

1 PIN DIAGRAM OF IC74150:

xD3 = S1 S0

38

PIN DIAGRAM OF IC 74154:

PROCEDURE:
39

 Connections are made as per the circuit diagram. Logical I/Ps are given as per the circuit diagram. Observe the O/P and verify the truth table.

RESULT: Thus the multiplexer and demultiplexer were designed and implemented using logic gates IC 74150 and IC 74154.

40

LOGIC DIAGRAM OF TWO BIT COMPARATOR:

LOGIC DIAGRAM OF 8 BIT COMPARATOR:

41

Expt. No. :7

DESIGN AND IMPLEMENTATON OF MAGNITUDE COMPARATOR

Date AIM:

To design and implement i. ii. 2-bit magnitude comparator using basic Gates. 8-bit magnitude comparator using IC 7485.

APPARATUS REQUIRED: S.NO 1. 2. 3. 4. 5. 6. 7. Components AND gate X-OR gate OR gate NOT gate Specification IC 7408 IC 7486 IC 7432 IC 7404 Quantity 2 1 1 1 2 1 few

4-bit magnitude IC 7485 Comparator IC Trainer kit Patch cards -

THEORY: The comparison of 2 numbers are an operator that determine one number is greater than or less than or equal to the other number. A magnitude comparator is a combinational circuit that compares 2 numbers A and B and determine their relative magnitude. The outcome of the comparator is specified by 3 binary variables that indicate ,A=B,A>B, A<B, A=A3A2A1A0 B=B3B2B1B0 The equality of the two numbers and B is displayed in a combinational circuit designed by the symbol (A=B). This indicates A greater than B, then inspect of the relative magnitude of pairs of significant position A is 0 and that of B is 0. We have A<B , the sequential comparison can be expanded as

42

TRUTH TABLE: Inputs A1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A0 B1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A>B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 Outputs A<B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 A=B 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0

A > B = A3 B3 + X 3 A2 B 2 + X 3 X 2 A1 B1 + X 3 X 2 X 1 A0 B0 A < B = A3 B3 + X 3 A2 B 2 + X 3 X 2 A1 B1 + X 3 X 2 X 1 A0 B0
43

The same circuit can be used to compare the relative magnitude of 2 BCD digits. Where A=B is expanded as (A=B)=(A3+B3) (A2+B2) (A1+B1) (A0+B0) PROCEDURE: 1. Connections are made as per the circuit diagram 2. Logical inputs are given as per the circuit diagram. 3. Observe the outputs and verify the truth table.

PIN DIAGRAM OF IC 7485:

44

TRUTH TABLE OF 8 BIT MAGNITUDE COMPARATOR: A 0000 0000 0001 0001 0000 0000 B 0000 0000 0000 0000 0001 0001 A>B 0 1 0 A=B 1 0 0 A<B 0 0 1

45

RESULT: Thus the design and implementation of magnitude comparator were done and verified.

LOGIC DIAGRAM OF 4 BIT ODD/EVEN PARITY CHECKER:

46

TRUTH TABLE: 4 Bit Message X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Expt. No. :8 Date :

47

Y 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

Z 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

P 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Parity Checker 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0

PARITY CHECKER AND GENERATOR

AIM: To design and implement ODD/EVEN parity checker and generator using logic gates. APPARATUS REQUIRED: S.No 1. 2. 3. 4. Name of the Apparatus Digital IC trainer kit NOT gate NOT gate Connecting wires IC 7404 IC 74180 Range Quantity 1 1 2 few

THEORY: A parity bit is used for the purpose of detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number of 1s either odd or even. The message including the parity bit is transmitted and then checked at the receiving end for errors. An error is detected if the checked parity does not correspond with the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker. In even parity the added parity bit will make the total number of 1s an even amount and in odd parity the added parity bit will make the total number of 1s an odd amount. In a three bit odd parity generator the three bits in the message together with the parity bit are transmitted to their destination, where they are applied to the parity checker circuit. The parity checker circuit checks for possible errors in the transmission. Since the information was transmitted with odd parity the four bits received must have an odd number of 1s. An error occurs during the transmission if the four bits received have an even number of 1s, indicating that one bit has changed during transmission. The output of the parity checker is denoted by PEC (parity error check) and it will be equal to 1 if an error occurs, i.e., if the four bits received has an even number of 1s.

LOGIC DIAGRAM OF 3 BIT EVEN PARITY GENERATOR:

48

TRUTH TABLE: 3 Bit message X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 Parity Generator 0 1 1 0 1 0 0 1

PROCEDURE: 1. Connections are given as per the circuit diagram.

49

2. Logical inputs are given as per the circuit diagram. 3. Observe the output and verify the truth table.

RESULT: Thus the Parity checker and Generator were designed and implemented and truth tables were verified. PIN DIAGRAM:

50

CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR:

WAVEFORM:

51

Expt. No. :9 Date AIM: :

ASTABLE AND MONOSTABLE MULTIVIBRATOR

To construct and study the operation of Astable and Monostable multivibrator using 555 timer.

APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. 7. 8. Component IC Resistor Capacitor CRO AFO Power Supply Bread Board Connecting Wires Specification 555 6.8K, 3.3 K, 10K 0.1F, 0.01F Quantity 1 Each Each 1 1 1 1 Few

THEORY: An astable multivibrator, often called a free-running multivibrator, is a rectangular-wave-generating circuit. This circuit do not require an external trigger to change the state of the output. The time during which the output is either high or low is determined by two resistors and a capacitor, which are connected externally to the 555 timer. The time during which the capacitor charges from 1/3 Vcc to 2/3 Vcc is equal to the time the output is high and is given by,
52

tc = 0.69 (R1 + R2) C Similarly the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is equal to the time the output is low and is given by td = 0.69 (R2) C. Thus the total time period of the output waveform is, T = tc + td = 0.69 (R1 + 2 R2) C. The term duty cycle is often used in conjunction with the astable multivibrator. The duty cycle is the ratio of the time tc during which the output is high to the total time period T. It is generally expressed in percentage. In equation form, % duty cycle = [(R1 + R2) / (R1 + 2 R2)] x 100 TABULATION: Time TON TOFF

Output Voltage

Capacitor Voltage

Charging

Discharging

CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:

53

PROCEDURE ASTABLE MULTIVIBRATOR: 1. Connections are made as per the circuit diagram. 2. Switch on the power supply. 3. The output waveform is noted in CRO.
4. TON and TOFF is calculated from the waveform.

5. Frequency is calculated by f=1/T.

54

MONOSTABLE MULTIVIBRATOR: 1. Connections are made as per the circuit diagram.

2. Trigger pulse input is given by means of AFO.

3. The output waveform is noted in CRO.

4. TON and TOFF is calculated from the waveform.

5. Frequency is calculated by f=1/T.

WAVEFORM:

55

TABULATION:

Input Voltage

Output Voltage

Capacitor Voltage

TON

TOFF

TON

TOFF

Charging

Discharging

56

RESULT: Thus the Astable and waveforms were plotted. CIRCUIT DIAGRAM OF INTEGRATOR:
57

Monostable multivibrator with IC 555 was constructed and the output

TABULATION: Input Voltage(V) Time (ON) ms Voltage (V) Output Time (OFF) ms

WAVEFORM OF INTEGRATOR:

Expt. No. :10

INTEGRATOR AND DIFFERENTIATOR

58

Date AIM:

i. ii.

To construct an integrator using an op-amp and study its operation. To construct an differentiator using an op-amp and study its operation.

APPARATUS REQUIRED: S.No 1 . 2 . 3 . 4 . 5 . 6 . 7 . Apparatus IC Specification 741 Quantity 1

Resistors

1K, 1.59K,10K,1.59K 0.1F, 0.01F, 10F

Capacitor

Fixed Power Supply

AFO,CRO

Bread Board

Connecting Wires

few

THEORY: INTEGRATOR: A circuit in which the output voltage waveform is the integral of the input voltage waveform is the integrator. Such a circuit is obtained by using a basic inverting amplifier configuration if the feedback resistor Rf is replaced by a capacitor Cf . The expression for the output voltage is given as,
59

Vo = - (1/Rf C1) Vi dt Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal. Normally between fa and fb the circuit acts as an integrator. Generally, the value of fa < fb . The input signal will be integrated properly if the Time period T of the signal is larger than or equal to Rf Cf. That is, T Rf Cf The integrator is most commonly used in analog computers and ADC and signal-wave shaping circuits. CIRCUIT DIAGRAM OF DIFFERENTIATOR:

TABULATION: Input Voltage(V) Time (ON) ms Voltage (V) Output Time (OFF) ms

WAVEFORM:

60

DIFFERENTIATOR: The differentiator circuit performs the mathematical operation of differentiation; that is, the output waveform is the derivative of the input waveform. The differentiator may be constructed from a basic inverting amplifier if an input resistor R1 is replaced by a capacitor C1. The expression for the output voltage is given as, Vo = - Rf C1 (dVi /dt) Here the negative sign indicates that the output voltage is 180 0 out of phase with the input signal. A resistor Rcomp = Rf is normally connected to the non-inverting input terminal of the op-amp to compensate for the input bias current. A workable differentiator can be designed by implementing the following steps: Then, assuming a value of C1 < 1 F, calculate the value of Rf. 2. Choose fb = 20 fa and calculate the values of R1 and Cf so that R1C1 = Rf Cf. The differentiator is most commonly used in waveshaping circuits to detect high frequency components in an input signal and also as a rateofchange detector in FM modulators. Procedure for Integrator:
1. Connections are made as per the circuit diagram. 1. Select fa equal to the highest frequency of the input signal to be differentiated.

2. A Square wave input of required amplitude and frequency is applied as input using an AFO. 3. The output triangular wave is measured using CRO. 4. The input and output waveforms are plotted. Procedure for Differentiator:
1. Connections are made as per the circuit diagram. 61

2. A Square wave input of required amplitude and frequency is applied as input using an AFO. 3. The output spike signal is measured using the CRO. 4. The input and output waveforms are plotted.

RESULT: Thus the Integrator and differentiator circuit was designed and its input and output waveforms were drawn. RS FLIP FLOP

LOGIC SYMBOL:

CIRCUIT DIAGRAM:

TRUTH TABLE: Clock 0 1 1 S X 0 0 R X 0 1 Q NC NC 0 NC NC 1

62

1 1

1 1

0 1

1 invalid

0 invalid

Expt. No. :11 Date AIM: :

STUDY OF FLIP FLOPS

To study and verify the following Flip Flops using truth table. APPARATUS REQUIRED: S.No Components 1 NAND Gate . 2 NOR Gate . 3 AND Gate . 4 IC Trainer Kit . 1 IC 7411 1 IC 7402 1 Range IC7400 Quantity 1

63

5 Connecting wires . THEORY:

few

A Flip Flop is a sequential device that samples its input signals and changes its output states only at times determined by clocking signal. Flip Flops may vary in the number of inputs they possess and the manner in which the inputs affect the binary states. RS FLIP FLOP: The clocked RS flip flop consists of NAND gates and the output changes its state with respect to the input on application of clock pulse. When the clock pulse is high the S and R inputs reach the second level NAND gates in their complementary form. The Flip Flop is reset when the R input high and S input is low. The Flip Flop is set when the S input is high and R input is low. When both the inputs are high the output is in an indeterminate state. D FLIP FLOP: To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the same time. This is obtained by making the two inputs complement of each other. D FLIP FLOP: LOGIC SYMBOL: CIRCUIT DIAGRAM:

64

TRUTH TABLE: Clock 1 1 D 0 1 Q 0 1 1 0

JK FLIP FLOP

LOGIC SYMBOL:

CIRCUIT DIAGRAM:

65

JK FLIP FLOP: The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs behave like S and R inputs to set and reset the Flip Flop. The output Q is ANDed with K input and the clock pulse, similarly the output Q is ANDed with J input and the Clock pulse. When the clock pulse is zero both the AND gates are disabled and the Q and Q output retain their previous values. When the clock pulse is high, the J and K inputs reach the NOR gates. When both the inputs are high the output toggles continuously. This is called Race around condition and this must be avoided. T FLIP FLOP: This is a modification of JK Flip Flop, obtained by connecting both inputs J and K inputs together. T Flip Flop is also called Toggle Flip Flop.

66

TRUTH TABLE OH JK FLIP FLOP: Clock 0 1 1 1 1 J X 0 0 1 1 K X 0 1 0 1 Q NC NC 0 1 toggle NC NC 1 0 toggle

T FLIP FLOP: LOGIC SYMBOL: CIRCUIT DIAGRAM:

67

TRUTH TABLE: Clock 1 1 T 0 1 Q Last Toggle Toggle Last Toggle Toggle

PROCEDURE: 1. Connections are made as per the circuit diagram. 2. Input gives and corresponding output are taken and they are verified with the truth table.

68

RESULT: Thus the different types of Flip Flops are constructed and their truth tables are verified.

PIN DIAGRAM OF IC 7476

CHARACTERISTIC TABLE: Q 0 0 1 1 TRUTH TABLE: Input Up/Down Counter 0 0 0 0 0 0 0 0 1 1 1 1 Present State QA 0 1 1 1 1 0 0 0 0 0 0 0 QB 0 1 0 1 0 1 0 1 0 1 0 1 QC 0 1 0 1 0 1 0 1 0 1 0 1 QA 1 1 1 1 0 0 0 0 0 0 0 1 Next State
+

Qn+1 0 1 0 1

J 0 1 X X

K X X 1 0 A
+

B KA X 0 0 0 1 X X 0 X X X 0 JB 1 x x 0 1 x x 0 0 0 1 x KB x 0 1 x x 0 1 x x x 0 1 JC 1 x 1 x 1 x 1 x 1 x 1 x

C KC x 1 x 1 x 1 x 1 x 1 x 1
69

QB 1 1 0 0 1 1 0 0 1 1 0 0

QC 1 0 1 0 1 0 1 0 1 0 1 0

JA 1 x x x x 0 0 0 0 0 0 x

1 1 1 1 Expt. No.12:

1 1 1 1

0 1 0 1

0 1 0 1

1 1 1 0

1 1 0 0

1 0 1 0

x x x x

0 0 0 1

0 1 x x

x x 0 1

1 x 1 x

x 1 x 1

DESIGN AND IMPLEMENT 3-BIT SYNCHRONOUS UP/DOWN COUNTER

Date AIM:

To design and implement 3-bit synchronous UP/DOWN counter. APPARATUS REQUIRED: S.No 1 . 2 . 3 . 4 . 5 . 6 . 7 . Connecting wires few IC trainer gate 1 NOT gate IC 7404 1 X-OR gate IC7486 1 OR Gate IC 7432 1 3 Input AND gate IC 7411 1 Component JK Flip flop Specification IC 7476 Quantity 2

70

THEORY: A Counter is a register capable of counting number of clock pulse arriving at its clock input. Counter represents the number of clock pulse arrived. An UP/DOWN counter is one that is capable of progressing in increasing order or decreasing order through a certain sequence. An UP/DOWN counter is also called bidirectional counter usually up/down operation of the counter is controlled by up/down signal. When this signal is high counter goes through UP sequence and this signal is low counter follows reverse sequence.

STATE DIAGRAM:

Synchronous UP/DOWN Counter

LOGIC DIAGRAM:
71

PROCEDURE: 1. Connections are made as per the circuit diagram. 2. Logical inputs are made as per the circuit diagram. 3. Observe the outputs and verify the truth table.

72

RESULT: Thus the 3 bit UP/DOWN synchronous counter was designed and implemented. 4-BIT BINARY ADDER: LOGIC DIAGRAM:

73

PIN DIAGRAM OF IC 7483:

Expt. No. :13 Date AIM: :

DESIGN OF 4-BIT ADDER AND SUBTRACTOR

74

To design and implement a 4-bit adder and subtractor using IC7483. APPARATUS REQUIRED: S.No 1. 2. 3. 4. 5. 6. IC EX-OR AND Gate OR Gate IC Trainer kit Patch cards Components Specifications IC 7483 IC 7486 IC 7408 IC 7432 Quantity 2 1 1 1 1 Few

THEORY: A binary adder is a digital circuit that produces the arithematic sum of 2 binary numbers. It can be constructed with full adders connected in cascade with the output carry from each full adder connected to the input carry of next full adder in chain. The augends bits of A and the addend bits of B are designed by subscript numbers from right to left, with subscript 0 denoting the least significant bit. The carriers are connected in chain through the full adder. The input carry to the adder is Co and it ripples through the full adder to the input carry C4.

4-BIT BINARY SUBTRACTOR:

The circuit for subtracting 4-bit consists of an adder with inverters , placed between each data inputs(B) and the corresponding input of full adder. The input carry C0 must be equal to 1 when performing subtraction.
75

LOGIC DIAGRAM OF 4-BIT BINARY ADDER/SUBTRACTOR:

76

4-BIT BINARY ADDER/ SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one common binary adder. The mode input m controls the operation. When m=0, the circuit is adder circuit. When m=1, it becomes subtractor.

4-BIT BCD ADDER:

Consider the arithmetic operation of two decimal digits in BCD, together with an input carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than 19, the 1 in the sum bring an input carry. The output of two decimal digits must be represented in BCD and should appear in the form listed in the columns. A BCD adder that adds 2 BCD digits and produce a sum digit in BCD. The two decimal digits together with the input carry are first added in the top 4-bit adder to produce the binary sum.

PROCEDURE: 1. Connections are made as per the circuit diagram.

77

2. Logical inputs given as per the truth table. 3. Observe the logical outputs and verity with the truth table.

TRUTH TABLE FOR 4 BIT BINARY ADDERS: B3 0 0 0 0 0 0 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 A3 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 S3 0 0 0 0 1 1 1 1 S2 0 0 1 1 0 0 1 1 S1 0 1 0 1 0 1 0 1 S0 0 0 0 0 0 0 0 0 COUT 0 0 0 0 0 0 0 0

78

1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

79

TRUTH TABLE 4 BIT BINARY ADDER/SUBTRACTOR: INPUT DATA A A4 1 1 0 0 1 1 1 A3 0 0 0 0 0 0 0 A2 0 0 1 0 1 1 1 A1 0 0 0 1 0 0 0 B4 0 1 1 0 1 1 1 INPUT DATA B B3 0 0 0 1 0 1 1 B2 1 0 0 1 1 1 0 B1 0 0 0 1 1 1 1 B 1 1 0 0 0 0 0 SUBTRACTION D4 0 0 1 1 1 1 1 D3 1 0 0 0 1 1 1 D2 1 0 1 1 1 1 0 D1 0 0 0 0 1 1 1
80

BCD ADDER LOGIC DIAGRAM:

81

TRUTH TABLE FOR BCD ADDER: BCD Sum S4 0 0 0 0 0 0 S3 0 0 0 0 1 1 S2 0 0 1 1 0 0 S1 0 1 0 1 0 1 Carry C 0 0 0 0 0 0

82

0 0 1 1 1 1 1 1 1 1

1 1 0 0 0 0 1 1 1 1

1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1

0 0 1 1 1 1 1 1 1 1

83

RESULT: Thus the 4-Bit adder and subtractor were designed and implemented using IC 7483. CIRCUIT SHOWING APPLICATION OF A/D AND D/A CONVERTER:

84

FUNCTIONAL DIAGRAM OF ADC

85

Expt. No. :14 Date AIM: :

STUDY OF ANALOG TO DIGITAL CONVERTER

Realization of circuit for digital conversion. THEORY: The operation of any digital communication system is based upon analog to digital and digital to analog conversion .The figure shows the typical application within A->D and D->A conversion is used .The analog signal obtained from the transducer is band limited by intialsing filter .The signal is then sampled at a frequency rate more than twice the maximum frequency of the band limited signal .The sampled signal has to be held constant while conversion is taking place in A/D converter. This requires the ADC output is a sequence in binary digit .The micro computer (or) digital signal processor performs. The numerical calculations of the desired controls algorithm. The D/A convertor is usually operated at the same frequency as the ADC. The output is passed through a smoothing filter to reduce the effect of quantization noise. Both ADC and DAC are also known as data convertors and are available in Ic form. It may be mentioned here that for slowly varying signal sometimes sample and hold circuit may be avoided without considerable error. The A/D conversion usually makes use of a D/a convertors. So we shall first discuss DAC followed by ADC. A/D CONVERTOR: The Block schematic of ADC is shown in figure. It provides the function just opposite to that of a DAC. It accepts analog input voltage Vo and produces an output binary words d1,d2,..dn of
1 2 n function value D1 so that D = d 1 2 + d 2 2 + .............. + d n 2

Where the d1 is the most significant bit and dn is the least significant bit. An ADC usually has 2 additional control lines. The start input to tell ADC when to start the conversion and the EOC output to announce when the conversion is complete. Depending upon the type of applications ADC are designed for microprocessor interfacing (or) to directly drive LCD (or) LED displays. ADCS compares a given analog signal with the internally generated equivalent signal. This groups includes, Flash (comparator) type convertor Counter type convert tracking type convertor Successive approximation type convertor. TRACKING A/D CONVERTER:
86

FUNCTIONAL DIAGRAM OF SUCCESSIVE APPROXIMATION ADC:

Integrating type ADCS perform conversion in an indirect manner by first changing the analog input signal to a linear function of time or frequency and then to a digital code. The two most widly used integrating type convertors are
87

1. Charging balancing ADC 2. Dual slope ADC The most commonly used ADCS are successive approximation and the integration type. The successive approximation and the integration ADCS are used in application such as data loggers instrumentations with conversion speed is important. The successive approximation and comparator type are faster but generally less accurate than integrating type convertors. The flash type is expensive for high degree of accuracy. The integrating type convertors are used to applications such as digital meter, panel meter and monitoring system were the conversion accuracy is critical. Successive Approximation convertor: The successive approximation technique used a very efficient code searh technology strategy to complete in-bit conversion in just n-clock periods. An light but convertor would require right clock pulses to obtain a digital output as shown in figure. The circuit uses a successive approximation register (SAR) to find the required value of each bit by trail and error. The circuit operates as follows with the arrival of the state command, the SAR sets the MSB=d1=1 with all other bits to zero that the DAC is greater than the DAC output Vo then 10000000 is less than the correct digital representation. The MSB is left at 1 and the further (or) next lower significant bit is made 1 and further tested. However if va is less than DAc output the 1000000 is greater than the current correct digital representation. So reset MSB 0 and goto the next lower significant bit. This procedure is repeated for all bits, one at an time until all bit position has then tested. Whenever the DAC output crosses Vo the comparator changes state and this can be taken as the end of conversion(EOC) command. The following table shows the typical conversion sequence. The figure shows the corresponding waveforms. It can be sum that D/A output voltage becomes successively closer to the actual analog input voltage. It requires eight pulses to establish the accurate output regardless of the value of the accurate output regardless of the value of the analog input from load the output registers and reinitializes the circuit.

88

Correct digit representation 11010100

Successive approximation registor output Vd at different stages in conversion 10000000

Comparator output 1(initial o/p)

89

11000000 11100000 11010000 11011000 11010100 11010110 11010110 11010101 110101010 1 0 1 0 1 0 0 0

A comparison of the need of an 8 bit tracking ADC and an 8 bit successive approximation. ADC is made in figure. Given the same clock frequency, we see that the tracking circuit is faster only for small changes in the output. In general the successive approximation technique is more versa late and superior to all other input circuits discussed so far, successive approximation ADCS are available as self contained ICs. The AD 7582 a 28 pin dual line cases package is a 2 bit A/D convertor using successive approximation technique.

RESULT: Thus the realization of circuit for conversion was studied.

BLOCK DIAGRAM OF PLL:

90

PIN DIAGRAM:

91

Expt. No. :15 Date AIM: :

STUDY OF PLL

To study PLL IC and frequency multiplication using NE/SE 565 PLL IC. BASIC PRINCIPLES: The basic principles of schematic diagram of the PLL is shown in fig. This feedback system consists of 1. Phase detector comparator 2. A low pass filter 3. An error amplifier
4. A voltage control oscillator[ VCD]

A VCD is a free running multivibrator and operates at a set frequency Fo. This frequency is determined by an internal timing capacitor and external series resistors. It can also the shifted to either side by applying a dc voltage Vc to an appropriate terminal of the IC. The frequency deviation is directly proportional to the control voltage.

If an input signal Vs of frequency is applied to PLL, the phase detector compares the phase and frequency of the incoming signal to that of the Output Vo of the VCD.

If the two signal Vs of frequency and phase an error voltage is generated. The phase detector is basically a multiplier and process the sum [Fo+F3] and difference [Fs-Fo] components at its output. The high frequency components [Fs+Fo] is removed by the low pass filter and difference frequency component is amplified and the applied as control voltage Vc to Vco. The signal Vc shifts the Vco frequency in a direction to reduce the frequency difference between F3 and fo. Once this action starts we say that the signal is the capture range. The circuit is said to be locked. Once the locked, the O/P frequency to of Vco is identical to F3 inspect for a finite phase difference F.
92

Free Running: 1. Capture 2. Locked (or) tracking The graph shows the capture transient as capture starts small sine wave appears. This is due to the difference frequency between the Vco and the I/P signal. Each successive cycle causes the Vco frequency becomes smaller and a large dc component is passed by the filter shifting the Vco locks on to the signal and difference frequency is dc. The low pass fiter controls the difference range. If Vco frequency is far away the beat frequency will be high to pass through the filter and the PLL will not respond we say thet the signal is not of the capture band. The Vco can trans, thus tracking range. NE/SE 565 BLOCK DIAGRAM:

FREQUENCY MULTIPLIER USING IC PLL:

93

LOCK IN RANGE: Once the PLL is locked it can track frequency changes in the incoming signal. The range of frequency which the PLL can maintain lock with the incoming signal is called lock in range or tracking range. The lock range is usually expressed as a percentage of Fo , the Vco Frequency.

CAPTURE RANGE: The range of frequencies over the PLl can acquire lock with an input signal is called the capture range. This parameter is also expressed as percentage of Fo.

PULL IN TIME:

94

The total time taken by the PLL to establish the lock is called pull in time. This depends on the initial phase and frequency difference between the two signals as well as on the over all loop gain loop filter characteristics.

IC PLL 565: 565 is available as a 14-pin dip package as 10-pin metal can package. The pin configuration and the block diagram are shown in figure. The output frequency of the Vco is given gy the equation Fo=0.25/RtCt Hz, where Rt and Ct are the external resistor and capacitor connected to 8 pin and pin 8. The Vco free running frequency is adjusted with Rt and Ct to be at the centre of the input frequency range. It may be seen the input Frequency range. That phase locked loop is internally broken between the Vco output and the phase comparator so as the compare fo with input signal Fo A capacitor C is connected between pin 7 and pin 10 and made a low pass filter with the internal resistance of 3.6ohm.

PLL APPLICATIONS: The output from a PLL system can be obtained either as the voltage signal Vce corresponding to the error voltage in the feedback loop (or) as a frequency signal to Vco output terminal. The voltage output is used in frequency dissemination application whereas the frequency output is used in signal conditioning, frequency synthesis (or) clock recovery applications.

FREQUENCY MULTIPLICATION DIVISION : The figure shows the block diagram of a frequency multiplier using PLL. A divided by N network is inserted between the Vco output and the phase comparator input frequency Fo is given by Fo=nfs.The multiplication factor can be obtained by selecting a proper scaling factor N of the counter frequency multiplication can also be obtained by using PLL in its harmonic locking mode.If the input signal is such in harmonic then Vco can be directly locked to the Nth harmonic of the input signal conditioning without any frequency divider in between affixture locking may not take place for high values of n Typically n is kept less than 10.

95

96

PROCEDURE: 1. 2.
3.

Make the connections as per the circuit diagram. Set the input signal at Vpp square wave at 500Hz. Vary the Vco frequency by adjusting the 20K ohms potentiometer till the the PLL is locked. Measure the output frequency. It should be five times the input frequency.

4.

Repeat step 2,3 for input frequency of 1KHZ and 1.5KHZ.

97

RESULT: Thus the PLL IC and frequency multiplication using NE/SE 565 PLL IC were studied.
98

VOLTAGE CONTROLLED OSCILLATOR: PIN CONFIGURATION:

BLOCK DIAGRAM:

99

Expt. No. :16 Date AIM: :

STUDY OF VCO

To study VCO and voltage of frequency characteristics of NE/SE 566 IC. THEORY: VOLTAGE CONTROL OSCILLATOR: IC 566: The common type of VCO available in IC form is NE/SE 566. The pin configuration and bias block diagram of 566 VCO are shown in the figure referring to the figure timing capacitor. Ct is linearly charged or discharged by the constant current source as in K. The amount of current VC applied at the modulating input (or) by changing the timing resistor Ri , external to IC chip. The

100

voltage at pin 6 is held at the voltage as pin 5. Thus if the modulating voltage at pin 5 is increased, resulting in low voltage, across Rt and thereby decreasing the charging current. The voltage across the capacitor CT is applied to the inverting input terminal of the Schmitt trigger. A2 via after amplified A1. The output using the Schmitt trigger is designed to VCC and 0.5VCC. If Ra and Rb in the positive feedback loop the voltage swings from 0.5Vcc to 0.25Vcc. When the capacitor circuits exceeds 0.5Vcc during charging, the output of Schmitt trigger goes low. The capacitor now discharges and when it is 0.25 Vcc the output of Schmitt trigger goes high. Since the source and sink current are equal the capacitor charges and discharges for the same amount of time. This gives a triangular voltage waveform across CT which is also available at pin 4. The square wave output of the Schmitt trigger is inverted by inverter A3 and is available at pin 3. The output waveform is shown in figure. The output frequency is f o = 2(VCC VC ) / ( CT RT VCC ) . VOLTAGE TO FREQUENCY CONVERSION FACTOR: A parameter of importance of VCO is voltage to frequency conversion factor KV and is designed as KV=f01VC. Here VC is the modulation voltage required to produce the frequency shift f0. For a VCO if the original frequency shift is f0 and new frequency is f1 then f0=f1-f0 V=f0CTRTVco/2 VC=f0VCC/sf0 OUTPUT WAVEFORM:

101

TYPICAL CONNECTION DIAGRAM:

102

RESULT: Thus the VCO and Voltage of frequency characteristics of NE/SE IC 566 were studied.

103